1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017-2020, 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef __MAIN_H__ 8 #define __MAIN_H__ 9 10 #include <linux/irqreturn.h> 11 #include <linux/kobject.h> 12 #include <linux/platform_device.h> 13 #include <linux/ipc_logging.h> 14 #include <linux/power_supply.h> 15 #if IS_ENABLED(CONFIG_MSM_QMP) 16 #include <linux/mailbox/qmp.h> 17 #endif 18 #ifdef CONFIG_CNSS_OUT_OF_TREE 19 #include "icnss2.h" 20 #else 21 #include <soc/qcom/icnss2.h> 22 #endif 23 #include "wlan_firmware_service_v01.h" 24 #include "cnss_prealloc.h" 25 #include "cnss_common.h" 26 #include <linux/mailbox_client.h> 27 #include <linux/timer.h> 28 29 #define THERMAL_NAME_LENGTH 20 30 #define ICNSS_SMEM_VALUE_MASK 0xFFFFFFFF 31 #define ICNSS_SMEM_SEQ_NO_POS 16 32 #define QCA6750_PATH_PREFIX "qca6750/" 33 #define ADRASTEA_PATH_PREFIX "adrastea/" 34 #define WCN6450_PATH_PREFIX "wcn6450/" 35 #define ICNSS_MAX_FILE_NAME 35 36 #define ICNSS_PCI_EP_WAKE_OFFSET 4 37 #define ICNSS_DISABLE_M3_SSR 0 38 #define ICNSS_ENABLE_M3_SSR 1 39 #define WLAN_RF_SLATE 0 40 #define WLAN_RF_APACHE 1 41 42 extern uint64_t dynamic_feature_mask; 43 44 enum icnss_bdf_type { 45 ICNSS_BDF_BIN, 46 ICNSS_BDF_ELF, 47 ICNSS_BDF_REGDB = 4, 48 }; 49 50 struct icnss_control_params { 51 unsigned long quirks; 52 unsigned int qmi_timeout; 53 unsigned int bdf_type; 54 }; 55 56 enum icnss_driver_event_type { 57 ICNSS_DRIVER_EVENT_SERVER_ARRIVE, 58 ICNSS_DRIVER_EVENT_SERVER_EXIT, 59 ICNSS_DRIVER_EVENT_FW_READY_IND, 60 ICNSS_DRIVER_EVENT_REGISTER_DRIVER, 61 ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER, 62 ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN, 63 ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND, 64 ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN, 65 ICNSS_DRIVER_EVENT_IDLE_RESTART, 66 ICNSS_DRIVER_EVENT_FW_INIT_DONE_IND, 67 ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM, 68 ICNSS_DRIVER_EVENT_QDSS_TRACE_SAVE, 69 ICNSS_DRIVER_EVENT_QDSS_TRACE_FREE, 70 ICNSS_DRIVER_EVENT_M3_DUMP_UPLOAD_REQ, 71 ICNSS_DRIVER_EVENT_IMS_WFC_CALL_IND, 72 ICNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND, 73 ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA, 74 ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL, 75 ICNSS_DRIVER_EVENT_MAX, 76 }; 77 78 enum icnss_soc_wake_event_type { 79 ICNSS_SOC_WAKE_REQUEST_EVENT, 80 ICNSS_SOC_WAKE_RELEASE_EVENT, 81 ICNSS_SOC_WAKE_EVENT_MAX, 82 }; 83 84 struct icnss_event_server_arrive_data { 85 unsigned int node; 86 unsigned int port; 87 }; 88 89 struct icnss_event_pd_service_down_data { 90 bool crashed; 91 bool fw_rejuvenate; 92 }; 93 94 struct icnss_driver_event { 95 struct list_head list; 96 enum icnss_driver_event_type type; 97 bool sync; 98 struct completion complete; 99 int ret; 100 void *data; 101 }; 102 103 struct icnss_soc_wake_event { 104 struct list_head list; 105 enum icnss_soc_wake_event_type type; 106 bool sync; 107 struct completion complete; 108 int ret; 109 void *data; 110 }; 111 112 enum icnss_driver_state { 113 ICNSS_WLFW_CONNECTED, 114 ICNSS_POWER_ON, 115 ICNSS_FW_READY, 116 ICNSS_DRIVER_PROBED, 117 ICNSS_FW_TEST_MODE, 118 ICNSS_PM_SUSPEND, 119 ICNSS_PM_SUSPEND_NOIRQ, 120 ICNSS_SSR_REGISTERED, 121 ICNSS_PDR_REGISTERED, 122 ICNSS_PD_RESTART, 123 ICNSS_WLFW_EXISTS, 124 ICNSS_SHUTDOWN_DONE, 125 ICNSS_HOST_TRIGGERED_PDR, 126 ICNSS_FW_DOWN, 127 ICNSS_DRIVER_UNLOADING, 128 ICNSS_REJUVENATE, 129 ICNSS_MODE_ON, 130 ICNSS_BLOCK_SHUTDOWN, 131 ICNSS_PDR, 132 ICNSS_IMS_CONNECTED, 133 ICNSS_DEL_SERVER, 134 ICNSS_COLD_BOOT_CAL, 135 ICNSS_QMI_DMS_CONNECTED, 136 ICNSS_SLATE_SSR_REGISTERED, 137 ICNSS_SLATE_UP, 138 ICNSS_SLATE_READY, 139 ICNSS_LOW_POWER, 140 }; 141 142 struct ce_irq_list { 143 int irq; 144 irqreturn_t (*handler)(int irq, void *priv); 145 }; 146 147 struct icnss_vreg_cfg { 148 const char *name; 149 u32 min_uv; 150 u32 max_uv; 151 u32 load_ua; 152 u32 delay_us; 153 u32 need_unvote; 154 bool required; 155 bool is_supported; 156 }; 157 158 struct icnss_vreg_info { 159 struct list_head list; 160 struct regulator *reg; 161 struct icnss_vreg_cfg cfg; 162 u32 enabled; 163 }; 164 165 struct icnss_cpr_info { 166 const char *vreg_ol_cpr; 167 u32 voltage; 168 }; 169 170 enum icnss_vreg_type { 171 ICNSS_VREG_PRIM, 172 }; 173 struct icnss_clk_cfg { 174 const char *name; 175 u32 freq; 176 u32 required; 177 }; 178 179 struct icnss_battery_level { 180 int lower_battery_threshold; 181 int ldo_voltage; 182 }; 183 184 struct icnss_clk_info { 185 struct list_head list; 186 struct clk *clk; 187 struct icnss_clk_cfg cfg; 188 u32 enabled; 189 }; 190 191 struct icnss_fw_mem { 192 size_t size; 193 void *va; 194 phys_addr_t pa; 195 u8 valid; 196 u32 type; 197 unsigned long attrs; 198 }; 199 200 enum icnss_smp2p_msg_id { 201 ICNSS_RESET_MSG, 202 ICNSS_POWER_SAVE_ENTER, 203 ICNSS_POWER_SAVE_EXIT, 204 ICNSS_TRIGGER_SSR, 205 ICNSS_SOC_WAKE_REQ, 206 ICNSS_SOC_WAKE_REL, 207 ICNSS_PCI_EP_POWER_SAVE_ENTER, 208 ICNSS_PCI_EP_POWER_SAVE_EXIT, 209 }; 210 211 struct icnss_subsys_restart_level_data { 212 uint8_t restart_level; 213 }; 214 215 struct icnss_stats { 216 struct { 217 uint32_t posted; 218 uint32_t processed; 219 } events[ICNSS_DRIVER_EVENT_MAX]; 220 221 struct { 222 u32 posted; 223 u32 processed; 224 } soc_wake_events[ICNSS_SOC_WAKE_EVENT_MAX]; 225 226 struct { 227 uint32_t request; 228 uint32_t free; 229 uint32_t enable; 230 uint32_t disable; 231 } ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS]; 232 233 struct { 234 uint32_t pdr_fw_crash; 235 uint32_t pdr_host_error; 236 uint32_t root_pd_crash; 237 uint32_t root_pd_shutdown; 238 } recovery; 239 240 uint32_t pm_suspend; 241 uint32_t pm_suspend_err; 242 uint32_t pm_resume; 243 uint32_t pm_resume_err; 244 uint32_t pm_suspend_noirq; 245 uint32_t pm_suspend_noirq_err; 246 uint32_t pm_resume_noirq; 247 uint32_t pm_resume_noirq_err; 248 uint32_t pm_stay_awake; 249 uint32_t pm_relax; 250 251 uint32_t ind_register_req; 252 uint32_t ind_register_resp; 253 uint32_t ind_register_err; 254 uint32_t msa_info_req; 255 uint32_t msa_info_resp; 256 uint32_t msa_info_err; 257 uint32_t msa_ready_req; 258 uint32_t msa_ready_resp; 259 uint32_t msa_ready_err; 260 uint32_t msa_ready_ind; 261 uint32_t cap_req; 262 uint32_t cap_resp; 263 uint32_t cap_err; 264 uint32_t pin_connect_result; 265 uint32_t cfg_req; 266 uint32_t cfg_resp; 267 uint32_t cfg_req_err; 268 uint32_t mode_req; 269 uint32_t mode_resp; 270 uint32_t mode_req_err; 271 uint32_t ini_req; 272 uint32_t ini_resp; 273 uint32_t ini_req_err; 274 u32 rejuvenate_ind; 275 uint32_t rejuvenate_ack_req; 276 uint32_t rejuvenate_ack_resp; 277 uint32_t rejuvenate_ack_err; 278 uint32_t device_info_req; 279 uint32_t device_info_resp; 280 uint32_t device_info_err; 281 u32 exit_power_save_req; 282 u32 exit_power_save_resp; 283 u32 exit_power_save_err; 284 u32 enter_power_save_req; 285 u32 enter_power_save_resp; 286 u32 enter_power_save_err; 287 u32 soc_wake_req; 288 u32 soc_wake_resp; 289 u32 soc_wake_err; 290 u32 restart_level_req; 291 u32 restart_level_resp; 292 u32 restart_level_err; 293 }; 294 295 #define WLFW_MAX_TIMESTAMP_LEN 32 296 #define WLFW_MAX_BUILD_ID_LEN 128 297 #define WLFW_MAX_NUM_MEMORY_REGIONS 2 298 #define WLFW_FUNCTION_NAME_LEN 129 299 #define WLFW_MAX_DATA_SIZE 6144 300 #define WLFW_MAX_STR_LEN 16 301 #define WLFW_MAX_NUM_CE 12 302 #define WLFW_MAX_NUM_SVC 24 303 #define WLFW_MAX_NUM_SHADOW_REG 24 304 #define WLFW_MAX_HANG_EVENT_DATA_SIZE 400 305 306 struct wlfw_rf_chip_info { 307 uint32_t chip_id; 308 uint32_t chip_family; 309 }; 310 311 struct wlfw_rf_board_info { 312 uint32_t board_id; 313 }; 314 315 struct wlfw_fw_version_info { 316 uint32_t fw_version; 317 char fw_build_timestamp[WLFW_MAX_TIMESTAMP_LEN + 1]; 318 }; 319 320 struct icnss_mem_region_info { 321 uint64_t reg_addr; 322 uint32_t size; 323 uint8_t secure_flag; 324 }; 325 326 struct icnss_msi_user { 327 char *name; 328 int num_vectors; 329 u32 base_vector; 330 }; 331 332 struct icnss_msi_config { 333 int total_vectors; 334 int total_users; 335 struct icnss_msi_user *users; 336 }; 337 338 struct icnss_thermal_cdev { 339 struct list_head tcdev_list; 340 int tcdev_id; 341 unsigned long curr_thermal_state; 342 unsigned long max_thermal_state; 343 struct device_node *dev_node; 344 struct thermal_cooling_device *tcdev; 345 }; 346 347 enum smp2p_out_entry { 348 ICNSS_SMP2P_OUT_POWER_SAVE, 349 ICNSS_SMP2P_OUT_SOC_WAKE, 350 ICNSS_SMP2P_OUT_EP_POWER_SAVE, 351 ICNSS_SMP2P_OUT_MAX 352 }; 353 354 static const char * const icnss_smp2p_str[] = { 355 [ICNSS_SMP2P_OUT_POWER_SAVE] = "wlan-smp2p-out", 356 [ICNSS_SMP2P_OUT_SOC_WAKE] = "wlan-soc-wake-smp2p-out", 357 [ICNSS_SMP2P_OUT_EP_POWER_SAVE] = "wlan-ep-powersave-smp2p-out", 358 }; 359 360 struct smp2p_out_info { 361 unsigned short seq; 362 unsigned int smem_bit; 363 struct qcom_smem_state *smem_state; 364 }; 365 366 struct icnss_dms_data { 367 u8 mac_valid; 368 u8 nv_mac_not_prov; 369 u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01]; 370 }; 371 372 struct icnss_ramdump_info { 373 int minor; 374 char name[32]; 375 struct device *dev; 376 }; 377 378 struct icnss_priv { 379 uint32_t magic; 380 struct platform_device *pdev; 381 struct icnss_driver_ops *ops; 382 struct ce_irq_list ce_irq_list[ICNSS_MAX_IRQ_REGISTRATIONS]; 383 struct list_head vreg_list; 384 struct list_head clk_list; 385 struct icnss_cpr_info cpr_info; 386 unsigned long device_id; 387 struct icnss_msi_config *msi_config; 388 u32 msi_base_data; 389 struct icnss_control_params ctrl_params; 390 u8 cal_done; 391 u8 use_prefix_path; 392 u32 ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS]; 393 u32 srng_irqs[IWCN_MAX_IRQ_REGISTRATIONS]; 394 phys_addr_t mem_base_pa; 395 void __iomem *mem_base_va; 396 u32 mem_base_size; 397 phys_addr_t mhi_state_info_pa; 398 void __iomem *mhi_state_info_va; 399 u32 mhi_state_info_size; 400 struct iommu_domain *iommu_domain; 401 dma_addr_t smmu_iova_start; 402 size_t smmu_iova_len; 403 dma_addr_t smmu_iova_ipa_start; 404 dma_addr_t smmu_iova_ipa_current; 405 size_t smmu_iova_ipa_len; 406 struct qmi_handle qmi; 407 struct qmi_handle qmi_dms; 408 struct qmi_handle ims_qmi; 409 struct qmi_txn ims_async_txn; 410 struct list_head event_list; 411 struct list_head soc_wake_msg_list; 412 spinlock_t event_lock; 413 spinlock_t soc_wake_msg_lock; 414 struct work_struct event_work; 415 struct work_struct fw_recv_msg_work; 416 struct work_struct soc_wake_msg_work; 417 struct workqueue_struct *event_wq; 418 struct workqueue_struct *soc_wake_wq; 419 phys_addr_t msa_pa; 420 phys_addr_t msi_addr_pa; 421 dma_addr_t msi_addr_iova; 422 uint32_t msa_mem_size; 423 void *msa_va; 424 unsigned long state; 425 struct wlfw_rf_chip_info chip_info; 426 uint32_t board_id; 427 uint32_t soc_id; 428 struct wlfw_fw_version_info fw_version_info; 429 char fw_build_id[WLFW_MAX_BUILD_ID_LEN + 1]; 430 u32 pwr_pin_result; 431 u32 phy_io_pin_result; 432 u32 rf_pin_result; 433 uint32_t nr_mem_region; 434 struct icnss_mem_region_info 435 mem_region[WLFW_MAX_NUM_MEMORY_REGIONS]; 436 struct icnss_dev_mem_info dev_mem_info[ICNSS_MAX_DEV_MEM_NUM]; 437 struct dentry *root_dentry; 438 spinlock_t on_off_lock; 439 struct icnss_stats stats; 440 void *modem_notify_handler; 441 void *wpss_notify_handler; 442 void *wpss_early_notify_handler; 443 struct notifier_block modem_ssr_nb; 444 struct notifier_block wpss_ssr_nb; 445 struct notifier_block wpss_early_ssr_nb; 446 void *slate_notify_handler; 447 struct notifier_block slate_ssr_nb; 448 uint32_t diag_reg_read_addr; 449 uint32_t diag_reg_read_mem_type; 450 uint32_t diag_reg_read_len; 451 uint8_t *diag_reg_read_buf; 452 atomic_t pm_count; 453 struct icnss_ramdump_info *msa0_dump_dev; 454 struct icnss_ramdump_info *m3_dump_phyareg; 455 struct icnss_ramdump_info *m3_dump_phydbg; 456 struct icnss_ramdump_info *m3_dump_wmac0reg; 457 struct icnss_ramdump_info *m3_dump_wcssdbg; 458 struct icnss_ramdump_info *m3_dump_phyapdmem; 459 bool force_err_fatal; 460 bool allow_recursive_recovery; 461 bool early_crash_ind; 462 u8 cause_for_rejuvenation; 463 u8 requesting_sub_system; 464 u16 line_number; 465 struct mutex dev_lock; 466 uint32_t fw_error_fatal_irq; 467 uint32_t fw_early_crash_irq; 468 struct smp2p_out_info smp2p_info[ICNSS_SMP2P_OUT_MAX]; 469 struct completion unblock_shutdown; 470 char function_name[WLFW_FUNCTION_NAME_LEN + 1]; 471 bool is_ssr; 472 bool smmu_s1_enable; 473 struct kobject *icnss_kobject; 474 struct rproc *rproc; 475 atomic_t is_shutdown; 476 u32 qdss_mem_seg_len; 477 struct icnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01]; 478 void *get_info_cb_ctx; 479 int (*get_info_cb)(void *ctx, void *event, int event_len); 480 atomic_t soc_wake_ref_count; 481 phys_addr_t hang_event_data_pa; 482 void __iomem *hang_event_data_va; 483 uint16_t hang_event_data_len; 484 void *hang_event_data; 485 struct list_head icnss_tcdev_list; 486 struct mutex tcdev_lock; 487 bool is_chain1_supported; 488 u32 hw_trc_override; 489 struct icnss_dms_data dms; 490 u8 use_nv_mac; 491 struct pdr_handle *pdr_handle; 492 struct pdr_service *pdr_service; 493 bool root_pd_shutdown; 494 struct mbox_client mbox_client_data; 495 struct mbox_chan *mbox_chan; 496 #if IS_ENABLED(CONFIG_MSM_QMP) 497 struct qmp *qmp; 498 #endif 499 bool use_direct_qmp; 500 const char **pdc_init_table; 501 int pdc_init_table_len; 502 u32 wlan_en_delay_ms; 503 u32 wlan_en_delay_ms_user; 504 struct class *icnss_ramdump_class; 505 dev_t icnss_ramdump_dev; 506 struct completion smp2p_soc_wake_wait; 507 uint32_t fw_soc_wake_ack_irq; 508 char foundry_name; 509 bool bdf_download_support; 510 bool psf_supported; 511 struct notifier_block psf_nb; 512 struct power_supply *batt_psy; 513 int last_updated_voltage; 514 struct work_struct soc_update_work; 515 struct workqueue_struct *soc_update_wq; 516 unsigned long device_config; 517 bool wpss_supported; 518 u8 low_power_support; 519 bool is_rf_subtype_valid; 520 u32 rf_subtype; 521 u8 is_slate_rfa; 522 struct completion slate_boot_complete; 523 #ifdef CONFIG_SLATE_MODULE_ENABLED 524 struct seb_notif_info *seb_handle; 525 struct notifier_block seb_nb; 526 #endif 527 struct timer_list recovery_timer; 528 struct timer_list wpss_ssr_timer; 529 bool wpss_self_recovery_enabled; 530 enum icnss_rd_card_chain_cap rd_card_chain_cap; 531 enum icnss_phy_he_channel_width_cap phy_he_channel_width_cap; 532 enum icnss_phy_qam_cap phy_qam_cap; 533 bool rproc_fw_download; 534 struct wlchip_serial_id_v01 serial_id; 535 }; 536 537 struct icnss_reg_info { 538 uint32_t mem_type; 539 uint32_t reg_offset; 540 uint32_t data_len; 541 }; 542 543 void icnss_free_qdss_mem(struct icnss_priv *priv); 544 char *icnss_driver_event_to_str(enum icnss_driver_event_type type); 545 int icnss_call_driver_uevent(struct icnss_priv *priv, 546 enum icnss_uevent uevent, void *data); 547 int icnss_driver_event_post(struct icnss_priv *priv, 548 enum icnss_driver_event_type type, 549 u32 flags, void *data); 550 void icnss_allow_recursive_recovery(struct device *dev); 551 void icnss_disallow_recursive_recovery(struct device *dev); 552 char *icnss_soc_wake_event_to_str(enum icnss_soc_wake_event_type type); 553 int icnss_soc_wake_event_post(struct icnss_priv *priv, 554 enum icnss_soc_wake_event_type type, 555 u32 flags, void *data); 556 int icnss_get_iova(struct icnss_priv *priv, u64 *addr, u64 *size); 557 int icnss_get_iova_ipa(struct icnss_priv *priv, u64 *addr, u64 *size); 558 int icnss_update_cpr_info(struct icnss_priv *priv); 559 void icnss_add_fw_prefix_name(struct icnss_priv *priv, char *prefix_name, 560 char *name); 561 int icnss_aop_interface_init(struct icnss_priv *priv); 562 void icnss_aop_interface_deinit(struct icnss_priv *priv); 563 int icnss_aop_pdc_reconfig(struct icnss_priv *priv); 564 void icnss_power_misc_params_init(struct icnss_priv *priv); 565 void icnss_recovery_timeout_hdlr(struct timer_list *t); 566 void icnss_wpss_ssr_timeout_hdlr(struct timer_list *t); 567 #endif 568 569