1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_params.h" 23 #include "intel_display_power.h" 24 #include "intel_dpll_mgr.h" 25 #include "intel_fbc.h" 26 #include "intel_global_state.h" 27 #include "intel_gmbus.h" 28 #include "intel_opregion.h" 29 #include "intel_dmc_wl.h" 30 #include "intel_wm_types.h" 31 32 struct task_struct; 33 34 struct drm_i915_private; 35 struct drm_property; 36 struct drm_property_blob; 37 struct i915_audio_component; 38 struct i915_hdcp_arbiter; 39 struct intel_atomic_state; 40 struct intel_audio_funcs; 41 struct intel_cdclk_funcs; 42 struct intel_cdclk_vals; 43 struct intel_color_funcs; 44 struct intel_crtc; 45 struct intel_crtc_state; 46 struct intel_dmc; 47 struct intel_dpll_funcs; 48 struct intel_dpll_mgr; 49 struct intel_fbdev; 50 struct intel_fdi_funcs; 51 struct intel_hotplug_funcs; 52 struct intel_initial_plane_config; 53 struct intel_opregion; 54 struct intel_overlay; 55 56 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 57 #define I915_NUM_QGV_POINTS 8 58 59 /* Amount of PSF GV points, BSpec precisely defines this */ 60 #define I915_NUM_PSF_GV_POINTS 3 61 62 struct intel_display_funcs { 63 /* 64 * Returns the active state of the crtc, and if the crtc is active, 65 * fills out the pipe-config with the hw state. 66 */ 67 bool (*get_pipe_config)(struct intel_crtc *, 68 struct intel_crtc_state *); 69 void (*get_initial_plane_config)(struct intel_crtc *, 70 struct intel_initial_plane_config *); 71 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 72 const struct intel_initial_plane_config *plane_config); 73 void (*crtc_enable)(struct intel_atomic_state *state, 74 struct intel_crtc *crtc); 75 void (*crtc_disable)(struct intel_atomic_state *state, 76 struct intel_crtc *crtc); 77 void (*commit_modeset_enables)(struct intel_atomic_state *state); 78 }; 79 80 /* functions used for watermark calcs for display. */ 81 struct intel_wm_funcs { 82 /* update_wm is for legacy wm management */ 83 void (*update_wm)(struct drm_i915_private *dev_priv); 84 int (*compute_pipe_wm)(struct intel_atomic_state *state, 85 struct intel_crtc *crtc); 86 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 87 struct intel_crtc *crtc); 88 void (*initial_watermarks)(struct intel_atomic_state *state, 89 struct intel_crtc *crtc); 90 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 91 struct intel_crtc *crtc); 92 void (*optimize_watermarks)(struct intel_atomic_state *state, 93 struct intel_crtc *crtc); 94 int (*compute_global_watermarks)(struct intel_atomic_state *state); 95 void (*get_hw_state)(struct drm_i915_private *i915); 96 }; 97 98 struct intel_audio_state { 99 struct intel_encoder *encoder; 100 u8 eld[MAX_ELD_BYTES]; 101 }; 102 103 struct intel_audio { 104 /* hda/i915 audio component */ 105 struct i915_audio_component *component; 106 bool component_registered; 107 /* mutex for audio/video sync */ 108 struct mutex mutex; 109 int power_refcount; 110 u32 freq_cntrl; 111 112 /* current audio state for the audio component hooks */ 113 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 114 115 /* necessary resource sharing with HDMI LPE audio driver. */ 116 struct { 117 struct platform_device *platdev; 118 int irq; 119 } lpe; 120 }; 121 122 /* 123 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 124 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 125 * dpll, because on some platforms plls share registers. 126 */ 127 struct intel_dpll { 128 struct mutex lock; 129 130 int num_shared_dpll; 131 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 132 const struct intel_dpll_mgr *mgr; 133 134 struct { 135 int nssc; 136 int ssc; 137 } ref_clks; 138 139 /* 140 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 141 */ 142 u8 pch_ssc_use; 143 }; 144 145 struct intel_frontbuffer_tracking { 146 spinlock_t lock; 147 148 /* 149 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 150 * scheduled flips. 151 */ 152 unsigned busy_bits; 153 unsigned flip_bits; 154 }; 155 156 struct intel_hotplug { 157 struct delayed_work hotplug_work; 158 159 const u32 *hpd, *pch_hpd; 160 161 struct { 162 unsigned long last_jiffies; 163 int count; 164 enum { 165 HPD_ENABLED = 0, 166 HPD_DISABLED = 1, 167 HPD_MARK_DISABLED = 2 168 } state; 169 } stats[HPD_NUM_PINS]; 170 u32 event_bits; 171 u32 retry_bits; 172 struct delayed_work reenable_work; 173 174 u32 long_port_mask; 175 u32 short_port_mask; 176 struct work_struct dig_port_work; 177 178 struct work_struct poll_init_work; 179 bool poll_enabled; 180 181 /* 182 * Queuing of hotplug_work, reenable_work and poll_init_work is 183 * enabled. Protected by drm_i915_private::irq_lock. 184 */ 185 bool detection_work_enabled; 186 187 unsigned int hpd_storm_threshold; 188 /* Whether or not to count short HPD IRQs in HPD storms */ 189 u8 hpd_short_storm_enabled; 190 191 /* Last state reported by oob_hotplug_event for each encoder */ 192 unsigned long oob_hotplug_last_state; 193 194 /* 195 * if we get a HPD irq from DP and a HPD irq from non-DP 196 * the non-DP HPD could block the workqueue on a mode config 197 * mutex getting, that userspace may have taken. However 198 * userspace is waiting on the DP workqueue to run which is 199 * blocked behind the non-DP one. 200 */ 201 struct workqueue_struct *dp_wq; 202 203 /* 204 * Flag to track if long HPDs need not to be processed 205 * 206 * Some panels generate long HPDs while keep connected to the port. 207 * This can cause issues with CI tests results. In CI systems we 208 * don't expect to disconnect the panels and could ignore the long 209 * HPDs generated from the faulty panels. This flag can be used as 210 * cue to ignore the long HPDs and can be set / unset using debugfs. 211 */ 212 bool ignore_long_hpd; 213 }; 214 215 struct intel_vbt_data { 216 /* bdb version */ 217 u16 version; 218 219 /* Feature bits */ 220 unsigned int int_tv_support:1; 221 unsigned int int_crt_support:1; 222 unsigned int lvds_use_ssc:1; 223 unsigned int int_lvds_support:1; 224 unsigned int display_clock_mode:1; 225 unsigned int fdi_rx_polarity_inverted:1; 226 int lvds_ssc_freq; 227 enum drm_panel_orientation orientation; 228 229 bool override_afc_startup; 230 u8 override_afc_startup_val; 231 232 int crt_ddc_pin; 233 234 struct list_head display_devices; 235 struct list_head bdb_blocks; 236 237 struct sdvo_device_mapping { 238 u8 initialized; 239 u8 dvo_port; 240 u8 target_addr; 241 u8 dvo_wiring; 242 u8 i2c_pin; 243 u8 ddc_pin; 244 } sdvo_mappings[2]; 245 }; 246 247 struct intel_wm { 248 /* 249 * Raw watermark latency values: 250 * in 0.1us units for WM0, 251 * in 0.5us units for WM1+. 252 */ 253 /* primary */ 254 u16 pri_latency[5]; 255 /* sprite */ 256 u16 spr_latency[5]; 257 /* cursor */ 258 u16 cur_latency[5]; 259 /* 260 * Raw watermark memory latency values 261 * for SKL for all 8 levels 262 * in 1us units. 263 */ 264 u16 skl_latency[8]; 265 266 /* current hardware state */ 267 union { 268 struct ilk_wm_values hw; 269 struct vlv_wm_values vlv; 270 struct g4x_wm_values g4x; 271 }; 272 273 u8 num_levels; 274 275 /* 276 * Should be held around atomic WM register writing; also 277 * protects * intel_crtc->wm.active and 278 * crtc_state->wm.need_postvbl_update. 279 */ 280 struct mutex wm_mutex; 281 282 bool ipc_enabled; 283 }; 284 285 struct intel_display { 286 /* drm device backpointer */ 287 struct drm_device *drm; 288 289 /* Display functions */ 290 struct { 291 /* Top level crtc-ish functions */ 292 const struct intel_display_funcs *display; 293 294 /* Display CDCLK functions */ 295 const struct intel_cdclk_funcs *cdclk; 296 297 /* Display pll funcs */ 298 const struct intel_dpll_funcs *dpll; 299 300 /* irq display functions */ 301 const struct intel_hotplug_funcs *hotplug; 302 303 /* pm display functions */ 304 const struct intel_wm_funcs *wm; 305 306 /* fdi display functions */ 307 const struct intel_fdi_funcs *fdi; 308 309 /* Display internal color functions */ 310 const struct intel_color_funcs *color; 311 312 /* Display internal audio functions */ 313 const struct intel_audio_funcs *audio; 314 } funcs; 315 316 struct { 317 bool any_task_allowed; 318 struct task_struct *allowed_task; 319 } access; 320 321 struct { 322 /* backlight registers and fields in struct intel_panel */ 323 struct mutex lock; 324 } backlight; 325 326 struct { 327 struct intel_global_obj obj; 328 329 struct intel_bw_info { 330 /* for each QGV point */ 331 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 332 /* for each PSF GV point */ 333 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 334 /* Peak BW for each QGV point */ 335 unsigned int peakbw[I915_NUM_QGV_POINTS]; 336 u8 num_qgv_points; 337 u8 num_psf_gv_points; 338 u8 num_planes; 339 } max[6]; 340 } bw; 341 342 struct { 343 /* The current hardware cdclk configuration */ 344 struct intel_cdclk_config hw; 345 346 /* cdclk, divider, and ratio table from bspec */ 347 const struct intel_cdclk_vals *table; 348 349 struct intel_global_obj obj; 350 351 unsigned int max_cdclk_freq; 352 unsigned int max_dotclk_freq; 353 unsigned int skl_preferred_vco_freq; 354 } cdclk; 355 356 struct { 357 struct drm_property_blob *glk_linear_degamma_lut; 358 } color; 359 360 struct { 361 /* The current hardware dbuf configuration */ 362 u8 enabled_slices; 363 364 struct intel_global_obj obj; 365 } dbuf; 366 367 struct { 368 /* 369 * dkl.phy_lock protects against concurrent access of the 370 * Dekel TypeC PHYs. 371 */ 372 spinlock_t phy_lock; 373 } dkl; 374 375 struct { 376 struct intel_dmc *dmc; 377 intel_wakeref_t wakeref; 378 } dmc; 379 380 struct { 381 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 382 u32 mmio_base; 383 } dsi; 384 385 struct { 386 /* list of fbdev register on this device */ 387 struct intel_fbdev *fbdev; 388 struct work_struct suspend_work; 389 } fbdev; 390 391 struct { 392 unsigned int pll_freq; 393 u32 rx_config; 394 } fdi; 395 396 struct { 397 struct list_head obj_list; 398 } global; 399 400 struct { 401 /* 402 * Base address of where the gmbus and gpio blocks are located 403 * (either on PCH or on SoC for platforms without PCH). 404 */ 405 u32 mmio_base; 406 407 /* 408 * gmbus.mutex protects against concurrent usage of the single 409 * hw gmbus controller on different i2c buses. 410 */ 411 struct mutex mutex; 412 413 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 414 415 wait_queue_head_t wait_queue; 416 } gmbus; 417 418 struct { 419 struct i915_hdcp_arbiter *arbiter; 420 bool comp_added; 421 422 /* 423 * HDCP message struct for allocation of memory which can be 424 * reused when sending message to gsc cs. 425 * this is only populated post Meteorlake 426 */ 427 struct intel_hdcp_gsc_message *hdcp_message; 428 /* Mutex to protect the above hdcp related values. */ 429 struct mutex hdcp_mutex; 430 } hdcp; 431 432 struct { 433 /* 434 * HTI (aka HDPORT) state read during initial hw readout. Most 435 * platforms don't have HTI, so this will just stay 0. Those 436 * that do will use this later to figure out which PLLs and PHYs 437 * are unavailable for driver usage. 438 */ 439 u32 state; 440 } hti; 441 442 struct { 443 /* Access with DISPLAY_INFO() */ 444 const struct intel_display_device_info *__device_info; 445 446 /* Access with DISPLAY_RUNTIME_INFO() */ 447 struct intel_display_runtime_info __runtime_info; 448 } info; 449 450 struct { 451 bool false_color; 452 } ips; 453 454 struct { 455 bool display_irqs_enabled; 456 457 /* For i915gm/i945gm vblank irq workaround */ 458 u8 vblank_enabled; 459 460 u32 de_irq_mask[I915_MAX_PIPES]; 461 u32 pipestat_irq_mask[I915_MAX_PIPES]; 462 } irq; 463 464 struct { 465 wait_queue_head_t waitqueue; 466 467 /* mutex to protect pmdemand programming sequence */ 468 struct mutex lock; 469 470 struct intel_global_obj obj; 471 } pmdemand; 472 473 struct { 474 struct i915_power_domains domains; 475 476 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 477 u32 chv_phy_control; 478 479 /* perform PHY state sanity checks? */ 480 bool chv_phy_assert[2]; 481 } power; 482 483 struct { 484 u32 mmio_base; 485 486 /* protects panel power sequencer state */ 487 struct mutex mutex; 488 } pps; 489 490 struct { 491 struct drm_property *broadcast_rgb; 492 struct drm_property *force_audio; 493 } properties; 494 495 struct { 496 unsigned long mask; 497 } quirks; 498 499 struct { 500 /* restore state for suspend/resume and display reset */ 501 struct drm_atomic_state *modeset_state; 502 struct drm_modeset_acquire_ctx reset_ctx; 503 } restore; 504 505 struct { 506 enum { 507 I915_SAGV_UNKNOWN = 0, 508 I915_SAGV_DISABLED, 509 I915_SAGV_ENABLED, 510 I915_SAGV_NOT_CONTROLLED 511 } status; 512 513 u32 block_time_us; 514 } sagv; 515 516 struct { 517 /* 518 * DG2: Mask of PHYs that were not calibrated by the firmware 519 * and should not be used. 520 */ 521 u8 phy_failed_calibration; 522 } snps; 523 524 struct { 525 /* 526 * Shadows for CHV DPLL_MD regs to keep the state 527 * checker somewhat working in the presence hardware 528 * crappiness (can't read out DPLL_MD for pipes B & C). 529 */ 530 u32 chv_dpll_md[I915_MAX_PIPES]; 531 u32 bxt_phy_grc; 532 } state; 533 534 struct { 535 /* ordered wq for modesets */ 536 struct workqueue_struct *modeset; 537 538 /* unbound hipri wq for page flips/plane updates */ 539 struct workqueue_struct *flip; 540 } wq; 541 542 /* Grouping using named structs. Keep sorted. */ 543 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 544 struct intel_audio audio; 545 struct intel_dpll dpll; 546 struct intel_fbc *fbc[I915_MAX_FBCS]; 547 struct intel_frontbuffer_tracking fb_tracking; 548 struct intel_hotplug hotplug; 549 struct intel_opregion *opregion; 550 struct intel_overlay *overlay; 551 struct intel_display_params params; 552 struct intel_vbt_data vbt; 553 struct intel_dmc_wl wl; 554 struct intel_wm wm; 555 }; 556 557 #endif /* __INTEL_DISPLAY_CORE_H__ */ 558