1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <drv_types.h>
9 #include <hal_data.h>
10 #include <linux/kernel.h>
11
PHY_GetTxPowerByRateBase(struct adapter * Adapter,u8 RfPath,enum rate_section RateSection)12 u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
13 enum rate_section RateSection)
14 {
15 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
16 u8 value = 0;
17
18 if (RfPath >= RF_PATH_MAX)
19 return 0;
20
21 switch (RateSection) {
22 case CCK:
23 value = pHalData->TxPwrByRateBase2_4G[RfPath][0];
24 break;
25 case OFDM:
26 value = pHalData->TxPwrByRateBase2_4G[RfPath][1];
27 break;
28 case HT_MCS0_MCS7:
29 value = pHalData->TxPwrByRateBase2_4G[RfPath][2];
30 break;
31 default:
32 break;
33 }
34
35 return value;
36 }
37
38 static void
phy_SetTxPowerByRateBase(struct adapter * Adapter,u8 RfPath,enum rate_section RateSection,u8 Value)39 phy_SetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
40 enum rate_section RateSection, u8 Value)
41 {
42 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
43
44 if (RfPath >= RF_PATH_MAX)
45 return;
46
47 switch (RateSection) {
48 case CCK:
49 pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value;
50 break;
51 case OFDM:
52 pHalData->TxPwrByRateBase2_4G[RfPath][1] = Value;
53 break;
54 case HT_MCS0_MCS7:
55 pHalData->TxPwrByRateBase2_4G[RfPath][2] = Value;
56 break;
57 default:
58 break;
59 }
60 }
61
62 static void
phy_StoreTxPowerByRateBase(struct adapter * padapter)63 phy_StoreTxPowerByRateBase(
64 struct adapter *padapter
65 )
66 {
67 u8 path, base;
68
69 for (path = RF_PATH_A; path <= RF_PATH_B; ++path) {
70 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
71 phy_SetTxPowerByRateBase(padapter, path, CCK, base);
72
73 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
74 phy_SetTxPowerByRateBase(padapter, path, OFDM, base);
75
76 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
77 phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, base);
78 }
79 }
80
PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask)81 u8 PHY_GetRateSectionIndexOfTxPowerByRate(
82 struct adapter *padapter, u32 RegAddr, u32 BitMask
83 )
84 {
85 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
86 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
87 u8 index = 0;
88
89 if (pDM_Odm->PhyRegPgVersion == 0) {
90 switch (RegAddr) {
91 case rTxAGC_A_Rate18_06:
92 index = 0;
93 break;
94 case rTxAGC_A_Rate54_24:
95 index = 1;
96 break;
97 case rTxAGC_A_CCK1_Mcs32:
98 index = 6;
99 break;
100 case rTxAGC_B_CCK11_A_CCK2_11:
101 if (BitMask == bMaskH3Bytes)
102 index = 7;
103 else if (BitMask == 0x000000ff)
104 index = 15;
105 break;
106
107 case rTxAGC_A_Mcs03_Mcs00:
108 index = 2;
109 break;
110 case rTxAGC_A_Mcs07_Mcs04:
111 index = 3;
112 break;
113 case rTxAGC_B_Rate18_06:
114 index = 8;
115 break;
116 case rTxAGC_B_Rate54_24:
117 index = 9;
118 break;
119 case rTxAGC_B_CCK1_55_Mcs32:
120 index = 14;
121 break;
122 case rTxAGC_B_Mcs03_Mcs00:
123 index = 10;
124 break;
125 case rTxAGC_B_Mcs07_Mcs04:
126 index = 11;
127 break;
128 default:
129 break;
130 }
131 }
132
133 return index;
134 }
135
136 void
PHY_GetRateValuesOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Value,u8 * RateIndex,s8 * PwrByRateVal,u8 * RateNum)137 PHY_GetRateValuesOfTxPowerByRate(
138 struct adapter *padapter,
139 u32 RegAddr,
140 u32 BitMask,
141 u32 Value,
142 u8 *RateIndex,
143 s8 *PwrByRateVal,
144 u8 *RateNum
145 )
146 {
147 u8 i = 0;
148
149 switch (RegAddr) {
150 case rTxAGC_A_Rate18_06:
151 case rTxAGC_B_Rate18_06:
152 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
153 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
154 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
155 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
156 for (i = 0; i < 4; ++i) {
157 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
158 ((Value >> (i * 8)) & 0xF));
159 }
160 *RateNum = 4;
161 break;
162
163 case rTxAGC_A_Rate54_24:
164 case rTxAGC_B_Rate54_24:
165 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
166 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
167 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
168 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
169 for (i = 0; i < 4; ++i) {
170 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
171 ((Value >> (i * 8)) & 0xF));
172 }
173 *RateNum = 4;
174 break;
175
176 case rTxAGC_A_CCK1_Mcs32:
177 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
178 PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 +
179 ((Value >> 8) & 0xF));
180 *RateNum = 1;
181 break;
182
183 case rTxAGC_B_CCK11_A_CCK2_11:
184 if (BitMask == 0xffffff00) {
185 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
186 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
187 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
188 for (i = 1; i < 4; ++i) {
189 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
190 ((Value >> (i * 8)) & 0xF));
191 }
192 *RateNum = 3;
193 } else if (BitMask == 0x000000ff) {
194 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
195 PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF));
196 *RateNum = 1;
197 }
198 break;
199
200 case rTxAGC_A_Mcs03_Mcs00:
201 case rTxAGC_B_Mcs03_Mcs00:
202 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
203 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
204 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
205 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
206 for (i = 0; i < 4; ++i) {
207 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
208 ((Value >> (i * 8)) & 0xF));
209 }
210 *RateNum = 4;
211 break;
212
213 case rTxAGC_A_Mcs07_Mcs04:
214 case rTxAGC_B_Mcs07_Mcs04:
215 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
216 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
217 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
218 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
219 for (i = 0; i < 4; ++i) {
220 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
221 ((Value >> (i * 8)) & 0xF));
222 }
223 *RateNum = 4;
224 break;
225
226 case rTxAGC_B_CCK1_55_Mcs32:
227 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
228 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
229 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
230 for (i = 1; i < 4; ++i) {
231 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
232 ((Value >> (i * 8)) & 0xF));
233 }
234 *RateNum = 3;
235 break;
236
237 case 0xC20:
238 case 0xE20:
239 case 0x1820:
240 case 0x1a20:
241 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
242 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
243 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
244 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
245 for (i = 0; i < 4; ++i) {
246 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
247 ((Value >> (i * 8)) & 0xF));
248 }
249 *RateNum = 4;
250 break;
251
252 case 0xC24:
253 case 0xE24:
254 case 0x1824:
255 case 0x1a24:
256 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
257 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
258 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
259 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
260 for (i = 0; i < 4; ++i) {
261 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
262 ((Value >> (i * 8)) & 0xF));
263 }
264 *RateNum = 4;
265 break;
266
267 case 0xC28:
268 case 0xE28:
269 case 0x1828:
270 case 0x1a28:
271 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
272 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
273 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
274 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
275 for (i = 0; i < 4; ++i) {
276 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
277 ((Value >> (i * 8)) & 0xF));
278 }
279 *RateNum = 4;
280 break;
281
282 case 0xC2C:
283 case 0xE2C:
284 case 0x182C:
285 case 0x1a2C:
286 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
287 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
288 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
289 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
290 for (i = 0; i < 4; ++i) {
291 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
292 ((Value >> (i * 8)) & 0xF));
293 }
294 *RateNum = 4;
295 break;
296
297 case 0xC30:
298 case 0xE30:
299 case 0x1830:
300 case 0x1a30:
301 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
302 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
303 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
304 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
305 for (i = 0; i < 4; ++i) {
306 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
307 ((Value >> (i * 8)) & 0xF));
308 }
309 *RateNum = 4;
310 break;
311
312 default:
313 break;
314 }
315 }
316
PHY_StoreTxPowerByRateNew(struct adapter * padapter,u32 RfPath,u32 RegAddr,u32 BitMask,u32 Data)317 static void PHY_StoreTxPowerByRateNew(struct adapter *padapter, u32 RfPath,
318 u32 RegAddr, u32 BitMask, u32 Data)
319 {
320 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
321 u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
322 s8 PwrByRateVal[4] = {0};
323
324 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum);
325
326 if (RfPath >= RF_PATH_MAX)
327 return;
328
329 for (i = 0; i < rateNum; ++i) {
330 pHalData->TxPwrByRateOffset[RfPath][rateIndex[i]] = PwrByRateVal[i];
331 }
332 }
333
PHY_StoreTxPowerByRateOld(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)334 static void PHY_StoreTxPowerByRateOld(
335 struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data
336 )
337 {
338 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
339 u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask);
340
341 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
342 }
343
PHY_InitTxPowerByRate(struct adapter * padapter)344 void PHY_InitTxPowerByRate(struct adapter *padapter)
345 {
346 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
347 u8 rfPath, rate;
348
349 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath)
350 for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
351 pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
352 }
353
PHY_StoreTxPowerByRate(struct adapter * padapter,u32 RfPath,u32 RegAddr,u32 BitMask,u32 Data)354 void PHY_StoreTxPowerByRate(
355 struct adapter *padapter,
356 u32 RfPath,
357 u32 RegAddr,
358 u32 BitMask,
359 u32 Data
360 )
361 {
362 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
363 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
364
365 if (pDM_Odm->PhyRegPgVersion > 0)
366 PHY_StoreTxPowerByRateNew(padapter, RfPath, RegAddr, BitMask, Data);
367 else if (pDM_Odm->PhyRegPgVersion == 0) {
368 PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
369 }
370 }
371
372 static void
phy_ConvertTxPowerByRateInDbmToRelativeValues(struct adapter * padapter)373 phy_ConvertTxPowerByRateInDbmToRelativeValues(
374 struct adapter *padapter
375 )
376 {
377 u8 base = 0, i = 0, value = 0, path = 0;
378 u8 cckRates[4] = {
379 MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
380 };
381 u8 ofdmRates[8] = {
382 MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M
383 };
384 u8 mcs0_7Rates[8] = {
385 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
386 };
387 for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) {
388 /* CCK */
389 base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
390 for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
391 value = PHY_GetTxPowerByRate(padapter, path, cckRates[i]);
392 PHY_SetTxPowerByRate(padapter, path, cckRates[i], value - base);
393 }
394
395 /* OFDM */
396 base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
397 for (i = 0; i < sizeof(ofdmRates); ++i) {
398 value = PHY_GetTxPowerByRate(padapter, path, ofdmRates[i]);
399 PHY_SetTxPowerByRate(padapter, path, ofdmRates[i], value - base);
400 }
401
402 /* HT MCS0~7 */
403 base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
404 for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
405 value = PHY_GetTxPowerByRate(padapter, path, mcs0_7Rates[i]);
406 PHY_SetTxPowerByRate(padapter, path, mcs0_7Rates[i], value - base);
407 }
408 }
409 }
410
411 /*
412 * This function must be called if the value in the PHY_REG_PG.txt(or header)
413 * is exact dBm values
414 */
PHY_TxPowerByRateConfiguration(struct adapter * padapter)415 void PHY_TxPowerByRateConfiguration(struct adapter *padapter)
416 {
417 phy_StoreTxPowerByRateBase(padapter);
418 phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter);
419 }
420
PHY_SetTxPowerIndexByRateSection(struct adapter * padapter,u8 RFPath,u8 Channel,u8 RateSection)421 void PHY_SetTxPowerIndexByRateSection(
422 struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection
423 )
424 {
425 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
426
427 if (RateSection == CCK) {
428 u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
429 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
430 pHalData->CurrentChannelBW,
431 Channel, cckRates,
432 ARRAY_SIZE(cckRates));
433
434 } else if (RateSection == OFDM) {
435 u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
436 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
437 pHalData->CurrentChannelBW,
438 Channel, ofdmRates,
439 ARRAY_SIZE(ofdmRates));
440
441 } else if (RateSection == HT_MCS0_MCS7) {
442 u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
443 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
444 pHalData->CurrentChannelBW,
445 Channel, htRates1T,
446 ARRAY_SIZE(htRates1T));
447
448 }
449 }
450
PHY_GetTxPowerIndexBase(struct adapter * padapter,u8 RFPath,u8 Rate,enum channel_width BandWidth,u8 Channel)451 u8 PHY_GetTxPowerIndexBase(
452 struct adapter *padapter,
453 u8 RFPath,
454 u8 Rate,
455 enum channel_width BandWidth,
456 u8 Channel
457 )
458 {
459 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
460 u8 txPower = 0;
461 u8 chnlIdx = (Channel-1);
462
463 if (HAL_IsLegalChannel(padapter, Channel) == false)
464 chnlIdx = 0;
465
466 if (IS_CCK_RATE(Rate))
467 txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
468 else if (MGN_6M <= Rate)
469 txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
470
471 /* OFDM-1T */
472 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
473 txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
474
475 if (BandWidth == CHANNEL_WIDTH_20) { /* BW20-1S, BW20-2S */
476 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
477 txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
478 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */
479 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
480 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
481 }
482
483 return txPower;
484 }
485
PHY_GetTxPowerTrackingOffset(struct adapter * padapter,u8 RFPath,u8 Rate)486 s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate)
487 {
488 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
489 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
490 s8 offset = 0;
491
492 if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == false)
493 return offset;
494
495 if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M))
496 offset = pDM_Odm->Remnant_CCKSwingIdx;
497 else
498 offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath];
499
500 return offset;
501 }
502
PHY_GetRateIndexOfTxPowerByRate(u8 Rate)503 u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
504 {
505 u8 index = 0;
506 switch (Rate) {
507 case MGN_1M:
508 index = 0;
509 break;
510 case MGN_2M:
511 index = 1;
512 break;
513 case MGN_5_5M:
514 index = 2;
515 break;
516 case MGN_11M:
517 index = 3;
518 break;
519 case MGN_6M:
520 index = 4;
521 break;
522 case MGN_9M:
523 index = 5;
524 break;
525 case MGN_12M:
526 index = 6;
527 break;
528 case MGN_18M:
529 index = 7;
530 break;
531 case MGN_24M:
532 index = 8;
533 break;
534 case MGN_36M:
535 index = 9;
536 break;
537 case MGN_48M:
538 index = 10;
539 break;
540 case MGN_54M:
541 index = 11;
542 break;
543 case MGN_MCS0:
544 index = 12;
545 break;
546 case MGN_MCS1:
547 index = 13;
548 break;
549 case MGN_MCS2:
550 index = 14;
551 break;
552 case MGN_MCS3:
553 index = 15;
554 break;
555 case MGN_MCS4:
556 index = 16;
557 break;
558 case MGN_MCS5:
559 index = 17;
560 break;
561 case MGN_MCS6:
562 index = 18;
563 break;
564 case MGN_MCS7:
565 index = 19;
566 break;
567 default:
568 break;
569 }
570 return index;
571 }
572
PHY_GetTxPowerByRate(struct adapter * padapter,u8 RFPath,u8 Rate)573 s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate)
574 {
575 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
576 s8 value = 0;
577 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
578
579 if ((padapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) ||
580 padapter->registrypriv.RegEnableTxPowerByRate == 0)
581 return 0;
582
583 if (RFPath >= RF_PATH_MAX)
584 return value;
585
586 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
587 return value;
588
589 return pHalData->TxPwrByRateOffset[RFPath][rateIndex];
590
591 }
592
PHY_SetTxPowerByRate(struct adapter * padapter,u8 RFPath,u8 Rate,s8 Value)593 void PHY_SetTxPowerByRate(
594 struct adapter *padapter,
595 u8 RFPath,
596 u8 Rate,
597 s8 Value
598 )
599 {
600 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
601 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
602
603 if (RFPath >= RF_PATH_MAX)
604 return;
605
606 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
607 return;
608
609 pHalData->TxPwrByRateOffset[RFPath][rateIndex] = Value;
610 }
611
PHY_SetTxPowerLevelByPath(struct adapter * Adapter,u8 channel,u8 path)612 void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
613 {
614 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
615
616 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
617 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
618 }
619
PHY_SetTxPowerIndexByRateArray(struct adapter * padapter,u8 RFPath,enum channel_width BandWidth,u8 Channel,u8 * Rates,u8 RateArraySize)620 void PHY_SetTxPowerIndexByRateArray(
621 struct adapter *padapter,
622 u8 RFPath,
623 enum channel_width BandWidth,
624 u8 Channel,
625 u8 *Rates,
626 u8 RateArraySize
627 )
628 {
629 u32 powerIndex = 0;
630 int i = 0;
631
632 for (i = 0; i < RateArraySize; ++i) {
633 powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel);
634 PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]);
635 }
636 }
637
phy_GetWorldWideLimit(s8 * LimitTable)638 static s8 phy_GetWorldWideLimit(s8 *LimitTable)
639 {
640 s8 min = LimitTable[0];
641 u8 i = 0;
642
643 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
644 if (LimitTable[i] < min)
645 min = LimitTable[i];
646 }
647
648 return min;
649 }
650
phy_GetChannelIndexOfTxPowerLimit(u8 Channel)651 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Channel)
652 {
653 return Channel - 1;
654 }
655
get_bandwidth_idx(const enum channel_width bandwidth)656 static s16 get_bandwidth_idx(const enum channel_width bandwidth)
657 {
658 switch (bandwidth) {
659 case CHANNEL_WIDTH_20:
660 return 0;
661 case CHANNEL_WIDTH_40:
662 return 1;
663 default:
664 return -1;
665 }
666 }
667
get_rate_sctn_idx(const u8 rate)668 static s16 get_rate_sctn_idx(const u8 rate)
669 {
670 switch (rate) {
671 case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M:
672 return 0;
673 case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M:
674 case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M:
675 return 1;
676 case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3:
677 case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7:
678 return 2;
679 default:
680 return -1;
681 }
682 }
683
phy_get_tx_pwr_lmt(struct adapter * adapter,u32 reg_pwr_tbl_sel,enum channel_width bandwidth,u8 rf_path,u8 data_rate,u8 channel)684 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel,
685 enum channel_width bandwidth,
686 u8 rf_path, u8 data_rate, u8 channel)
687 {
688 s16 idx_regulation = -1;
689 s16 idx_bandwidth = -1;
690 s16 idx_rate_sctn = -1;
691 s16 idx_channel = -1;
692 s8 pwr_lmt = MAX_POWER_INDEX;
693 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
694 s8 limits[10] = {0}; u8 i = 0;
695
696 if (((adapter->registrypriv.RegEnableTxPowerLimit == 2) &&
697 (hal_data->EEPROMRegulatory != 1)) ||
698 (adapter->registrypriv.RegEnableTxPowerLimit == 0))
699 return MAX_POWER_INDEX;
700
701 switch (adapter->registrypriv.RegPwrTblSel) {
702 case 1:
703 idx_regulation = TXPWR_LMT_ETSI;
704 break;
705 case 2:
706 idx_regulation = TXPWR_LMT_MKK;
707 break;
708 case 3:
709 idx_regulation = TXPWR_LMT_FCC;
710 break;
711 case 4:
712 idx_regulation = TXPWR_LMT_WW;
713 break;
714 default:
715 idx_regulation = hal_data->Regulation2_4G;
716 break;
717 }
718
719 idx_bandwidth = get_bandwidth_idx(bandwidth);
720 idx_rate_sctn = get_rate_sctn_idx(data_rate);
721
722 /* workaround for wrong index combination to obtain tx power limit, */
723 /* OFDM only exists in BW 20M */
724 /* CCK table will only be given in BW 20M */
725 /* HT on 80M will reference to HT on 40M */
726 if (idx_rate_sctn == 0 || idx_rate_sctn == 1)
727 idx_bandwidth = 0;
728
729 channel = phy_GetChannelIndexOfTxPowerLimit(channel);
730
731 if (idx_regulation == -1 || idx_bandwidth == -1 ||
732 idx_rate_sctn == -1 || idx_channel == -1)
733 return MAX_POWER_INDEX;
734
735
736 for (i = 0; i < MAX_REGULATION_NUM; i++)
737 limits[i] = hal_data->TxPwrLimit_2_4G[i]
738 [idx_bandwidth]
739 [idx_rate_sctn]
740 [idx_channel]
741 [rf_path];
742
743 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
744 phy_GetWorldWideLimit(limits) :
745 hal_data->TxPwrLimit_2_4G[idx_regulation]
746 [idx_bandwidth]
747 [idx_rate_sctn]
748 [idx_channel]
749 [rf_path];
750
751 return pwr_lmt;
752 }
753
PHY_ConvertTxPowerLimitToPowerIndex(struct adapter * Adapter)754 void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
755 {
756 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
757 u8 BW40PwrBasedBm2_4G = 0x2E;
758 u8 regulation, bw, channel, rateSection;
759 s8 tempValue = 0, tempPwrLmt = 0;
760 u8 rfPath = 0;
761
762 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
763 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
764 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
765 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
766 tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A];
767
768 for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
769 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
770 if (rateSection == 2) /* HT 1T */
771 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, HT_MCS0_MCS7);
772 else if (rateSection == 1) /* OFDM */
773 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, OFDM);
774 else if (rateSection == 0) /* CCK */
775 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, CCK);
776 } else
777 BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2;
778
779 if (tempPwrLmt != MAX_POWER_INDEX) {
780 tempValue = tempPwrLmt - BW40PwrBasedBm2_4G;
781 pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
782 }
783 }
784 }
785 }
786 }
787 }
788 }
789
PHY_InitTxPowerLimit(struct adapter * Adapter)790 void PHY_InitTxPowerLimit(struct adapter *Adapter)
791 {
792 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
793 u8 i, j, k, l, m;
794
795 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
796 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
797 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
798 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
799 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
800 pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
801 }
802 }
803
PHY_SetTxPowerLimit(struct adapter * Adapter,u8 * Regulation,u8 * Bandwidth,u8 * RateSection,u8 * RfPath,u8 * Channel,u8 * PowerLimit)804 void PHY_SetTxPowerLimit(
805 struct adapter *Adapter,
806 u8 *Regulation,
807 u8 *Bandwidth,
808 u8 *RateSection,
809 u8 *RfPath,
810 u8 *Channel,
811 u8 *PowerLimit
812 )
813 {
814 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
815 u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
816 s8 powerLimit = 0, prevPowerLimit, channelIndex;
817
818 GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel);
819 GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit);
820
821 powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
822
823 if (eqNByte(Regulation, (u8 *)("FCC"), 3))
824 regulation = 0;
825 else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
826 regulation = 1;
827 else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
828 regulation = 2;
829 else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
830 regulation = 3;
831
832 if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
833 rateSection = 0;
834 else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
835 rateSection = 1;
836 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
837 rateSection = 2;
838 else
839 return;
840
841 if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
842 bandwidth = 0;
843 else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
844 bandwidth = 1;
845
846 channelIndex = phy_GetChannelIndexOfTxPowerLimit(channel);
847
848 if (channelIndex == -1)
849 return;
850
851 prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
852
853 if (powerLimit < prevPowerLimit)
854 pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
855 }
856
Hal_ChannelPlanToRegulation(struct adapter * Adapter,u16 ChannelPlan)857 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
858 {
859 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
860 pHalData->Regulation2_4G = TXPWR_LMT_WW;
861
862 switch (ChannelPlan) {
863 case RT_CHANNEL_DOMAIN_WORLD_NULL:
864 pHalData->Regulation2_4G = TXPWR_LMT_WW;
865 break;
866 case RT_CHANNEL_DOMAIN_ETSI1_NULL:
867 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
868 break;
869 case RT_CHANNEL_DOMAIN_FCC1_NULL:
870 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
871 break;
872 case RT_CHANNEL_DOMAIN_MKK1_NULL:
873 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
874 break;
875 case RT_CHANNEL_DOMAIN_ETSI2_NULL:
876 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
877 break;
878 case RT_CHANNEL_DOMAIN_FCC1_FCC1:
879 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
880 break;
881 case RT_CHANNEL_DOMAIN_WORLD_ETSI1:
882 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
883 break;
884 case RT_CHANNEL_DOMAIN_MKK1_MKK1:
885 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
886 break;
887 case RT_CHANNEL_DOMAIN_WORLD_KCC1:
888 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
889 break;
890 case RT_CHANNEL_DOMAIN_WORLD_FCC2:
891 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
892 break;
893 case RT_CHANNEL_DOMAIN_WORLD_FCC3:
894 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
895 break;
896 case RT_CHANNEL_DOMAIN_WORLD_FCC4:
897 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
898 break;
899 case RT_CHANNEL_DOMAIN_WORLD_FCC5:
900 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
901 break;
902 case RT_CHANNEL_DOMAIN_WORLD_FCC6:
903 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
904 break;
905 case RT_CHANNEL_DOMAIN_FCC1_FCC7:
906 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
907 break;
908 case RT_CHANNEL_DOMAIN_WORLD_ETSI2:
909 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
910 break;
911 case RT_CHANNEL_DOMAIN_WORLD_ETSI3:
912 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
913 break;
914 case RT_CHANNEL_DOMAIN_MKK1_MKK2:
915 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
916 break;
917 case RT_CHANNEL_DOMAIN_MKK1_MKK3:
918 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
919 break;
920 case RT_CHANNEL_DOMAIN_FCC1_NCC1:
921 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
922 break;
923 case RT_CHANNEL_DOMAIN_FCC1_NCC2:
924 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
925 break;
926 case RT_CHANNEL_DOMAIN_GLOBAL_NULL:
927 pHalData->Regulation2_4G = TXPWR_LMT_WW;
928 break;
929 case RT_CHANNEL_DOMAIN_ETSI1_ETSI4:
930 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
931 break;
932 case RT_CHANNEL_DOMAIN_FCC1_FCC2:
933 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
934 break;
935 case RT_CHANNEL_DOMAIN_FCC1_NCC3:
936 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
937 break;
938 case RT_CHANNEL_DOMAIN_WORLD_ETSI5:
939 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
940 break;
941 case RT_CHANNEL_DOMAIN_FCC1_FCC8:
942 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
943 break;
944 case RT_CHANNEL_DOMAIN_WORLD_ETSI6:
945 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
946 break;
947 case RT_CHANNEL_DOMAIN_WORLD_ETSI7:
948 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
949 break;
950 case RT_CHANNEL_DOMAIN_WORLD_ETSI8:
951 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
952 break;
953 case RT_CHANNEL_DOMAIN_WORLD_ETSI9:
954 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
955 break;
956 case RT_CHANNEL_DOMAIN_WORLD_ETSI10:
957 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
958 break;
959 case RT_CHANNEL_DOMAIN_WORLD_ETSI11:
960 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
961 break;
962 case RT_CHANNEL_DOMAIN_FCC1_NCC4:
963 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
964 break;
965 case RT_CHANNEL_DOMAIN_WORLD_ETSI12:
966 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
967 break;
968 case RT_CHANNEL_DOMAIN_FCC1_FCC9:
969 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
970 break;
971 case RT_CHANNEL_DOMAIN_WORLD_ETSI13:
972 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
973 break;
974 case RT_CHANNEL_DOMAIN_FCC1_FCC10:
975 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
976 break;
977 case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */
978 pHalData->Regulation2_4G = TXPWR_LMT_WW;
979 break;
980 default:
981 break;
982 }
983 }
984