1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HUBBUB_DCN10_H__ 27 #define __DC_HUBBUB_DCN10_H__ 28 29 #include "core_types.h" 30 #include "dchubbub.h" 31 32 #define TO_DCN10_HUBBUB(hubbub)\ 33 container_of(hubbub, struct dcn10_hubbub, base) 34 35 #define HUBBUB_REG_LIST_DCN_COMMON()\ 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 45 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 46 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 47 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 48 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 49 SR(DCHUBBUB_TEST_DEBUG_INDEX), \ 50 SR(DCHUBBUB_TEST_DEBUG_DATA),\ 51 SR(DCHUBBUB_SOFT_RESET) 52 53 #define HUBBUB_VM_REG_LIST() \ 54 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ 55 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ 56 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ 57 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D) 58 59 #define HUBBUB_SR_WATERMARK_REG_LIST()\ 60 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ 61 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ 62 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ 63 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ 64 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ 65 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ 66 SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ 67 SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) 68 69 #define HUBBUB_REG_LIST_DCN10(id)\ 70 HUBBUB_REG_LIST_DCN_COMMON(), \ 71 HUBBUB_VM_REG_LIST(), \ 72 HUBBUB_SR_WATERMARK_REG_LIST(), \ 73 SR(DCHUBBUB_SDPIF_FB_TOP),\ 74 SR(DCHUBBUB_SDPIF_FB_BASE),\ 75 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 76 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 77 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 78 SR(DCHUBBUB_SDPIF_AGP_TOP) 79 80 struct dcn_hubbub_registers { 81 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; 82 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; 83 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; 84 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; 85 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; 86 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; 87 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; 88 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; 89 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; 90 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; 91 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; 92 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; 93 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; 94 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; 95 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; 96 uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; 97 uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; 98 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; 99 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; 100 uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; 101 uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; 102 uint32_t DCHUBBUB_ARB_SAT_LEVEL; 103 uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; 104 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 105 uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; 106 uint32_t DCHUBBUB_TEST_DEBUG_INDEX; 107 uint32_t DCHUBBUB_TEST_DEBUG_DATA; 108 uint32_t DCHUBBUB_SDPIF_FB_TOP; 109 uint32_t DCHUBBUB_SDPIF_FB_BASE; 110 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 111 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 112 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 113 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 114 uint32_t DCHUBBUB_CRC_CTRL; 115 uint32_t DCHUBBUB_SOFT_RESET; 116 uint32_t DCN_VM_FB_LOCATION_BASE; 117 uint32_t DCN_VM_FB_LOCATION_TOP; 118 uint32_t DCN_VM_FB_OFFSET; 119 uint32_t DCN_VM_AGP_BOT; 120 uint32_t DCN_VM_AGP_TOP; 121 uint32_t DCN_VM_AGP_BASE; 122 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; 123 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; 124 uint32_t DCN_VM_FAULT_ADDR_MSB; 125 uint32_t DCN_VM_FAULT_ADDR_LSB; 126 uint32_t DCN_VM_FAULT_CNTL; 127 uint32_t DCN_VM_FAULT_STATUS; 128 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; 129 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; 130 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; 131 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; 132 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; 133 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; 134 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; 135 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; 136 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; 137 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; 138 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; 139 uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; 140 uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; 141 uint32_t DCHVM_CTRL0; 142 uint32_t DCHVM_MEM_CTRL; 143 uint32_t DCHVM_CLK_CTRL; 144 uint32_t DCHVM_RIOMMU_CTRL0; 145 uint32_t DCHVM_RIOMMU_STAT0; 146 uint32_t DCHUBBUB_DET0_CTRL; 147 uint32_t DCHUBBUB_DET1_CTRL; 148 uint32_t DCHUBBUB_DET2_CTRL; 149 uint32_t DCHUBBUB_DET3_CTRL; 150 uint32_t DCHUBBUB_COMPBUF_CTRL; 151 uint32_t COMPBUF_RESERVED_SPACE; 152 uint32_t DCHUBBUB_DEBUG_CTRL_0; 153 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A; 154 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A; 155 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B; 156 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B; 157 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C; 158 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; 159 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; 160 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; 161 uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL; 162 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A; 163 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B; 164 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C; 165 uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D; 166 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A; 167 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B; 168 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C; 169 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D; 170 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A; 171 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B; 172 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C; 173 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D; 174 uint32_t DCHUBBUB_ARB_MALL_CNTL; 175 uint32_t SDPIF_REQUEST_RATE_LIMIT; 176 uint32_t DCHUBBUB_SDPIF_CFG0; 177 uint32_t DCHUBBUB_SDPIF_CFG1; 178 uint32_t DCHUBBUB_CLOCK_CNTL; 179 uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL; 180 uint32_t DCHUBBUB_ARB_QOS_FORCE; 181 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A; 182 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A; 183 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B; 184 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B; 185 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A; 186 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A; 187 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B; 188 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B; 189 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A; 190 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A; 191 uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B; 192 uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B; 193 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A; 194 uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B; 195 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A; 196 uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B; 197 uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A; 198 uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B; 199 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A; 200 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B; 201 }; 202 203 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ 204 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\ 205 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\ 206 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\ 207 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\ 208 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\ 209 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\ 210 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\ 211 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\ 212 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\ 213 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\ 214 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\ 215 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\ 216 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\ 217 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\ 218 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\ 219 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;\ 220 type MALL_PREFETCH_COMPLETE;\ 221 type MALL_IN_USE 222 223 #define HUBBUB_REG_FIELD_LIST_DCN35(type) \ 224 type DCHUBBUB_FGCG_REP_DIS;\ 225 type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE 226 227 /* set field name */ 228 #define HUBBUB_SF(reg_name, field_name, post_fix)\ 229 .field_name = reg_name ## __ ## field_name ## post_fix 230 231 #define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\ 232 HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 233 HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ 234 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ 235 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ 236 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ 237 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ 238 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ 239 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ 240 HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ 241 HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ 242 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ 243 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ 244 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ 245 HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ 246 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ 247 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ 248 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ 249 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh) 250 251 #define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \ 252 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ 253 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ 254 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ 255 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ 256 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ 257 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ 258 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ 259 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh) 260 261 #define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ 262 HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ 263 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ 264 HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ 265 HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 266 HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 267 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 268 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 269 HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) 270 271 #define DCN_HUBBUB_REG_FIELD_LIST(type) \ 272 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 273 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ 274 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ 275 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ 276 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ 277 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ 278 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ 279 type DCHUBBUB_ARB_SAT_LEVEL;\ 280 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ 281 type DCHUBBUB_GLOBAL_TIMER_REFDIV;\ 282 type DCHUBBUB_GLOBAL_SOFT_RESET; \ 283 type SDPIF_FB_TOP;\ 284 type SDPIF_FB_BASE;\ 285 type SDPIF_FB_OFFSET;\ 286 type SDPIF_AGP_BASE;\ 287 type SDPIF_AGP_BOT;\ 288 type SDPIF_AGP_TOP;\ 289 type FB_BASE;\ 290 type FB_TOP;\ 291 type FB_OFFSET;\ 292 type AGP_BOT;\ 293 type AGP_TOP;\ 294 type AGP_BASE;\ 295 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\ 296 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\ 297 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\ 298 type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\ 299 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ 300 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ 301 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ 302 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ 303 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ 304 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ 305 type DCN_VM_FAULT_ADDR_MSB;\ 306 type DCN_VM_FAULT_ADDR_LSB;\ 307 type DCN_VM_ERROR_STATUS_CLEAR;\ 308 type DCN_VM_ERROR_STATUS_MODE;\ 309 type DCN_VM_ERROR_INTERRUPT_ENABLE;\ 310 type DCN_VM_RANGE_FAULT_DISABLE;\ 311 type DCN_VM_PRQ_FAULT_DISABLE;\ 312 type DCN_VM_ERROR_STATUS;\ 313 type DCN_VM_ERROR_VMID;\ 314 type DCN_VM_ERROR_TABLE_LEVEL;\ 315 type DCN_VM_ERROR_PIPE;\ 316 type DCN_VM_ERROR_INTERRUPT_STATUS 317 318 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ 319 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ 320 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\ 321 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\ 322 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\ 323 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\ 324 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\ 325 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ 326 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 327 328 329 #define HUBBUB_HVM_REG_FIELD_LIST(type) \ 330 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ 331 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ 332 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ 333 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ 334 type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ 335 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ 336 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ 337 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ 338 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ 339 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ 340 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ 341 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ 342 type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ 343 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ 344 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ 345 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ 346 type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ 347 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ 348 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ 349 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ 350 type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ 351 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ 352 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ 353 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ 354 type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ 355 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ 356 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ 357 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ 358 type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ 359 type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ 360 type HOSTVM_INIT_REQ; \ 361 type HVM_GPUVMRET_PWR_REQ_DIS; \ 362 type HVM_GPUVMRET_FORCE_REQ; \ 363 type HVM_GPUVMRET_POWER_STATUS; \ 364 type HVM_DISPCLK_R_GATE_DIS; \ 365 type HVM_DISPCLK_G_GATE_DIS; \ 366 type HVM_DCFCLK_R_GATE_DIS; \ 367 type HVM_DCFCLK_G_GATE_DIS; \ 368 type TR_REQ_REQCLKREQ_MODE; \ 369 type TW_RSP_COMPCLKREQ_MODE; \ 370 type HOSTVM_PREFETCH_REQ; \ 371 type HOSTVM_POWERSTATUS; \ 372 type RIOMMU_ACTIVE; \ 373 type HOSTVM_PREFETCH_DONE 374 375 #define HUBBUB_RET_REG_FIELD_LIST(type) \ 376 type DET_DEPTH;\ 377 type DET0_SIZE;\ 378 type DET1_SIZE;\ 379 type DET2_SIZE;\ 380 type DET3_SIZE;\ 381 type DET0_SIZE_CURRENT;\ 382 type DET1_SIZE_CURRENT;\ 383 type DET2_SIZE_CURRENT;\ 384 type DET3_SIZE_CURRENT;\ 385 type COMPBUF_SIZE;\ 386 type COMPBUF_SIZE_CURRENT;\ 387 type CONFIG_ERROR;\ 388 type COMPBUF_RESERVED_SPACE_64B;\ 389 type COMPBUF_RESERVED_SPACE_ZS;\ 390 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\ 391 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\ 392 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\ 393 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\ 394 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\ 395 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\ 396 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\ 397 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;\ 398 type SDPIF_REQUEST_RATE_LIMIT;\ 399 type DISPCLK_R_DCHUBBUB_GATE_DIS;\ 400 type DCFCLK_R_DCHUBBUB_GATE_DIS;\ 401 type SDPIF_MAX_NUM_OUTSTANDING;\ 402 type DCHUBBUB_ARB_MAX_REQ_OUTSTAND;\ 403 type SDPIF_PORT_CONTROL;\ 404 type DET_MEM_PWR_LS_MODE 405 406 407 #define HUBBUB_REG_FIELD_LIST_DCN4_01(type) \ 408 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;\ 409 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;\ 410 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;\ 411 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;\ 412 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;\ 413 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;\ 414 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;\ 415 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;\ 416 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;\ 417 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;\ 418 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;\ 419 type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;\ 420 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;\ 421 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;\ 422 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;\ 423 type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;\ 424 type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;\ 425 type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;\ 426 type DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;\ 427 type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B 428 429 struct dcn_hubbub_shift { 430 DCN_HUBBUB_REG_FIELD_LIST(uint8_t); 431 HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); 432 HUBBUB_HVM_REG_FIELD_LIST(uint8_t); 433 HUBBUB_RET_REG_FIELD_LIST(uint8_t); 434 HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); 435 HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); 436 HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t); 437 }; 438 439 struct dcn_hubbub_mask { 440 DCN_HUBBUB_REG_FIELD_LIST(uint32_t); 441 HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); 442 HUBBUB_HVM_REG_FIELD_LIST(uint32_t); 443 HUBBUB_RET_REG_FIELD_LIST(uint32_t); 444 HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); 445 HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); 446 HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t); 447 }; 448 449 struct dc; 450 451 struct dcn10_hubbub { 452 struct hubbub base; 453 const struct dcn_hubbub_registers *regs; 454 const struct dcn_hubbub_shift *shifts; 455 const struct dcn_hubbub_mask *masks; 456 unsigned int debug_test_index_pstate; 457 union dcn_watermark_set watermarks; 458 }; 459 460 void hubbub1_update_dchub( 461 struct hubbub *hubbub, 462 struct dchub_init_data *dh_data); 463 464 bool hubbub1_verify_allow_pstate_change_high( 465 struct hubbub *hubbub); 466 467 void hubbub1_wm_change_req_wa(struct hubbub *hubbub); 468 469 bool hubbub1_program_watermarks( 470 struct hubbub *hubbub, 471 union dcn_watermark_set *watermarks, 472 unsigned int refclk_mhz, 473 bool safe_to_lower); 474 475 void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); 476 477 bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); 478 479 void hubbub1_toggle_watermark_change_req( 480 struct hubbub *hubbub); 481 482 void hubbub1_wm_read_state(struct hubbub *hubbub, 483 struct dcn_hubbub_wm *wm); 484 485 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset); 486 void hubbub1_construct(struct hubbub *hubbub, 487 struct dc_context *ctx, 488 const struct dcn_hubbub_registers *hubbub_regs, 489 const struct dcn_hubbub_shift *hubbub_shift, 490 const struct dcn_hubbub_mask *hubbub_mask); 491 492 bool hubbub1_program_urgent_watermarks( 493 struct hubbub *hubbub, 494 union dcn_watermark_set *watermarks, 495 unsigned int refclk_mhz, 496 bool safe_to_lower); 497 bool hubbub1_program_stutter_watermarks( 498 struct hubbub *hubbub, 499 union dcn_watermark_set *watermarks, 500 unsigned int refclk_mhz, 501 bool safe_to_lower); 502 bool hubbub1_program_pstate_watermarks( 503 struct hubbub *hubbub, 504 union dcn_watermark_set *watermarks, 505 unsigned int refclk_mhz, 506 bool safe_to_lower); 507 508 #endif 509