1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2021, 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9 #ifndef _HTT_H_ 10 #define _HTT_H_ 11 12 #include <linux/bug.h> 13 #include <linux/interrupt.h> 14 #include <linux/dmapool.h> 15 #include <linux/hashtable.h> 16 #include <linux/kfifo.h> 17 #include <net/mac80211.h> 18 19 #include "htc.h" 20 #include "hw.h" 21 #include "rx_desc.h" 22 23 enum htt_dbg_stats_type { 24 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0, 25 HTT_DBG_STATS_RX_REORDER = 1 << 1, 26 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2, 27 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3, 28 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4, 29 /* bits 5-23 currently reserved */ 30 31 HTT_DBG_NUM_STATS /* keep this last */ 32 }; 33 34 enum htt_h2t_msg_type { /* host-to-target */ 35 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 36 HTT_H2T_MSG_TYPE_TX_FRM = 1, 37 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2, 38 HTT_H2T_MSG_TYPE_STATS_REQ = 3, 39 HTT_H2T_MSG_TYPE_SYNC = 4, 40 HTT_H2T_MSG_TYPE_AGGR_CFG = 5, 41 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6, 42 43 /* This command is used for sending management frames in HTT < 3.0. 44 * HTT >= 3.0 uses TX_FRM for everything. 45 */ 46 HTT_H2T_MSG_TYPE_MGMT_TX = 7, 47 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11, 48 49 HTT_H2T_NUM_MSGS /* keep this last */ 50 }; 51 52 struct htt_cmd_hdr { 53 u8 msg_type; 54 } __packed; 55 56 struct htt_ver_req { 57 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 58 } __packed; 59 60 /* 61 * HTT tx MSDU descriptor 62 * 63 * The HTT tx MSDU descriptor is created by the host HTT SW for each 64 * tx MSDU. The HTT tx MSDU descriptor contains the information that 65 * the target firmware needs for the FW's tx processing, particularly 66 * for creating the HW msdu descriptor. 67 * The same HTT tx descriptor is used for HL and LL systems, though 68 * a few fields within the tx descriptor are used only by LL or 69 * only by HL. 70 * The HTT tx descriptor is defined in two manners: by a struct with 71 * bitfields, and by a series of [dword offset, bit mask, bit shift] 72 * definitions. 73 * The target should use the struct def, for simplicity and clarity, 74 * but the host shall use the bit-mast + bit-shift defs, to be endian- 75 * neutral. Specifically, the host shall use the get/set macros built 76 * around the mask + shift defs. 77 */ 78 struct htt_data_tx_desc_frag { 79 union { 80 struct double_word_addr { 81 __le32 paddr; 82 __le32 len; 83 } __packed dword_addr; 84 struct triple_word_addr { 85 __le32 paddr_lo; 86 __le16 paddr_hi; 87 __le16 len_16; 88 } __packed tword_addr; 89 } __packed; 90 } __packed; 91 92 struct htt_msdu_ext_desc { 93 __le32 tso_flag[3]; 94 __le16 ip_identification; 95 u8 flags; 96 u8 reserved; 97 struct htt_data_tx_desc_frag frags[6]; 98 }; 99 100 struct htt_msdu_ext_desc_64 { 101 __le32 tso_flag[5]; 102 __le16 ip_identification; 103 u8 flags; 104 u8 reserved; 105 struct htt_data_tx_desc_frag frags[6]; 106 }; 107 108 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0) 109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1) 110 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2) 111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3) 112 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4) 113 114 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \ 115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \ 116 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \ 117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \ 118 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE) 119 120 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16) 121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17) 122 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18) 123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19) 124 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20) 125 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21) 126 127 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \ 128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \ 129 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \ 130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \ 131 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64) 132 133 enum htt_data_tx_desc_flags0 { 134 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0, 135 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1, 136 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2, 137 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3, 138 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4 139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0 140 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 141 }; 142 143 enum htt_data_tx_desc_flags1 { 144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F 146 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0 149 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 150 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11, 151 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12, 152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13, 153 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14, 154 HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE = 1 << 15 155 }; 156 157 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 158 #define HTT_TX_CREDIT_DELTA_ABS_S 16 159 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ 160 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) 161 162 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 163 #define HTT_TX_CREDIT_SIGN_BIT_S 8 164 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ 165 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) 166 167 enum htt_data_tx_ext_tid { 168 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16, 169 HTT_DATA_TX_EXT_TID_MGMT = 17, 170 HTT_DATA_TX_EXT_TID_INVALID = 31 171 }; 172 173 #define HTT_INVALID_PEERID 0xFFFF 174 175 /* 176 * htt_data_tx_desc - used for data tx path 177 * 178 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. 179 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ 180 * for special kinds of tids 181 * postponed: only for HL hosts. indicates if this is a resend 182 * (HL hosts manage queues on the host ) 183 * more_in_batch: only for HL hosts. indicates if more packets are 184 * pending. this allows target to wait and aggregate 185 * freq: 0 means home channel of given vdev. intended for offchannel 186 */ 187 struct htt_data_tx_desc { 188 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 189 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 190 __le16 len; 191 __le16 id; 192 __le32 frags_paddr; 193 union { 194 __le32 peerid; 195 struct { 196 __le16 peerid; 197 __le16 freq; 198 } __packed offchan_tx; 199 } __packed; 200 u8 prefetch[0]; /* start of frame, for FW classification engine */ 201 } __packed; 202 203 struct htt_data_tx_desc_64 { 204 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */ 205 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */ 206 __le16 len; 207 __le16 id; 208 __le64 frags_paddr; 209 union { 210 __le32 peerid; 211 struct { 212 __le16 peerid; 213 __le16 freq; 214 } __packed offchan_tx; 215 } __packed; 216 u8 prefetch[0]; /* start of frame, for FW classification engine */ 217 } __packed; 218 219 enum htt_rx_ring_flags { 220 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0, 221 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1, 222 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2, 223 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3, 224 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4, 225 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5, 226 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6, 227 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7, 228 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8, 229 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9, 230 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10, 231 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11, 232 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12, 233 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13, 234 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14, 235 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15 236 }; 237 238 #define HTT_RX_RING_SIZE_MIN 128 239 #define HTT_RX_RING_SIZE_MAX 2048 240 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX 241 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1) 242 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1) 243 244 struct htt_rx_ring_rx_desc_offsets { 245 /* the following offsets are in 4-byte units */ 246 __le16 mac80211_hdr_offset; 247 __le16 msdu_payload_offset; 248 __le16 ppdu_start_offset; 249 __le16 ppdu_end_offset; 250 __le16 mpdu_start_offset; 251 __le16 mpdu_end_offset; 252 __le16 msdu_start_offset; 253 __le16 msdu_end_offset; 254 __le16 rx_attention_offset; 255 __le16 frag_info_offset; 256 } __packed; 257 258 struct htt_rx_ring_setup_ring32 { 259 __le32 fw_idx_shadow_reg_paddr; 260 __le32 rx_ring_base_paddr; 261 __le16 rx_ring_len; /* in 4-byte words */ 262 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 263 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 264 __le16 fw_idx_init_val; 265 266 struct htt_rx_ring_rx_desc_offsets offsets; 267 } __packed; 268 269 struct htt_rx_ring_setup_ring64 { 270 __le64 fw_idx_shadow_reg_paddr; 271 __le64 rx_ring_base_paddr; 272 __le16 rx_ring_len; /* in 4-byte words */ 273 __le16 rx_ring_bufsize; /* rx skb size - in bytes */ 274 __le16 flags; /* %HTT_RX_RING_FLAGS_ */ 275 __le16 fw_idx_init_val; 276 277 struct htt_rx_ring_rx_desc_offsets offsets; 278 } __packed; 279 280 struct htt_rx_ring_setup_hdr { 281 u8 num_rings; /* supported values: 1, 2 */ 282 __le16 rsvd0; 283 } __packed; 284 285 struct htt_rx_ring_setup_32 { 286 struct htt_rx_ring_setup_hdr hdr; 287 struct htt_rx_ring_setup_ring32 rings[]; 288 } __packed; 289 290 struct htt_rx_ring_setup_64 { 291 struct htt_rx_ring_setup_hdr hdr; 292 struct htt_rx_ring_setup_ring64 rings[]; 293 } __packed; 294 295 /* 296 * htt_stats_req - request target to send specified statistics 297 * 298 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ 299 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually 300 * so make sure its little-endian. 301 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually 302 * so make sure its little-endian. 303 * @cfg_val: stat_type specific configuration 304 * @stat_type: see %htt_dbg_stats_type 305 * @cookie_lsb: used for confirmation message from target->host 306 * @cookie_msb: ditto as %cookie 307 */ 308 struct htt_stats_req { 309 u8 upload_types[3]; 310 u8 rsvd0; 311 u8 reset_types[3]; 312 struct { 313 u8 mpdu_bytes; 314 u8 mpdu_num_msdus; 315 u8 msdu_bytes; 316 } __packed; 317 u8 stat_type; 318 __le32 cookie_lsb; 319 __le32 cookie_msb; 320 } __packed; 321 322 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff 323 #define HTT_STATS_BIT_MASK GENMASK(16, 0) 324 325 /* 326 * htt_oob_sync_req - request out-of-band sync 327 * 328 * The HTT SYNC tells the target to suspend processing of subsequent 329 * HTT host-to-target messages until some other target agent locally 330 * informs the target HTT FW that the current sync counter is equal to 331 * or greater than (in a modulo sense) the sync counter specified in 332 * the SYNC message. 333 * 334 * This allows other host-target components to synchronize their operation 335 * with HTT, e.g. to ensure that tx frames don't get transmitted until a 336 * security key has been downloaded to and activated by the target. 337 * In the absence of any explicit synchronization counter value 338 * specification, the target HTT FW will use zero as the default current 339 * sync value. 340 * 341 * The HTT target FW will suspend its host->target message processing as long 342 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128. 343 */ 344 struct htt_oob_sync_req { 345 u8 sync_count; 346 __le16 rsvd0; 347 } __packed; 348 349 struct htt_aggr_conf { 350 u8 max_num_ampdu_subframes; 351 /* amsdu_subframes is limited by 0x1F mask */ 352 u8 max_num_amsdu_subframes; 353 } __packed; 354 355 struct htt_aggr_conf_v2 { 356 u8 max_num_ampdu_subframes; 357 /* amsdu_subframes is limited by 0x1F mask */ 358 u8 max_num_amsdu_subframes; 359 u8 reserved; 360 } __packed; 361 362 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 363 struct htt_mgmt_tx_desc_qca99x0 { 364 __le32 rate; 365 } __packed; 366 367 struct htt_mgmt_tx_desc { 368 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)]; 369 __le32 msdu_paddr; 370 __le32 desc_id; 371 __le32 len; 372 __le32 vdev_id; 373 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; 374 union { 375 struct htt_mgmt_tx_desc_qca99x0 qca99x0; 376 } __packed; 377 } __packed; 378 379 enum htt_mgmt_tx_status { 380 HTT_MGMT_TX_STATUS_OK = 0, 381 HTT_MGMT_TX_STATUS_RETRY = 1, 382 HTT_MGMT_TX_STATUS_DROP = 2 383 }; 384 385 /*=== target -> host messages ===============================================*/ 386 387 enum htt_main_t2h_msg_type { 388 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0, 389 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1, 390 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2, 391 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3, 392 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 393 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5, 394 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6, 395 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 396 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8, 397 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9, 398 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 399 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb, 400 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 401 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 402 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 403 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10, 404 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 405 HTT_MAIN_T2H_MSG_TYPE_TEST, 406 /* keep this last */ 407 HTT_MAIN_T2H_NUM_MSGS 408 }; 409 410 enum htt_10x_t2h_msg_type { 411 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0, 412 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1, 413 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2, 414 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3, 415 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 416 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5, 417 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6, 418 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 419 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8, 420 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9, 421 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 422 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb, 423 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 424 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 425 HTT_10X_T2H_MSG_TYPE_TEST = 0xe, 426 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 427 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11, 428 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12, 429 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13, 430 /* keep this last */ 431 HTT_10X_T2H_NUM_MSGS 432 }; 433 434 enum htt_tlv_t2h_msg_type { 435 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0, 436 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1, 437 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2, 438 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3, 439 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 440 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5, 441 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6, 442 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 443 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8, 444 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9, 445 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 446 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb, 447 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */ 448 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 449 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 450 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, 451 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10, 452 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, 453 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, 454 /* 0x13 reservd */ 455 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, 456 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, 457 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, 458 HTT_TLV_T2H_MSG_TYPE_TEST, 459 /* keep this last */ 460 HTT_TLV_T2H_NUM_MSGS 461 }; 462 463 enum htt_10_4_t2h_msg_type { 464 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0, 465 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1, 466 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2, 467 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3, 468 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 469 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5, 470 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6, 471 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, 472 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8, 473 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9, 474 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, 475 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb, 476 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, 477 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, 478 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, 479 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf, 480 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10, 481 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11, 482 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12, 483 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13, 484 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14, 485 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15, 486 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16, 487 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17, 488 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18, 489 /* 0x19 to 0x2f are reserved */ 490 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30, 491 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31, 492 /* keep this last */ 493 HTT_10_4_T2H_NUM_MSGS 494 }; 495 496 enum htt_t2h_msg_type { 497 HTT_T2H_MSG_TYPE_VERSION_CONF, 498 HTT_T2H_MSG_TYPE_RX_IND, 499 HTT_T2H_MSG_TYPE_RX_FLUSH, 500 HTT_T2H_MSG_TYPE_PEER_MAP, 501 HTT_T2H_MSG_TYPE_PEER_UNMAP, 502 HTT_T2H_MSG_TYPE_RX_ADDBA, 503 HTT_T2H_MSG_TYPE_RX_DELBA, 504 HTT_T2H_MSG_TYPE_TX_COMPL_IND, 505 HTT_T2H_MSG_TYPE_PKTLOG, 506 HTT_T2H_MSG_TYPE_STATS_CONF, 507 HTT_T2H_MSG_TYPE_RX_FRAG_IND, 508 HTT_T2H_MSG_TYPE_SEC_IND, 509 HTT_T2H_MSG_TYPE_RC_UPDATE_IND, 510 HTT_T2H_MSG_TYPE_TX_INSPECT_IND, 511 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION, 512 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, 513 HTT_T2H_MSG_TYPE_RX_PN_IND, 514 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND, 515 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND, 516 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE, 517 HTT_T2H_MSG_TYPE_CHAN_CHANGE, 518 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR, 519 HTT_T2H_MSG_TYPE_AGGR_CONF, 520 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD, 521 HTT_T2H_MSG_TYPE_TEST, 522 HTT_T2H_MSG_TYPE_EN_STATS, 523 HTT_T2H_MSG_TYPE_TX_FETCH_IND, 524 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM, 525 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND, 526 HTT_T2H_MSG_TYPE_PEER_STATS, 527 /* keep this last */ 528 HTT_T2H_NUM_MSGS 529 }; 530 531 /* 532 * htt_resp_hdr - header for target-to-host messages 533 * 534 * msg_type: see htt_t2h_msg_type 535 */ 536 struct htt_resp_hdr { 537 u8 msg_type; 538 } __packed; 539 540 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 541 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff 542 #define HTT_RESP_HDR_MSG_TYPE_LSB 0 543 544 /* htt_ver_resp - response sent for htt_ver_req */ 545 struct htt_ver_resp { 546 u8 minor; 547 u8 major; 548 u8 rsvd0; 549 } __packed; 550 551 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0) 552 553 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0) 554 555 struct htt_mgmt_tx_completion { 556 u8 rsvd0; 557 u8 rsvd1; 558 u8 flags; 559 __le32 desc_id; 560 __le32 status; 561 __le32 ppdu_id; 562 __le32 info; 563 } __packed; 564 565 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F) 566 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0) 567 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5) 568 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6) 569 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7) 570 571 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F 572 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 573 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0 574 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 575 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000 576 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 577 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000 578 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 579 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000 580 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 581 582 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0) 583 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1) 584 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2) 585 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3) 586 587 #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3) 588 #define HTT_TX_DATA_APPEND_RETRIES BIT(0) 589 #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1) 590 591 struct htt_rx_indication_hdr { 592 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */ 593 __le16 peer_id; 594 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */ 595 } __packed; 596 597 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0) 598 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E) 599 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1) 600 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5) 601 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6) 602 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7) 603 604 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF 605 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 606 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000 607 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 608 609 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF 610 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 611 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000 612 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 613 614 enum htt_rx_legacy_rate { 615 HTT_RX_OFDM_48 = 0, 616 HTT_RX_OFDM_24 = 1, 617 HTT_RX_OFDM_12, 618 HTT_RX_OFDM_6, 619 HTT_RX_OFDM_54, 620 HTT_RX_OFDM_36, 621 HTT_RX_OFDM_18, 622 HTT_RX_OFDM_9, 623 624 /* long preamble */ 625 HTT_RX_CCK_11_LP = 0, 626 HTT_RX_CCK_5_5_LP = 1, 627 HTT_RX_CCK_2_LP, 628 HTT_RX_CCK_1_LP, 629 /* short preamble */ 630 HTT_RX_CCK_11_SP, 631 HTT_RX_CCK_5_5_SP, 632 HTT_RX_CCK_2_SP 633 }; 634 635 enum htt_rx_legacy_rate_type { 636 HTT_RX_LEGACY_RATE_OFDM = 0, 637 HTT_RX_LEGACY_RATE_CCK 638 }; 639 640 enum htt_rx_preamble_type { 641 HTT_RX_LEGACY = 0x4, 642 HTT_RX_HT = 0x8, 643 HTT_RX_HT_WITH_TXBF = 0x9, 644 HTT_RX_VHT = 0xC, 645 HTT_RX_VHT_WITH_TXBF = 0xD, 646 }; 647 648 /* 649 * Fields: phy_err_valid, phy_err_code, tsf, 650 * usec_timestamp, sub_usec_timestamp 651 * ..are valid only if end_valid == 1. 652 * 653 * Fields: rssi_chains, legacy_rate_type, 654 * legacy_rate_cck, preamble_type, service, 655 * vht_sig_* 656 * ..are valid only if start_valid == 1; 657 */ 658 struct htt_rx_indication_ppdu { 659 u8 combined_rssi; 660 u8 sub_usec_timestamp; 661 u8 phy_err_code; 662 u8 info0; /* HTT_RX_INDICATION_INFO0_ */ 663 struct { 664 u8 pri20_db; 665 u8 ext20_db; 666 u8 ext40_db; 667 u8 ext80_db; 668 } __packed rssi_chains[4]; 669 __le32 tsf; 670 __le32 usec_timestamp; 671 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */ 672 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */ 673 } __packed; 674 675 enum htt_rx_mpdu_status { 676 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0, 677 HTT_RX_IND_MPDU_STATUS_OK, 678 HTT_RX_IND_MPDU_STATUS_ERR_FCS, 679 HTT_RX_IND_MPDU_STATUS_ERR_DUP, 680 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY, 681 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER, 682 /* only accept EAPOL frames */ 683 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, 684 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC, 685 /* Non-data in promiscuous mode */ 686 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, 687 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR, 688 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR, 689 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR, 690 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR, 691 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR, 692 693 /* 694 * MISC: discard for unspecified reasons. 695 * Leave this enum value last. 696 */ 697 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF 698 }; 699 700 struct htt_rx_indication_mpdu_range { 701 u8 mpdu_count; 702 u8 mpdu_range_status; /* %htt_rx_mpdu_status */ 703 u8 pad0; 704 u8 pad1; 705 } __packed; 706 707 struct htt_rx_indication_prefix { 708 __le16 fw_rx_desc_bytes; 709 u8 pad0; 710 u8 pad1; 711 } __packed; 712 713 struct htt_rx_indication { 714 struct htt_rx_indication_hdr hdr; 715 struct htt_rx_indication_ppdu ppdu; 716 struct htt_rx_indication_prefix prefix; 717 718 /* 719 * the following fields are both dynamically sized, so 720 * take care addressing them 721 */ 722 723 /* the size of this is %fw_rx_desc_bytes */ 724 struct fw_rx_desc_base fw_desc; 725 726 /* 727 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4) 728 * and has %num_mpdu_ranges elements. 729 */ 730 struct htt_rx_indication_mpdu_range mpdu_ranges[]; 731 } __packed; 732 733 /* High latency version of the RX indication */ 734 struct htt_rx_indication_hl { 735 struct htt_rx_indication_hdr hdr; 736 struct htt_rx_indication_ppdu ppdu; 737 struct htt_rx_indication_prefix prefix; 738 struct fw_rx_desc_hl fw_desc; 739 struct htt_rx_indication_mpdu_range mpdu_ranges[]; 740 } __packed; 741 742 struct htt_hl_rx_desc { 743 __le32 info; 744 __le32 pn_31_0; 745 union { 746 struct { 747 __le16 pn_47_32; 748 __le16 pn_63_48; 749 } pn16; 750 __le32 pn_63_32; 751 } u0; 752 __le32 pn_95_64; 753 __le32 pn_127_96; 754 } __packed; 755 756 static inline struct htt_rx_indication_mpdu_range * htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication * rx_ind)757 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind) 758 { 759 void *ptr = rx_ind; 760 761 ptr += sizeof(rx_ind->hdr) 762 + sizeof(rx_ind->ppdu) 763 + sizeof(rx_ind->prefix) 764 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4); 765 return ptr; 766 } 767 768 static inline struct htt_rx_indication_mpdu_range * htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl * rx_ind)769 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind) 770 { 771 void *ptr = rx_ind; 772 773 ptr += sizeof(rx_ind->hdr) 774 + sizeof(rx_ind->ppdu) 775 + sizeof(rx_ind->prefix) 776 + sizeof(rx_ind->fw_desc); 777 return ptr; 778 } 779 780 enum htt_rx_flush_mpdu_status { 781 HTT_RX_FLUSH_MPDU_DISCARD = 0, 782 HTT_RX_FLUSH_MPDU_REORDER = 1, 783 }; 784 785 /* 786 * htt_rx_flush - discard or reorder given range of mpdus 787 * 788 * Note: host must check if all sequence numbers between 789 * [seq_num_start, seq_num_end-1] are valid. 790 */ 791 struct htt_rx_flush { 792 __le16 peer_id; 793 u8 tid; 794 u8 rsvd0; 795 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */ 796 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */ 797 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */ 798 }; 799 800 struct htt_rx_peer_map { 801 u8 vdev_id; 802 __le16 peer_id; 803 u8 addr[6]; 804 u8 rsvd0; 805 u8 rsvd1; 806 } __packed; 807 808 struct htt_rx_peer_unmap { 809 u8 rsvd0; 810 __le16 peer_id; 811 } __packed; 812 813 enum htt_txrx_sec_cast_type { 814 HTT_TXRX_SEC_MCAST = 0, 815 HTT_TXRX_SEC_UCAST 816 }; 817 818 enum htt_rx_pn_check_type { 819 HTT_RX_NON_PN_CHECK = 0, 820 HTT_RX_PN_CHECK 821 }; 822 823 enum htt_rx_tkip_demic_type { 824 HTT_RX_NON_TKIP_MIC = 0, 825 HTT_RX_TKIP_MIC 826 }; 827 828 enum htt_security_types { 829 HTT_SECURITY_NONE, 830 HTT_SECURITY_WEP128, 831 HTT_SECURITY_WEP104, 832 HTT_SECURITY_WEP40, 833 HTT_SECURITY_TKIP, 834 HTT_SECURITY_TKIP_NOMIC, 835 HTT_SECURITY_AES_CCMP, 836 HTT_SECURITY_WAPI, 837 838 HTT_NUM_SECURITY_TYPES /* keep this last! */ 839 }; 840 841 #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX 2 842 #define ATH10K_TXRX_NUM_EXT_TIDS 19 843 #define ATH10K_TXRX_NON_QOS_TID 16 844 845 enum htt_security_flags { 846 #define HTT_SECURITY_TYPE_MASK 0x7F 847 #define HTT_SECURITY_TYPE_LSB 0 848 HTT_SECURITY_IS_UNICAST = 1 << 7 849 }; 850 851 struct htt_security_indication { 852 union { 853 /* dont use bitfields; undefined behaviour */ 854 u8 flags; /* %htt_security_flags */ 855 struct { 856 u8 security_type:7, /* %htt_security_types */ 857 is_unicast:1; 858 } __packed; 859 } __packed; 860 __le16 peer_id; 861 u8 michael_key[8]; 862 u8 wapi_rsc[16]; 863 } __packed; 864 865 #define HTT_RX_BA_INFO0_TID_MASK 0x000F 866 #define HTT_RX_BA_INFO0_TID_LSB 0 867 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0 868 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4 869 870 struct htt_rx_addba { 871 u8 window_size; 872 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 873 } __packed; 874 875 struct htt_rx_delba { 876 u8 rsvd0; 877 __le16 info0; /* %HTT_RX_BA_INFO0_ */ 878 } __packed; 879 880 enum htt_data_tx_status { 881 HTT_DATA_TX_STATUS_OK = 0, 882 HTT_DATA_TX_STATUS_DISCARD = 1, 883 HTT_DATA_TX_STATUS_NO_ACK = 2, 884 HTT_DATA_TX_STATUS_POSTPONE = 3 /* HL only */ 885 }; 886 887 enum htt_data_tx_flags { 888 #define HTT_DATA_TX_STATUS_MASK 0x07 889 #define HTT_DATA_TX_STATUS_LSB 0 890 #define HTT_DATA_TX_TID_MASK 0x78 891 #define HTT_DATA_TX_TID_LSB 3 892 HTT_DATA_TX_TID_INVALID = 1 << 7 893 }; 894 895 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF 896 897 struct htt_append_retries { 898 __le16 msdu_id; 899 u8 tx_retries; 900 u8 flag; 901 } __packed; 902 903 struct htt_data_tx_completion_ext { 904 struct htt_append_retries a_retries; 905 __le32 t_stamp; 906 __le16 msdus_rssi[]; 907 } __packed; 908 909 /* 910 * @brief target -> host TX completion indication message definition 911 * 912 * @details 913 * The following diagram shows the format of the TX completion indication sent 914 * from the target to the host 915 * 916 * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| 917 * |-------------------------------------------------------------| 918 * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | 919 * |-------------------------------------------------------------| 920 * payload: | MSDU1 ID | MSDU0 ID | 921 * |-------------------------------------------------------------| 922 * : MSDU3 ID : MSDU2 ID : 923 * |-------------------------------------------------------------| 924 * | struct htt_tx_compl_ind_append_retries | 925 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 926 * | struct htt_tx_compl_ind_append_tx_tstamp | 927 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 928 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | 929 * |-------------------------------------------------------------| 930 * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : 931 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| 932 * -msg_type 933 * Bits 7:0 934 * Purpose: identifies this as HTT TX completion indication 935 * -status 936 * Bits 10:8 937 * Purpose: the TX completion status of payload fragmentations descriptors 938 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD 939 * -tid 940 * Bits 14:11 941 * Purpose: the tid associated with those fragmentation descriptors. It is 942 * valid or not, depending on the tid_invalid bit. 943 * Value: 0 to 15 944 * -tid_invalid 945 * Bits 15:15 946 * Purpose: this bit indicates whether the tid field is valid or not 947 * Value: 0 indicates valid, 1 indicates invalid 948 * -num 949 * Bits 23:16 950 * Purpose: the number of payload in this indication 951 * Value: 1 to 255 952 * -A0 = append 953 * Bits 24:24 954 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains 955 * the number of tx retries for one MSDU at the end of this message 956 * Value: 0 indicates no appending, 1 indicates appending 957 * -A1 = append1 958 * Bits 25:25 959 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which 960 * contains the timestamp info for each TX msdu id in payload. 961 * Value: 0 indicates no appending, 1 indicates appending 962 * -TP = MSDU tx power presence 963 * Bits 26:26 964 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report 965 * for each MSDU referenced by the TX_COMPL_IND message. 966 * The order of the per-MSDU tx power reports matches the order 967 * of the MSDU IDs. 968 * Value: 0 indicates not appending, 1 indicates appending 969 * -A2 = append2 970 * Bits 27:27 971 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in 972 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report 973 * matches the order of the MSDU IDs. 974 * The ACK RSSI values are valid when status is COMPLETE_OK (and 975 * this append2 bit is set). 976 * Value: 0 indicates not appending, 1 indicates appending 977 */ 978 979 struct htt_data_tx_completion { 980 union { 981 u8 flags; 982 struct { 983 u8 status:3, 984 tid:4, 985 tid_invalid:1; 986 } __packed; 987 } __packed; 988 u8 num_msdus; 989 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */ 990 __le16 msdus[]; /* variable length based on %num_msdus */ 991 } __packed; 992 993 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0) 994 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16) 995 996 struct htt_data_tx_ppdu_dur { 997 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */ 998 __le32 tx_duration; /* in usecs */ 999 } __packed; 1000 1001 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0) 1002 1003 struct htt_data_tx_compl_ppdu_dur { 1004 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */ 1005 struct htt_data_tx_ppdu_dur ppdu_dur[]; 1006 } __packed; 1007 1008 struct htt_tx_compl_ind_base { 1009 u32 hdr; 1010 u16 payload[1/*or more*/]; 1011 } __packed; 1012 1013 struct htt_rc_tx_done_params { 1014 u32 rate_code; 1015 u32 rate_code_flags; 1016 u32 flags; 1017 u32 num_enqued; /* 1 for non-AMPDU */ 1018 u32 num_retries; 1019 u32 num_failed; /* for AMPDU */ 1020 u32 ack_rssi; 1021 u32 time_stamp; 1022 u32 is_probe; 1023 }; 1024 1025 struct htt_rc_update { 1026 u8 vdev_id; 1027 __le16 peer_id; 1028 u8 addr[6]; 1029 u8 num_elems; 1030 u8 rsvd0; 1031 struct htt_rc_tx_done_params params[]; /* variable length %num_elems */ 1032 } __packed; 1033 1034 /* see htt_rx_indication for similar fields and descriptions */ 1035 struct htt_rx_fragment_indication { 1036 union { 1037 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */ 1038 struct { 1039 u8 ext_tid:5, 1040 flush_valid:1; 1041 } __packed; 1042 } __packed; 1043 __le16 peer_id; 1044 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */ 1045 __le16 fw_rx_desc_bytes; 1046 __le16 rsvd0; 1047 1048 u8 fw_msdu_rx_desc[]; 1049 } __packed; 1050 1051 #define ATH10K_IEEE80211_EXTIV BIT(5) 1052 #define ATH10K_IEEE80211_TKIP_MICLEN 8 /* trailing MIC */ 1053 1054 #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN 16 1055 1056 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F 1057 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 1058 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20 1059 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 1060 1061 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F 1062 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 1063 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0 1064 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 1065 1066 struct htt_rx_pn_ind { 1067 __le16 peer_id; 1068 u8 tid; 1069 u8 seqno_start; 1070 u8 seqno_end; 1071 u8 pn_ie_count; 1072 u8 reserved; 1073 u8 pn_ies[]; 1074 } __packed; 1075 1076 struct htt_rx_offload_msdu { 1077 __le16 msdu_len; 1078 __le16 peer_id; 1079 u8 vdev_id; 1080 u8 tid; 1081 u8 fw_desc; 1082 u8 payload[]; 1083 } __packed; 1084 1085 struct htt_rx_offload_ind { 1086 u8 reserved; 1087 __le16 msdu_count; 1088 } __packed; 1089 1090 struct htt_rx_in_ord_msdu_desc { 1091 __le32 msdu_paddr; 1092 __le16 msdu_len; 1093 u8 fw_desc; 1094 u8 reserved; 1095 } __packed; 1096 1097 struct htt_rx_in_ord_msdu_desc_ext { 1098 __le64 msdu_paddr; 1099 __le16 msdu_len; 1100 u8 fw_desc; 1101 u8 reserved; 1102 } __packed; 1103 1104 struct htt_rx_in_ord_ind { 1105 u8 info; 1106 __le16 peer_id; 1107 u8 vdev_id; 1108 u8 reserved; 1109 __le16 msdu_count; 1110 union { 1111 DECLARE_FLEX_ARRAY(struct htt_rx_in_ord_msdu_desc, 1112 msdu_descs32); 1113 DECLARE_FLEX_ARRAY(struct htt_rx_in_ord_msdu_desc_ext, 1114 msdu_descs64); 1115 } __packed; 1116 } __packed; 1117 1118 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f 1119 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 1120 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020 1121 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 1122 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040 1123 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 1124 1125 /* 1126 * target -> host test message definition 1127 * 1128 * The following field definitions describe the format of the test 1129 * message sent from the target to the host. 1130 * The message consists of a 4-octet header, followed by a variable 1131 * number of 32-bit integer values, followed by a variable number 1132 * of 8-bit character values. 1133 * 1134 * |31 16|15 8|7 0| 1135 * |-----------------------------------------------------------| 1136 * | num chars | num ints | msg type | 1137 * |-----------------------------------------------------------| 1138 * | int 0 | 1139 * |-----------------------------------------------------------| 1140 * | int 1 | 1141 * |-----------------------------------------------------------| 1142 * | ... | 1143 * |-----------------------------------------------------------| 1144 * | char 3 | char 2 | char 1 | char 0 | 1145 * |-----------------------------------------------------------| 1146 * | | | ... | char 4 | 1147 * |-----------------------------------------------------------| 1148 * - MSG_TYPE 1149 * Bits 7:0 1150 * Purpose: identifies this as a test message 1151 * Value: HTT_MSG_TYPE_TEST 1152 * - NUM_INTS 1153 * Bits 15:8 1154 * Purpose: indicate how many 32-bit integers follow the message header 1155 * - NUM_CHARS 1156 * Bits 31:16 1157 * Purpose: indicate how many 8-bit characters follow the series of integers 1158 */ 1159 struct htt_rx_test { 1160 u8 num_ints; 1161 __le16 num_chars; 1162 1163 /* payload consists of 2 lists: 1164 * a) num_ints * sizeof(__le32) 1165 * b) num_chars * sizeof(u8) aligned to 4bytes 1166 */ 1167 u8 payload[]; 1168 } __packed; 1169 htt_rx_test_get_ints(struct htt_rx_test * rx_test)1170 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test) 1171 { 1172 return (__le32 *)rx_test->payload; 1173 } 1174 htt_rx_test_get_chars(struct htt_rx_test * rx_test)1175 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test) 1176 { 1177 return rx_test->payload + (rx_test->num_ints * sizeof(__le32)); 1178 } 1179 1180 /* 1181 * target -> host packet log message 1182 * 1183 * The following field definitions describe the format of the packet log 1184 * message sent from the target to the host. 1185 * The message consists of a 4-octet header,followed by a variable number 1186 * of 32-bit character values. 1187 * 1188 * |31 24|23 16|15 8|7 0| 1189 * |-----------------------------------------------------------| 1190 * | | | | msg type | 1191 * |-----------------------------------------------------------| 1192 * | payload | 1193 * |-----------------------------------------------------------| 1194 * - MSG_TYPE 1195 * Bits 7:0 1196 * Purpose: identifies this as a test message 1197 * Value: HTT_MSG_TYPE_PACKETLOG 1198 */ 1199 struct htt_pktlog_msg { 1200 u8 pad[3]; 1201 u8 payload[]; 1202 } __packed; 1203 1204 struct htt_dbg_stats_rx_reorder_stats { 1205 /* Non QoS MPDUs received */ 1206 __le32 deliver_non_qos; 1207 1208 /* MPDUs received in-order */ 1209 __le32 deliver_in_order; 1210 1211 /* Flush due to reorder timer expired */ 1212 __le32 deliver_flush_timeout; 1213 1214 /* Flush due to move out of window */ 1215 __le32 deliver_flush_oow; 1216 1217 /* Flush due to DELBA */ 1218 __le32 deliver_flush_delba; 1219 1220 /* MPDUs dropped due to FCS error */ 1221 __le32 fcs_error; 1222 1223 /* MPDUs dropped due to monitor mode non-data packet */ 1224 __le32 mgmt_ctrl; 1225 1226 /* MPDUs dropped due to invalid peer */ 1227 __le32 invalid_peer; 1228 1229 /* MPDUs dropped due to duplication (non aggregation) */ 1230 __le32 dup_non_aggr; 1231 1232 /* MPDUs dropped due to processed before */ 1233 __le32 dup_past; 1234 1235 /* MPDUs dropped due to duplicate in reorder queue */ 1236 __le32 dup_in_reorder; 1237 1238 /* Reorder timeout happened */ 1239 __le32 reorder_timeout; 1240 1241 /* invalid bar ssn */ 1242 __le32 invalid_bar_ssn; 1243 1244 /* reorder reset due to bar ssn */ 1245 __le32 ssn_reset; 1246 }; 1247 1248 struct htt_dbg_stats_wal_tx_stats { 1249 /* Num HTT cookies queued to dispatch list */ 1250 __le32 comp_queued; 1251 1252 /* Num HTT cookies dispatched */ 1253 __le32 comp_delivered; 1254 1255 /* Num MSDU queued to WAL */ 1256 __le32 msdu_enqued; 1257 1258 /* Num MPDU queue to WAL */ 1259 __le32 mpdu_enqued; 1260 1261 /* Num MSDUs dropped by WMM limit */ 1262 __le32 wmm_drop; 1263 1264 /* Num Local frames queued */ 1265 __le32 local_enqued; 1266 1267 /* Num Local frames done */ 1268 __le32 local_freed; 1269 1270 /* Num queued to HW */ 1271 __le32 hw_queued; 1272 1273 /* Num PPDU reaped from HW */ 1274 __le32 hw_reaped; 1275 1276 /* Num underruns */ 1277 __le32 underrun; 1278 1279 /* Num PPDUs cleaned up in TX abort */ 1280 __le32 tx_abort; 1281 1282 /* Num MPDUs requeued by SW */ 1283 __le32 mpdus_requeued; 1284 1285 /* excessive retries */ 1286 __le32 tx_ko; 1287 1288 /* data hw rate code */ 1289 __le32 data_rc; 1290 1291 /* Scheduler self triggers */ 1292 __le32 self_triggers; 1293 1294 /* frames dropped due to excessive sw retries */ 1295 __le32 sw_retry_failure; 1296 1297 /* illegal rate phy errors */ 1298 __le32 illgl_rate_phy_err; 1299 1300 /* wal pdev continuous xretry */ 1301 __le32 pdev_cont_xretry; 1302 1303 /* wal pdev continuous xretry */ 1304 __le32 pdev_tx_timeout; 1305 1306 /* wal pdev resets */ 1307 __le32 pdev_resets; 1308 1309 __le32 phy_underrun; 1310 1311 /* MPDU is more than txop limit */ 1312 __le32 txop_ovf; 1313 } __packed; 1314 1315 struct htt_dbg_stats_wal_rx_stats { 1316 /* Cnts any change in ring routing mid-ppdu */ 1317 __le32 mid_ppdu_route_change; 1318 1319 /* Total number of statuses processed */ 1320 __le32 status_rcvd; 1321 1322 /* Extra frags on rings 0-3 */ 1323 __le32 r0_frags; 1324 __le32 r1_frags; 1325 __le32 r2_frags; 1326 __le32 r3_frags; 1327 1328 /* MSDUs / MPDUs delivered to HTT */ 1329 __le32 htt_msdus; 1330 __le32 htt_mpdus; 1331 1332 /* MSDUs / MPDUs delivered to local stack */ 1333 __le32 loc_msdus; 1334 __le32 loc_mpdus; 1335 1336 /* AMSDUs that have more MSDUs than the status ring size */ 1337 __le32 oversize_amsdu; 1338 1339 /* Number of PHY errors */ 1340 __le32 phy_errs; 1341 1342 /* Number of PHY errors drops */ 1343 __le32 phy_err_drop; 1344 1345 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1346 __le32 mpdu_errs; 1347 } __packed; 1348 1349 struct htt_dbg_stats_wal_peer_stats { 1350 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 1351 } __packed; 1352 1353 struct htt_dbg_stats_wal_pdev_txrx { 1354 struct htt_dbg_stats_wal_tx_stats tx_stats; 1355 struct htt_dbg_stats_wal_rx_stats rx_stats; 1356 struct htt_dbg_stats_wal_peer_stats peer_stats; 1357 } __packed; 1358 1359 struct htt_dbg_stats_rx_rate_info { 1360 __le32 mcs[10]; 1361 __le32 sgi[10]; 1362 __le32 nss[4]; 1363 __le32 stbc[10]; 1364 __le32 bw[3]; 1365 __le32 pream[6]; 1366 __le32 ldpc; 1367 __le32 txbf; 1368 }; 1369 1370 /* 1371 * htt_dbg_stats_status - 1372 * present - The requested stats have been delivered in full. 1373 * This indicates that either the stats information was contained 1374 * in its entirety within this message, or else this message 1375 * completes the delivery of the requested stats info that was 1376 * partially delivered through earlier STATS_CONF messages. 1377 * partial - The requested stats have been delivered in part. 1378 * One or more subsequent STATS_CONF messages with the same 1379 * cookie value will be sent to deliver the remainder of the 1380 * information. 1381 * error - The requested stats could not be delivered, for example due 1382 * to a shortage of memory to construct a message holding the 1383 * requested stats. 1384 * invalid - The requested stat type is either not recognized, or the 1385 * target is configured to not gather the stats type in question. 1386 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1387 * series_done - This special value indicates that no further stats info 1388 * elements are present within a series of stats info elems 1389 * (within a stats upload confirmation message). 1390 */ 1391 enum htt_dbg_stats_status { 1392 HTT_DBG_STATS_STATUS_PRESENT = 0, 1393 HTT_DBG_STATS_STATUS_PARTIAL = 1, 1394 HTT_DBG_STATS_STATUS_ERROR = 2, 1395 HTT_DBG_STATS_STATUS_INVALID = 3, 1396 HTT_DBG_STATS_STATUS_SERIES_DONE = 7 1397 }; 1398 1399 /* 1400 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank 1401 * 1402 * The following field definitions describe the format of the HTT host 1403 * to target frag_desc/msdu_ext bank configuration message. 1404 * The message contains the based address and the min and max id of the 1405 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and 1406 * MSDU_EXT/FRAG_DESC. 1407 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. 1408 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 1409 * the hardware does the mapping/translation. 1410 * 1411 * Total banks that can be configured is configured to 16. 1412 * 1413 * This should be called before any TX has be initiated by the HTT 1414 * 1415 * |31 16|15 8|7 5|4 0| 1416 * |------------------------------------------------------------| 1417 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | 1418 * |------------------------------------------------------------| 1419 * | BANK0_BASE_ADDRESS | 1420 * |------------------------------------------------------------| 1421 * | ... | 1422 * |------------------------------------------------------------| 1423 * | BANK15_BASE_ADDRESS | 1424 * |------------------------------------------------------------| 1425 * | BANK0_MAX_ID | BANK0_MIN_ID | 1426 * |------------------------------------------------------------| 1427 * | ... | 1428 * |------------------------------------------------------------| 1429 * | BANK15_MAX_ID | BANK15_MIN_ID | 1430 * |------------------------------------------------------------| 1431 * Header fields: 1432 * - MSG_TYPE 1433 * Bits 7:0 1434 * Value: 0x6 1435 * - BANKx_BASE_ADDRESS 1436 * Bits 31:0 1437 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT 1438 * bank physical/bus address. 1439 * - BANKx_MIN_ID 1440 * Bits 15:0 1441 * Purpose: Provide a mechanism to specify the min index that needs to 1442 * mapped. 1443 * - BANKx_MAX_ID 1444 * Bits 31:16 1445 * Purpose: Provide a mechanism to specify the max index that needs to 1446 * 1447 */ 1448 struct htt_frag_desc_bank_id { 1449 __le16 bank_min_id; 1450 __le16 bank_max_id; 1451 } __packed; 1452 1453 /* real is 16 but it wouldn't fit in the max htt message size 1454 * so we use a conservatively safe value for now 1455 */ 1456 #define HTT_FRAG_DESC_BANK_MAX 4 1457 1458 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03 1459 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 1460 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2) 1461 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3) 1462 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4) 1463 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 1464 1465 enum htt_q_depth_type { 1466 HTT_Q_DEPTH_TYPE_BYTES = 0, 1467 HTT_Q_DEPTH_TYPE_MSDUS = 1, 1468 }; 1469 1470 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \ 1471 TARGET_10_4_NUM_VDEVS) 1472 #define HTT_TX_Q_STATE_NUM_TIDS 8 1473 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 1474 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 1475 1476 /** 1477 * struct htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config 1478 * 1479 * Defines host q state format and behavior. See htt_q_state. 1480 * 1481 * @paddr: Queue physical address 1482 * @num_peers: Number of supported peers 1483 * @num_tids: Number of supported TIDs 1484 * @record_size: Defines the size of each host q entry in bytes. In practice 1485 * however firmware (at least 10.4.3-00191) ignores this host 1486 * configuration value and uses hardcoded value of 1. 1487 * @record_multiplier: This is valid only when q depth type is MSDUs. It 1488 * defines the exponent for the power of 2 multiplication. 1489 * @pad: struct padding for 32-bit alignment 1490 */ 1491 struct htt_q_state_conf { 1492 __le32 paddr; 1493 __le16 num_peers; 1494 __le16 num_tids; 1495 u8 record_size; 1496 u8 record_multiplier; 1497 u8 pad[2]; 1498 } __packed; 1499 1500 struct htt_frag_desc_bank_cfg32 { 1501 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1502 u8 num_banks; 1503 u8 desc_size; 1504 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1505 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1506 struct htt_q_state_conf q_state; 1507 } __packed; 1508 1509 struct htt_frag_desc_bank_cfg64 { 1510 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */ 1511 u8 num_banks; 1512 u8 desc_size; 1513 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX]; 1514 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX]; 1515 struct htt_q_state_conf q_state; 1516 } __packed; 1517 1518 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 1519 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f 1520 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 1521 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0 1522 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 1523 1524 /** 1525 * struct htt_q_state - shared between host and firmware via DMA 1526 * 1527 * This structure is used for the host to expose it's software queue state to 1528 * firmware so that its rate control can schedule fetch requests for optimized 1529 * performance. This is most notably used for MU-MIMO aggregation when multiple 1530 * MU clients are connected. 1531 * 1532 * @count: Each element defines the host queue depth. When q depth type was 1533 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: 1534 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and 1535 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as 1536 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** 1537 * record_multiplier (see htt_q_state_conf). 1538 * @map: Used by firmware to quickly check which host queues are not empty. It 1539 * is a bitmap simply saying. 1540 * @seq: Used by firmware to quickly check if the host queues were updated 1541 * since it last checked. 1542 * 1543 * FIXME: Is the q_state map[] size calculation really correct? 1544 */ 1545 struct htt_q_state { 1546 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS]; 1547 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32]; 1548 __le32 seq; 1549 } __packed; 1550 1551 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff 1552 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 1553 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000 1554 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 1555 1556 struct htt_tx_fetch_record { 1557 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */ 1558 __le16 num_msdus; 1559 __le32 num_bytes; 1560 } __packed; 1561 1562 struct htt_tx_fetch_ind { 1563 u8 pad0; 1564 __le16 fetch_seq_num; 1565 __le32 token; 1566 __le16 num_resp_ids; 1567 __le16 num_records; 1568 union { 1569 /* ath10k_htt_get_tx_fetch_ind_resp_ids() */ 1570 DECLARE_FLEX_ARRAY(__le32, resp_ids); 1571 DECLARE_FLEX_ARRAY(struct htt_tx_fetch_record, records); 1572 } __packed; 1573 } __packed; 1574 1575 static inline void * ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind * ind)1576 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind) 1577 { 1578 return (void *)&ind->records[le16_to_cpu(ind->num_records)]; 1579 } 1580 1581 struct htt_tx_fetch_resp { 1582 u8 pad0; 1583 __le16 resp_id; 1584 __le16 fetch_seq_num; 1585 __le16 num_records; 1586 __le32 token; 1587 struct htt_tx_fetch_record records[]; 1588 } __packed; 1589 1590 struct htt_tx_fetch_confirm { 1591 u8 pad0; 1592 __le16 num_resp_ids; 1593 __le32 resp_ids[]; 1594 } __packed; 1595 1596 enum htt_tx_mode_switch_mode { 1597 HTT_TX_MODE_SWITCH_PUSH = 0, 1598 HTT_TX_MODE_SWITCH_PUSH_PULL = 1, 1599 }; 1600 1601 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0) 1602 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe 1603 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 1604 1605 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003 1606 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 1607 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc 1608 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 1609 1610 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff 1611 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 1612 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000 1613 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 1614 1615 struct htt_tx_mode_switch_record { 1616 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ 1617 __le16 num_max_msdus; 1618 } __packed; 1619 1620 struct htt_tx_mode_switch_ind { 1621 u8 pad0; 1622 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */ 1623 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 1624 u8 pad1[2]; 1625 struct htt_tx_mode_switch_record records[]; 1626 } __packed; 1627 1628 struct htt_channel_change { 1629 u8 pad[3]; 1630 __le32 freq; 1631 __le32 center_freq1; 1632 __le32 center_freq2; 1633 __le32 phymode; 1634 } __packed; 1635 1636 struct htt_per_peer_tx_stats_ind { 1637 __le32 succ_bytes; 1638 __le32 retry_bytes; 1639 __le32 failed_bytes; 1640 u8 ratecode; 1641 u8 flags; 1642 __le16 peer_id; 1643 __le16 succ_pkts; 1644 __le16 retry_pkts; 1645 __le16 failed_pkts; 1646 __le16 tx_duration; 1647 __le32 reserved1; 1648 __le32 reserved2; 1649 } __packed; 1650 1651 struct htt_peer_tx_stats { 1652 u8 num_ppdu; 1653 u8 ppdu_len; 1654 u8 version; 1655 u8 payload[]; 1656 } __packed; 1657 1658 #define ATH10K_10_2_TX_STATS_OFFSET 136 1659 #define PEER_STATS_FOR_NO_OF_PPDUS 4 1660 1661 struct ath10k_10_2_peer_tx_stats { 1662 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; 1663 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1664 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1665 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1666 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1667 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; 1668 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; 1669 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; 1670 __le32 tx_duration; 1671 u8 tx_ppdu_cnt; 1672 u8 peer_id; 1673 } __packed; 1674 1675 union htt_rx_pn_t { 1676 /* WEP: 24-bit PN */ 1677 u32 pn24; 1678 1679 /* TKIP or CCMP: 48-bit PN */ 1680 u64 pn48; 1681 1682 /* WAPI: 128-bit PN */ 1683 u64 pn128[2]; 1684 }; 1685 1686 struct htt_cmd { 1687 struct htt_cmd_hdr hdr; 1688 union { 1689 struct htt_ver_req ver_req; 1690 struct htt_mgmt_tx_desc mgmt_tx; 1691 struct htt_data_tx_desc data_tx; 1692 struct htt_rx_ring_setup_32 rx_setup_32; 1693 struct htt_rx_ring_setup_64 rx_setup_64; 1694 struct htt_stats_req stats_req; 1695 struct htt_oob_sync_req oob_sync_req; 1696 struct htt_aggr_conf aggr_conf; 1697 struct htt_aggr_conf_v2 aggr_conf_v2; 1698 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32; 1699 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64; 1700 struct htt_tx_fetch_resp tx_fetch_resp; 1701 }; 1702 } __packed; 1703 1704 struct htt_resp { 1705 struct htt_resp_hdr hdr; 1706 union { 1707 struct htt_ver_resp ver_resp; 1708 struct htt_mgmt_tx_completion mgmt_tx_completion; 1709 struct htt_data_tx_completion data_tx_completion; 1710 struct htt_rx_indication rx_ind; 1711 struct htt_rx_indication_hl rx_ind_hl; 1712 struct htt_rx_fragment_indication rx_frag_ind; 1713 struct htt_rx_peer_map peer_map; 1714 struct htt_rx_peer_unmap peer_unmap; 1715 struct htt_rx_flush rx_flush; 1716 struct htt_rx_addba rx_addba; 1717 struct htt_rx_delba rx_delba; 1718 struct htt_security_indication security_indication; 1719 struct htt_rc_update rc_update; 1720 struct htt_rx_test rx_test; 1721 struct htt_pktlog_msg pktlog_msg; 1722 struct htt_rx_pn_ind rx_pn_ind; 1723 struct htt_rx_offload_ind rx_offload_ind; 1724 struct htt_rx_in_ord_ind rx_in_ord_ind; 1725 struct htt_tx_fetch_ind tx_fetch_ind; 1726 struct htt_tx_fetch_confirm tx_fetch_confirm; 1727 struct htt_tx_mode_switch_ind tx_mode_switch_ind; 1728 struct htt_channel_change chan_change; 1729 struct htt_peer_tx_stats peer_tx_stats; 1730 } __packed; 1731 } __packed; 1732 1733 /*** host side structures follow ***/ 1734 1735 struct htt_tx_done { 1736 u16 msdu_id; 1737 u16 status; 1738 u8 ack_rssi; 1739 }; 1740 1741 enum htt_tx_compl_state { 1742 HTT_TX_COMPL_STATE_NONE, 1743 HTT_TX_COMPL_STATE_ACK, 1744 HTT_TX_COMPL_STATE_NOACK, 1745 HTT_TX_COMPL_STATE_DISCARD, 1746 }; 1747 1748 struct htt_peer_map_event { 1749 u8 vdev_id; 1750 u16 peer_id; 1751 u8 addr[ETH_ALEN]; 1752 }; 1753 1754 struct htt_peer_unmap_event { 1755 u16 peer_id; 1756 }; 1757 1758 struct ath10k_htt_txbuf_32 { 1759 struct htt_data_tx_desc_frag frags[2]; 1760 struct ath10k_htc_hdr htc_hdr; 1761 struct htt_cmd_hdr cmd_hdr; 1762 struct htt_data_tx_desc cmd_tx; 1763 } __packed __aligned(4); 1764 1765 struct ath10k_htt_txbuf_64 { 1766 struct htt_data_tx_desc_frag frags[2]; 1767 struct ath10k_htc_hdr htc_hdr; 1768 struct htt_cmd_hdr cmd_hdr; 1769 struct htt_data_tx_desc_64 cmd_tx; 1770 } __packed __aligned(4); 1771 1772 struct ath10k_htt { 1773 struct ath10k *ar; 1774 enum ath10k_htc_ep_id eid; 1775 1776 struct sk_buff_head rx_indication_head; 1777 1778 u8 target_version_major; 1779 u8 target_version_minor; 1780 struct completion target_version_received; 1781 u8 max_num_amsdu; 1782 u8 max_num_ampdu; 1783 1784 const enum htt_t2h_msg_type *t2h_msg_types; 1785 u32 t2h_msg_types_max; 1786 1787 struct { 1788 /* 1789 * Ring of network buffer objects - This ring is 1790 * used exclusively by the host SW. This ring 1791 * mirrors the dev_addrs_ring that is shared 1792 * between the host SW and the MAC HW. The host SW 1793 * uses this netbufs ring to locate the network 1794 * buffer objects whose data buffers the HW has 1795 * filled. 1796 */ 1797 struct sk_buff **netbufs_ring; 1798 1799 /* This is used only with firmware supporting IN_ORD_IND. 1800 * 1801 * With Full Rx Reorder the HTT Rx Ring is more of a temporary 1802 * buffer ring from which buffer addresses are copied by the 1803 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND 1804 * pointing to specific (re-ordered) buffers. 1805 * 1806 * FIXME: With kernel generic hashing functions there's a lot 1807 * of hash collisions for sk_buffs. 1808 */ 1809 bool in_ord_rx; 1810 DECLARE_HASHTABLE(skb_table, 4); 1811 1812 /* 1813 * Ring of buffer addresses - 1814 * This ring holds the "physical" device address of the 1815 * rx buffers the host SW provides for the MAC HW to 1816 * fill. 1817 */ 1818 union { 1819 __le64 *paddrs_ring_64; 1820 __le32 *paddrs_ring_32; 1821 }; 1822 1823 /* 1824 * Base address of ring, as a "physical" device address 1825 * rather than a CPU address. 1826 */ 1827 dma_addr_t base_paddr; 1828 1829 /* how many elems in the ring (power of 2) */ 1830 int size; 1831 1832 /* size - 1 */ 1833 unsigned int size_mask; 1834 1835 /* how many rx buffers to keep in the ring */ 1836 int fill_level; 1837 1838 /* how many rx buffers (full+empty) are in the ring */ 1839 int fill_cnt; 1840 1841 /* 1842 * alloc_idx - where HTT SW has deposited empty buffers 1843 * This is allocated in consistent mem, so that the FW can 1844 * read this variable, and program the HW's FW_IDX reg with 1845 * the value of this shadow register. 1846 */ 1847 struct { 1848 __le32 *vaddr; 1849 dma_addr_t paddr; 1850 } alloc_idx; 1851 1852 /* where HTT SW has processed bufs filled by rx MAC DMA */ 1853 struct { 1854 unsigned int msdu_payld; 1855 } sw_rd_idx; 1856 1857 /* 1858 * refill_retry_timer - timer triggered when the ring is 1859 * not refilled to the level expected 1860 */ 1861 struct timer_list refill_retry_timer; 1862 1863 /* Protects access to all rx ring buffer state variables */ 1864 spinlock_t lock; 1865 } rx_ring; 1866 1867 unsigned int prefetch_len; 1868 1869 /* Protects access to pending_tx, num_pending_tx */ 1870 spinlock_t tx_lock; 1871 int max_num_pending_tx; 1872 int num_pending_tx; 1873 int num_pending_mgmt_tx; 1874 struct idr pending_tx; 1875 wait_queue_head_t empty_tx_wq; 1876 1877 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ 1878 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done); 1879 1880 /* set if host-fw communication goes haywire 1881 * used to avoid further failures 1882 */ 1883 bool rx_confused; 1884 atomic_t num_mpdus_ready; 1885 1886 /* This is used to group tx/rx completions separately and process them 1887 * in batches to reduce cache stalls 1888 */ 1889 struct sk_buff_head rx_msdus_q; 1890 struct sk_buff_head rx_in_ord_compl_q; 1891 struct sk_buff_head tx_fetch_ind_q; 1892 1893 /* rx_status template */ 1894 struct ieee80211_rx_status rx_status; 1895 1896 struct { 1897 dma_addr_t paddr; 1898 union { 1899 struct htt_msdu_ext_desc *vaddr_desc_32; 1900 struct htt_msdu_ext_desc_64 *vaddr_desc_64; 1901 }; 1902 size_t size; 1903 } frag_desc; 1904 1905 struct { 1906 dma_addr_t paddr; 1907 union { 1908 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32; 1909 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64; 1910 }; 1911 size_t size; 1912 } txbuf; 1913 1914 struct { 1915 bool enabled; 1916 struct htt_q_state *vaddr; 1917 dma_addr_t paddr; 1918 u16 num_push_allowed; 1919 u16 num_peers; 1920 u16 num_tids; 1921 enum htt_tx_mode_switch_mode mode; 1922 enum htt_q_depth_type type; 1923 } tx_q_state; 1924 1925 bool tx_mem_allocated; 1926 const struct ath10k_htt_tx_ops *tx_ops; 1927 const struct ath10k_htt_rx_ops *rx_ops; 1928 bool disable_tx_comp; 1929 bool bundle_tx; 1930 struct sk_buff_head tx_req_head; 1931 struct sk_buff_head tx_complete_head; 1932 }; 1933 1934 struct ath10k_htt_tx_ops { 1935 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt); 1936 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt); 1937 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt); 1938 void (*htt_free_frag_desc)(struct ath10k_htt *htt); 1939 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode, 1940 struct sk_buff *msdu); 1941 int (*htt_alloc_txbuff)(struct ath10k_htt *htt); 1942 void (*htt_free_txbuff)(struct ath10k_htt *htt); 1943 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt, 1944 u8 max_subfrms_ampdu, 1945 u8 max_subfrms_amsdu); 1946 void (*htt_flush_tx)(struct ath10k_htt *htt); 1947 }; 1948 ath10k_htt_send_rx_ring_cfg(struct ath10k_htt * htt)1949 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt) 1950 { 1951 if (!htt->tx_ops->htt_send_rx_ring_cfg) 1952 return -EOPNOTSUPP; 1953 1954 return htt->tx_ops->htt_send_rx_ring_cfg(htt); 1955 } 1956 ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt * htt)1957 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt) 1958 { 1959 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg) 1960 return -EOPNOTSUPP; 1961 1962 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt); 1963 } 1964 ath10k_htt_alloc_frag_desc(struct ath10k_htt * htt)1965 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt) 1966 { 1967 if (!htt->tx_ops->htt_alloc_frag_desc) 1968 return -EOPNOTSUPP; 1969 1970 return htt->tx_ops->htt_alloc_frag_desc(htt); 1971 } 1972 ath10k_htt_free_frag_desc(struct ath10k_htt * htt)1973 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt) 1974 { 1975 if (htt->tx_ops->htt_free_frag_desc) 1976 htt->tx_ops->htt_free_frag_desc(htt); 1977 } 1978 ath10k_htt_tx(struct ath10k_htt * htt,enum ath10k_hw_txrx_mode txmode,struct sk_buff * msdu)1979 static inline int ath10k_htt_tx(struct ath10k_htt *htt, 1980 enum ath10k_hw_txrx_mode txmode, 1981 struct sk_buff *msdu) 1982 { 1983 return htt->tx_ops->htt_tx(htt, txmode, msdu); 1984 } 1985 ath10k_htt_flush_tx(struct ath10k_htt * htt)1986 static inline void ath10k_htt_flush_tx(struct ath10k_htt *htt) 1987 { 1988 if (htt->tx_ops->htt_flush_tx) 1989 htt->tx_ops->htt_flush_tx(htt); 1990 } 1991 ath10k_htt_alloc_txbuff(struct ath10k_htt * htt)1992 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt) 1993 { 1994 if (!htt->tx_ops->htt_alloc_txbuff) 1995 return -EOPNOTSUPP; 1996 1997 return htt->tx_ops->htt_alloc_txbuff(htt); 1998 } 1999 ath10k_htt_free_txbuff(struct ath10k_htt * htt)2000 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt) 2001 { 2002 if (htt->tx_ops->htt_free_txbuff) 2003 htt->tx_ops->htt_free_txbuff(htt); 2004 } 2005 ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt * htt,u8 max_subfrms_ampdu,u8 max_subfrms_amsdu)2006 static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 2007 u8 max_subfrms_ampdu, 2008 u8 max_subfrms_amsdu) 2009 2010 { 2011 if (!htt->tx_ops->htt_h2t_aggr_cfg_msg) 2012 return -EOPNOTSUPP; 2013 2014 return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt, 2015 max_subfrms_ampdu, 2016 max_subfrms_amsdu); 2017 } 2018 2019 struct ath10k_htt_rx_ops { 2020 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt); 2021 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr); 2022 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr, 2023 int idx); 2024 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt); 2025 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx); 2026 bool (*htt_rx_proc_rx_frag_ind)(struct ath10k_htt *htt, 2027 struct htt_rx_fragment_indication *rx, 2028 struct sk_buff *skb); 2029 }; 2030 ath10k_htt_get_rx_ring_size(struct ath10k_htt * htt)2031 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt) 2032 { 2033 if (!htt->rx_ops->htt_get_rx_ring_size) 2034 return 0; 2035 2036 return htt->rx_ops->htt_get_rx_ring_size(htt); 2037 } 2038 ath10k_htt_config_paddrs_ring(struct ath10k_htt * htt,void * vaddr)2039 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt, 2040 void *vaddr) 2041 { 2042 if (htt->rx_ops->htt_config_paddrs_ring) 2043 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr); 2044 } 2045 ath10k_htt_set_paddrs_ring(struct ath10k_htt * htt,dma_addr_t paddr,int idx)2046 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt, 2047 dma_addr_t paddr, 2048 int idx) 2049 { 2050 if (htt->rx_ops->htt_set_paddrs_ring) 2051 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx); 2052 } 2053 ath10k_htt_get_vaddr_ring(struct ath10k_htt * htt)2054 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt) 2055 { 2056 if (!htt->rx_ops->htt_get_vaddr_ring) 2057 return NULL; 2058 2059 return htt->rx_ops->htt_get_vaddr_ring(htt); 2060 } 2061 ath10k_htt_reset_paddrs_ring(struct ath10k_htt * htt,int idx)2062 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx) 2063 { 2064 if (htt->rx_ops->htt_reset_paddrs_ring) 2065 htt->rx_ops->htt_reset_paddrs_ring(htt, idx); 2066 } 2067 ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt * htt,struct htt_rx_fragment_indication * rx,struct sk_buff * skb)2068 static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt, 2069 struct htt_rx_fragment_indication *rx, 2070 struct sk_buff *skb) 2071 { 2072 if (!htt->rx_ops->htt_rx_proc_rx_frag_ind) 2073 return true; 2074 2075 return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb); 2076 } 2077 2078 /* the driver strongly assumes that the rx header status be 64 bytes long, 2079 * so all possible rx_desc structures must respect this assumption. 2080 */ 2081 #define RX_HTT_HDR_STATUS_LEN 64 2082 2083 /* The rx descriptor structure layout is programmed via rx ring setup 2084 * so that FW knows how to transfer the rx descriptor to the host. 2085 * Unfortunately, though, QCA6174's firmware doesn't currently behave correctly 2086 * when modifying the structure layout of the rx descriptor beyond what it expects 2087 * (even if it correctly programmed during the rx ring setup). 2088 * Therefore we must keep two different memory layouts, abstract the rx descriptor 2089 * representation and use ath10k_rx_desc_ops 2090 * for correctly accessing rx descriptor data. 2091 */ 2092 2093 /* base struct used for abstracting the rx descriptor representation */ 2094 struct htt_rx_desc { 2095 union { 2096 /* This field is filled on the host using the msdu buffer 2097 * from htt_rx_indication 2098 */ 2099 struct fw_rx_desc_base fw_desc; 2100 u32 pad; 2101 } __packed; 2102 } __packed; 2103 2104 /* rx descriptor for wcn3990 and possibly extensible for newer cards 2105 * Buffers like this are placed on the rx ring. 2106 */ 2107 struct htt_rx_desc_v2 { 2108 struct htt_rx_desc base; 2109 struct { 2110 struct rx_attention attention; 2111 struct rx_frag_info frag_info; 2112 struct rx_mpdu_start mpdu_start; 2113 struct rx_msdu_start msdu_start; 2114 struct rx_msdu_end msdu_end; 2115 struct rx_mpdu_end mpdu_end; 2116 struct rx_ppdu_start ppdu_start; 2117 struct rx_ppdu_end ppdu_end; 2118 } __packed; 2119 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 2120 u8 msdu_payload[]; 2121 }; 2122 2123 /* QCA6174, QCA988x, QCA99x0 dedicated rx descriptor to make sure their firmware 2124 * works correctly. We keep a single rx descriptor for all these three 2125 * families of cards because from tests it seems to be the most stable solution, 2126 * e.g. having a rx descriptor only for QCA6174 seldom caused firmware crashes 2127 * during some tests. 2128 * Buffers like this are placed on the rx ring. 2129 */ 2130 struct htt_rx_desc_v1 { 2131 struct htt_rx_desc base; 2132 struct { 2133 struct rx_attention attention; 2134 struct rx_frag_info_v1 frag_info; 2135 struct rx_mpdu_start mpdu_start; 2136 struct rx_msdu_start_v1 msdu_start; 2137 struct rx_msdu_end_v1 msdu_end; 2138 struct rx_mpdu_end mpdu_end; 2139 struct rx_ppdu_start ppdu_start; 2140 struct rx_ppdu_end_v1 ppdu_end; 2141 } __packed; 2142 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN]; 2143 u8 msdu_payload[]; 2144 }; 2145 2146 /* rx_desc abstraction */ 2147 struct ath10k_htt_rx_desc_ops { 2148 /* These fields are mandatory, they must be specified in any instance */ 2149 2150 /* sizeof() of the rx_desc structure used by this hw */ 2151 size_t rx_desc_size; 2152 2153 /* offset of msdu_payload inside the rx_desc structure used by this hw */ 2154 size_t rx_desc_msdu_payload_offset; 2155 2156 /* These fields are options. 2157 * When a field is not provided the default implementation gets used 2158 * (see the ath10k_rx_desc_* operations below for more info about the defaults) 2159 */ 2160 bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd); 2161 int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd); 2162 2163 /* Safely cast from a void* buffer containing an rx descriptor 2164 * to the proper rx_desc structure 2165 */ 2166 struct htt_rx_desc *(*rx_desc_from_raw_buffer)(void *buff); 2167 2168 void (*rx_desc_get_offsets)(struct htt_rx_ring_rx_desc_offsets *offs); 2169 struct rx_attention *(*rx_desc_get_attention)(struct htt_rx_desc *rxd); 2170 struct rx_frag_info_common *(*rx_desc_get_frag_info)(struct htt_rx_desc *rxd); 2171 struct rx_mpdu_start *(*rx_desc_get_mpdu_start)(struct htt_rx_desc *rxd); 2172 struct rx_mpdu_end *(*rx_desc_get_mpdu_end)(struct htt_rx_desc *rxd); 2173 struct rx_msdu_start_common *(*rx_desc_get_msdu_start)(struct htt_rx_desc *rxd); 2174 struct rx_msdu_end_common *(*rx_desc_get_msdu_end)(struct htt_rx_desc *rxd); 2175 struct rx_ppdu_start *(*rx_desc_get_ppdu_start)(struct htt_rx_desc *rxd); 2176 struct rx_ppdu_end_common *(*rx_desc_get_ppdu_end)(struct htt_rx_desc *rxd); 2177 u8 *(*rx_desc_get_rx_hdr_status)(struct htt_rx_desc *rxd); 2178 u8 *(*rx_desc_get_msdu_payload)(struct htt_rx_desc *rxd); 2179 }; 2180 2181 extern const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops; 2182 extern const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops; 2183 extern const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops; 2184 2185 static inline int ath10k_htt_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2186 ath10k_htt_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2187 { 2188 if (hw->rx_desc_ops->rx_desc_get_l3_pad_bytes) 2189 return hw->rx_desc_ops->rx_desc_get_l3_pad_bytes(rxd); 2190 return 0; 2191 } 2192 2193 static inline bool ath10k_htt_rx_desc_msdu_limit_error(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2194 ath10k_htt_rx_desc_msdu_limit_error(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2195 { 2196 if (hw->rx_desc_ops->rx_desc_get_msdu_limit_error) 2197 return hw->rx_desc_ops->rx_desc_get_msdu_limit_error(rxd); 2198 return false; 2199 } 2200 2201 /* The default implementation of all these getters is using the old rx_desc, 2202 * so that it is easier to define the ath10k_htt_rx_desc_ops instances. 2203 * But probably, if new wireless cards must be supported, it would be better 2204 * to switch the default implementation to the new rx_desc, since this would 2205 * make the extension easier . 2206 */ 2207 static inline struct htt_rx_desc * ath10k_htt_rx_desc_from_raw_buffer(struct ath10k_hw_params * hw,void * buff)2208 ath10k_htt_rx_desc_from_raw_buffer(struct ath10k_hw_params *hw, void *buff) 2209 { 2210 if (hw->rx_desc_ops->rx_desc_from_raw_buffer) 2211 return hw->rx_desc_ops->rx_desc_from_raw_buffer(buff); 2212 return &((struct htt_rx_desc_v1 *)buff)->base; 2213 } 2214 2215 static inline void ath10k_htt_rx_desc_get_offsets(struct ath10k_hw_params * hw,struct htt_rx_ring_rx_desc_offsets * off)2216 ath10k_htt_rx_desc_get_offsets(struct ath10k_hw_params *hw, 2217 struct htt_rx_ring_rx_desc_offsets *off) 2218 { 2219 if (hw->rx_desc_ops->rx_desc_get_offsets) { 2220 hw->rx_desc_ops->rx_desc_get_offsets(off); 2221 } else { 2222 #define desc_offset(x) (offsetof(struct htt_rx_desc_v1, x) / 4) 2223 off->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 2224 off->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 2225 off->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 2226 off->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 2227 off->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 2228 off->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 2229 off->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 2230 off->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 2231 off->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 2232 off->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 2233 #undef desc_offset 2234 } 2235 } 2236 2237 static inline struct rx_attention * ath10k_htt_rx_desc_get_attention(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2238 ath10k_htt_rx_desc_get_attention(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2239 { 2240 struct htt_rx_desc_v1 *rx_desc; 2241 2242 if (hw->rx_desc_ops->rx_desc_get_attention) 2243 return hw->rx_desc_ops->rx_desc_get_attention(rxd); 2244 2245 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2246 return &rx_desc->attention; 2247 } 2248 2249 static inline struct rx_frag_info_common * ath10k_htt_rx_desc_get_frag_info(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2250 ath10k_htt_rx_desc_get_frag_info(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2251 { 2252 struct htt_rx_desc_v1 *rx_desc; 2253 2254 if (hw->rx_desc_ops->rx_desc_get_frag_info) 2255 return hw->rx_desc_ops->rx_desc_get_frag_info(rxd); 2256 2257 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2258 return &rx_desc->frag_info.common; 2259 } 2260 2261 static inline struct rx_mpdu_start * ath10k_htt_rx_desc_get_mpdu_start(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2262 ath10k_htt_rx_desc_get_mpdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2263 { 2264 struct htt_rx_desc_v1 *rx_desc; 2265 2266 if (hw->rx_desc_ops->rx_desc_get_mpdu_start) 2267 return hw->rx_desc_ops->rx_desc_get_mpdu_start(rxd); 2268 2269 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2270 return &rx_desc->mpdu_start; 2271 } 2272 2273 static inline struct rx_mpdu_end * ath10k_htt_rx_desc_get_mpdu_end(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2274 ath10k_htt_rx_desc_get_mpdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2275 { 2276 struct htt_rx_desc_v1 *rx_desc; 2277 2278 if (hw->rx_desc_ops->rx_desc_get_mpdu_end) 2279 return hw->rx_desc_ops->rx_desc_get_mpdu_end(rxd); 2280 2281 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2282 return &rx_desc->mpdu_end; 2283 } 2284 2285 static inline struct rx_msdu_start_common * ath10k_htt_rx_desc_get_msdu_start(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2286 ath10k_htt_rx_desc_get_msdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2287 { 2288 struct htt_rx_desc_v1 *rx_desc; 2289 2290 if (hw->rx_desc_ops->rx_desc_get_msdu_start) 2291 return hw->rx_desc_ops->rx_desc_get_msdu_start(rxd); 2292 2293 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2294 return &rx_desc->msdu_start.common; 2295 } 2296 2297 static inline struct rx_msdu_end_common * ath10k_htt_rx_desc_get_msdu_end(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2298 ath10k_htt_rx_desc_get_msdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2299 { 2300 struct htt_rx_desc_v1 *rx_desc; 2301 2302 if (hw->rx_desc_ops->rx_desc_get_msdu_end) 2303 return hw->rx_desc_ops->rx_desc_get_msdu_end(rxd); 2304 2305 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2306 return &rx_desc->msdu_end.common; 2307 } 2308 2309 static inline struct rx_ppdu_start * ath10k_htt_rx_desc_get_ppdu_start(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2310 ath10k_htt_rx_desc_get_ppdu_start(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2311 { 2312 struct htt_rx_desc_v1 *rx_desc; 2313 2314 if (hw->rx_desc_ops->rx_desc_get_ppdu_start) 2315 return hw->rx_desc_ops->rx_desc_get_ppdu_start(rxd); 2316 2317 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2318 return &rx_desc->ppdu_start; 2319 } 2320 2321 static inline struct rx_ppdu_end_common * ath10k_htt_rx_desc_get_ppdu_end(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2322 ath10k_htt_rx_desc_get_ppdu_end(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2323 { 2324 struct htt_rx_desc_v1 *rx_desc; 2325 2326 if (hw->rx_desc_ops->rx_desc_get_ppdu_end) 2327 return hw->rx_desc_ops->rx_desc_get_ppdu_end(rxd); 2328 2329 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2330 return &rx_desc->ppdu_end.common; 2331 } 2332 2333 static inline u8 * ath10k_htt_rx_desc_get_rx_hdr_status(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2334 ath10k_htt_rx_desc_get_rx_hdr_status(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2335 { 2336 struct htt_rx_desc_v1 *rx_desc; 2337 2338 if (hw->rx_desc_ops->rx_desc_get_rx_hdr_status) 2339 return hw->rx_desc_ops->rx_desc_get_rx_hdr_status(rxd); 2340 2341 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2342 return rx_desc->rx_hdr_status; 2343 } 2344 2345 static inline u8 * ath10k_htt_rx_desc_get_msdu_payload(struct ath10k_hw_params * hw,struct htt_rx_desc * rxd)2346 ath10k_htt_rx_desc_get_msdu_payload(struct ath10k_hw_params *hw, struct htt_rx_desc *rxd) 2347 { 2348 struct htt_rx_desc_v1 *rx_desc; 2349 2350 if (hw->rx_desc_ops->rx_desc_get_msdu_payload) 2351 return hw->rx_desc_ops->rx_desc_get_msdu_payload(rxd); 2352 2353 rx_desc = container_of(rxd, struct htt_rx_desc_v1, base); 2354 return rx_desc->msdu_payload; 2355 } 2356 2357 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff 2358 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0 2359 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000 2360 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12 2361 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000 2362 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13 2363 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00010000 2364 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 16 2365 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000 2366 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17 2367 2368 struct htt_rx_desc_base_hl { 2369 __le32 info; /* HTT_RX_DESC_HL_INFO_ */ 2370 }; 2371 2372 struct htt_rx_chan_info { 2373 __le16 primary_chan_center_freq_mhz; 2374 __le16 contig_chan1_center_freq_mhz; 2375 __le16 contig_chan2_center_freq_mhz; 2376 u8 phy_mode; 2377 u8 reserved; 2378 } __packed; 2379 2380 #define HTT_RX_DESC_ALIGN 8 2381 2382 #define HTT_MAC_ADDR_LEN 6 2383 2384 /* 2385 * FIX THIS 2386 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, 2387 * rounded up to a cache line size. 2388 */ 2389 #define HTT_RX_BUF_SIZE 2048 2390 2391 /* The HTT_RX_MSDU_SIZE can't be statically computed anymore, 2392 * because it depends on the underlying device rx_desc representation 2393 */ ath10k_htt_rx_msdu_size(struct ath10k_hw_params * hw)2394 static inline int ath10k_htt_rx_msdu_size(struct ath10k_hw_params *hw) 2395 { 2396 return HTT_RX_BUF_SIZE - (int)hw->rx_desc_ops->rx_desc_size; 2397 } 2398 2399 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle 2400 * aggregated traffic more nicely. 2401 */ 2402 #define ATH10K_HTT_MAX_NUM_REFILL 100 2403 2404 /* 2405 * DMA_MAP expects the buffer to be an integral number of cache lines. 2406 * Rather than checking the actual cache line size, this code makes a 2407 * conservative estimate of what the cache line size could be. 2408 */ 2409 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ 2410 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1) 2411 2412 /* These values are default in most firmware revisions and apparently are a 2413 * sweet spot performance wise. 2414 */ 2415 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 2416 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 2417 2418 int ath10k_htt_connect(struct ath10k_htt *htt); 2419 int ath10k_htt_init(struct ath10k *ar); 2420 int ath10k_htt_setup(struct ath10k_htt *htt); 2421 2422 int ath10k_htt_tx_start(struct ath10k_htt *htt); 2423 void ath10k_htt_tx_stop(struct ath10k_htt *htt); 2424 void ath10k_htt_tx_destroy(struct ath10k_htt *htt); 2425 void ath10k_htt_tx_free(struct ath10k_htt *htt); 2426 2427 int ath10k_htt_rx_alloc(struct ath10k_htt *htt); 2428 int ath10k_htt_rx_ring_refill(struct ath10k *ar); 2429 void ath10k_htt_rx_free(struct ath10k_htt *htt); 2430 2431 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2432 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2433 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); 2434 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); 2435 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, 2436 u64 cookie); 2437 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb); 2438 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 2439 __le32 token, 2440 __le16 fetch_seq_num, 2441 struct htt_tx_fetch_record *records, 2442 size_t num_records); 2443 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar); 2444 2445 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 2446 struct ieee80211_txq *txq); 2447 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 2448 struct ieee80211_txq *txq); 2449 void ath10k_htt_tx_txq_sync(struct ath10k *ar); 2450 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt); 2451 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt); 2452 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt); 2453 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 2454 bool is_presp); 2455 2456 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb); 2457 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id); 2458 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu); 2459 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar, 2460 struct sk_buff *skb); 2461 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget); 2462 int ath10k_htt_rx_hl_indication(struct ath10k *ar, int budget); 2463 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt); 2464 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt); 2465 #endif 2466