1 /* 2 * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_API_MON_H_ 21 #define _HAL_API_MON_H_ 22 23 #include "qdf_types.h" 24 #include "hal_internal.h" 25 #include "hal_rx.h" 26 #include "hal_hw_headers.h" 27 #include <target_type.h> 28 29 #define HAL_RX_PHY_DATA_RADAR 0x01 30 #define HAL_SU_MU_CODING_LDPC 0x01 31 32 #define HAL_RX_FCS_LEN (4) 33 #define KEY_EXTIV 0x20 34 35 #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1) 36 #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask)) 37 38 #define HAL_RX_TLV32_HDR_SIZE 4 39 40 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \ 41 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 42 HAL_RX_USER_TLV32_TYPE_MASK) >> \ 43 HAL_RX_USER_TLV32_TYPE_LSB) 44 45 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \ 46 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 47 HAL_RX_USER_TLV32_LEN_MASK) >> \ 48 HAL_RX_USER_TLV32_LEN_LSB) 49 50 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \ 51 ((*((uint32_t *)(rx_status_tlv_ptr)) & \ 52 HAL_RX_USER_TLV32_USERID_MASK) >> \ 53 HAL_RX_USER_TLV32_USERID_LSB) 54 55 #define HAL_RX_TLV64_HDR_SIZE 8 56 57 #ifdef CONFIG_4_BYTES_TLV_TAG 58 #define HAL_RX_TLV_HDR_SIZE HAL_RX_TLV32_HDR_SIZE 59 #else 60 #define HAL_RX_TLV_HDR_SIZE HAL_RX_TLV64_HDR_SIZE 61 #endif 62 63 #define HAL_TLV_STATUS_PPDU_NOT_DONE 0 64 #define HAL_TLV_STATUS_PPDU_DONE 1 65 #define HAL_TLV_STATUS_BUF_DONE 2 66 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3 67 #define HAL_TLV_STATUS_PPDU_START 4 68 #define HAL_TLV_STATUS_HEADER 5 69 #define HAL_TLV_STATUS_MPDU_END 6 70 #define HAL_TLV_STATUS_MSDU_START 7 71 #define HAL_TLV_STATUS_MSDU_END 8 72 #define HAL_TLV_STATUS_MON_BUF_ADDR 9 73 #define HAL_TLV_STATUS_MPDU_START 10 74 #define HAL_TLV_STATUS_MON_DROP 11 75 76 #define HAL_MAX_UL_MU_USERS 37 77 78 #define HAL_RX_PKT_TYPE_11A 0 79 #define HAL_RX_PKT_TYPE_11B 1 80 #define HAL_RX_PKT_TYPE_11N 2 81 #define HAL_RX_PKT_TYPE_11AC 3 82 #define HAL_RX_PKT_TYPE_11AX 4 83 #ifdef WLAN_FEATURE_11BE 84 #define HAL_RX_PKT_TYPE_11BE 6 85 #endif 86 87 #define HAL_RX_RECEPTION_TYPE_SU 0 88 #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1 89 #define HAL_RX_RECEPTION_TYPE_OFDMA 2 90 #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3 91 92 /* Multiply rate by 2 to avoid float point 93 * and get rate in units of 500kbps 94 */ 95 #define HAL_11B_RATE_0MCS 11*2 96 #define HAL_11B_RATE_1MCS 5.5*2 97 #define HAL_11B_RATE_2MCS 2*2 98 #define HAL_11B_RATE_3MCS 1*2 99 #define HAL_11B_RATE_4MCS 11*2 100 #define HAL_11B_RATE_5MCS 5.5*2 101 #define HAL_11B_RATE_6MCS 2*2 102 103 #define HAL_11A_RATE_0MCS 48*2 104 #define HAL_11A_RATE_1MCS 24*2 105 #define HAL_11A_RATE_2MCS 12*2 106 #define HAL_11A_RATE_3MCS 6*2 107 #define HAL_11A_RATE_4MCS 54*2 108 #define HAL_11A_RATE_5MCS 36*2 109 #define HAL_11A_RATE_6MCS 18*2 110 #define HAL_11A_RATE_7MCS 9*2 111 112 #define HAL_LEGACY_MCS0 0 113 #define HAL_LEGACY_MCS1 1 114 #define HAL_LEGACY_MCS2 2 115 #define HAL_LEGACY_MCS3 3 116 #define HAL_LEGACY_MCS4 4 117 #define HAL_LEGACY_MCS5 5 118 #define HAL_LEGACY_MCS6 6 119 #define HAL_LEGACY_MCS7 7 120 121 #define HE_GI_0_8 0 122 #define HE_GI_0_4 1 123 #define HE_GI_1_6 2 124 #define HE_GI_3_2 3 125 126 #define HE_GI_RADIOTAP_0_8 0 127 #define HE_GI_RADIOTAP_1_6 1 128 #define HE_GI_RADIOTAP_3_2 2 129 #define HE_GI_RADIOTAP_RESERVED 3 130 131 #define HE_LTF_RADIOTAP_UNKNOWN 0 132 #define HE_LTF_RADIOTAP_1_X 1 133 #define HE_LTF_RADIOTAP_2_X 2 134 #define HE_LTF_RADIOTAP_4_X 3 135 136 #define HT_SGI_PRESENT 0x80 137 138 #define HE_LTF_1_X 0 139 #define HE_LTF_2_X 1 140 #define HE_LTF_4_X 2 141 #define HE_LTF_UNKNOWN 3 142 #define VHT_SIG_SU_NSS_MASK 0x7 143 #define HT_SIG_SU_NSS_SHIFT 0x3 144 145 #define HAL_TID_INVALID 31 146 #define HAL_AST_IDX_INVALID 0xFFFF 147 148 #ifdef GET_MSDU_AGGREGATION 149 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 150 {\ 151 struct rx_msdu_end *rx_msdu_end;\ 152 bool first_msdu, last_msdu; \ 153 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 154 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\ 155 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\ 156 if (first_msdu && last_msdu)\ 157 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 158 else\ 159 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 160 } \ 161 162 #define HAL_RX_SET_MSDU_AGGREGATION((rs_mpdu), (rs_ppdu))\ 163 {\ 164 if (rs_mpdu->rs_flags & IEEE80211_AMSDU_FLAG)\ 165 rs_ppdu->rs_flags |= IEEE80211_AMSDU_FLAG;\ 166 } \ 167 168 #else 169 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 170 #define HAL_RX_SET_MSDU_AGGREGATION(rs_mpdu, rs_ppdu) 171 #endif 172 173 /* Max MPDUs per status buffer */ 174 #define HAL_RX_MAX_MPDU 256 175 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) 176 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 177 178 /* Max pilot count */ 179 #ifdef QCA_MONITOR_2_0_SUPPORT 180 #define HAL_RX_MAX_SU_EVM_COUNT 256 181 #else 182 #define HAL_RX_MAX_SU_EVM_COUNT 32 183 #endif 184 185 #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C 186 #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ 187 (((fc) & HAL_RX_FRAMECTRL_TYPE_MASK) >> 2) 188 #define HAL_RX_FRAME_CTRL_TYPE_MGMT 0x0 189 #define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1 190 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2 191 192 /** 193 * enum hal_dl_ul_flag - flag to indicate UL/DL 194 * @dl_ul_flag_is_dl_or_tdls: DL 195 * @dl_ul_flag_is_ul: UL 196 */ 197 enum hal_dl_ul_flag { 198 dl_ul_flag_is_dl_or_tdls, 199 dl_ul_flag_is_ul, 200 }; 201 202 /** 203 * enum hal_eht_ppdu_sig_cmn_type - PPDU type 204 * @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU 205 * @eht_ppdu_sig_su: SU PPDU 206 * @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU 207 */ 208 enum hal_eht_ppdu_sig_cmn_type { 209 eht_ppdu_sig_tb_or_dl_ofdma, 210 eht_ppdu_sig_su, 211 eht_ppdu_sig_dl_mu_mimo, 212 }; 213 214 /** 215 * struct hal_mon_packet_info - packet info 216 * @sw_cookie: 64-bit SW desc virtual address 217 * @dma_length: packet DMA length 218 * @msdu_continuation: msdu continulation in next buffer 219 * @truncated: packet is truncated 220 */ 221 struct hal_mon_packet_info { 222 uint64_t sw_cookie; 223 uint32_t dma_length : 16, 224 msdu_continuation : 1, 225 truncated : 1; 226 }; 227 228 /** 229 * struct hal_rx_mon_msdu_info - msdu info 230 * @first_buffer: first buffer of msdu 231 * @last_buffer: last buffer of msdu 232 * @first_mpdu: first MPDU 233 * @mpdu_length_err: MPDU length error 234 * @fcs_err: FCS error 235 * @first_msdu: first msdu 236 * @decap_type: decap type 237 * @last_msdu: last msdu 238 * @l3_header_padding: L3 padding header 239 * @stbc: stbc enabled 240 * @sgi: SGI value 241 * @reception_type: reception type 242 * @msdu_index: msdu index 243 * @buffer_len: buffer len 244 * @frag_len: frag len 245 * @msdu_len: msdu len 246 * @user_rssi: user rssi 247 */ 248 struct hal_rx_mon_msdu_info { 249 uint32_t first_buffer : 1, 250 last_buffer : 1, 251 first_mpdu : 1, 252 mpdu_length_err : 1, 253 fcs_err : 1, 254 first_msdu : 1, 255 decap_type : 3, 256 last_msdu : 1, 257 l3_header_padding : 3, 258 stbc : 1, 259 sgi : 2, 260 reception_type : 3, 261 msdu_index : 4; 262 uint16_t buffer_len : 12; 263 uint16_t frag_len : 12; 264 uint16_t msdu_len; 265 int16_t user_rssi; 266 }; 267 268 /** 269 * struct hal_rx_mon_mpdu_info - MPDU info 270 * @decap_type: decap_type 271 * @mpdu_length_err: MPDU length error 272 * @fcs_err: FCS error 273 * @overflow_err: overflow error 274 * @decrypt_err: decrypt error 275 * @mpdu_start_received: MPDU start received 276 * @full_pkt: Full MPDU received 277 * @first_rx_hdr_rcvd: First rx_hdr received 278 * @truncated: truncated MPDU 279 */ 280 struct hal_rx_mon_mpdu_info { 281 uint32_t decap_type : 8, 282 mpdu_length_err : 1, 283 fcs_err : 1, 284 overflow_err : 1, 285 decrypt_err : 1, 286 mpdu_start_received : 1, 287 full_pkt : 1, 288 first_rx_hdr_rcvd : 1, 289 truncated : 1; 290 }; 291 292 /** 293 * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info 294 * 295 * @ppdu_id: PHY ppdu id 296 * @status_ppdu_id: status PHY ppdu id 297 * @status_buf_count: number of status buffer count 298 * @rxdma_push_reason: rxdma push reason 299 * @rxdma_error_code: rxdma error code 300 * @msdu_count: msdu count 301 * @end_of_ppdu: end of ppdu 302 * @link_desc: msdu link descriptor address 303 * @status_buf: for a PPDU, status buffers can span across 304 * multiple buffers, status_buf points to first 305 * status buffer address of PPDU 306 * @drop_ppdu: flag to indicate current destination 307 * ring ppdu drop 308 */ 309 struct hal_rx_mon_desc_info { 310 uint16_t ppdu_id; 311 uint16_t status_ppdu_id; 312 uint8_t status_buf_count; 313 uint8_t rxdma_push_reason; 314 uint8_t rxdma_error_code; 315 uint8_t msdu_count; 316 uint8_t end_of_ppdu; 317 struct hal_buf_info link_desc; 318 struct hal_buf_info status_buf; 319 bool drop_ppdu; 320 }; 321 322 /** 323 * struct hal_rx_su_evm_info - SU evm info 324 * @number_of_symbols: number of symbols 325 * @nss_count: nss count 326 * @pilot_count: pilot count 327 * @pilot_evm: Array of pilot evm values 328 */ 329 struct hal_rx_su_evm_info { 330 uint32_t number_of_symbols; 331 uint8_t nss_count; 332 uint8_t pilot_count; 333 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT]; 334 }; 335 336 enum { 337 DP_PPDU_STATUS_START, 338 DP_PPDU_STATUS_DONE, 339 }; 340 341 /** 342 * struct hal_rx_ppdu_drop_cnt - PPDU drop count 343 * @ppdu_drop_cnt: PPDU drop count 344 * @mpdu_drop_cnt: MPDU drop count 345 * @end_of_ppdu_drop_cnt: End of PPDU drop count 346 * @tlv_drop_cnt: TLV drop count 347 */ 348 struct hal_rx_ppdu_drop_cnt { 349 uint8_t ppdu_drop_cnt; 350 uint16_t mpdu_drop_cnt; 351 uint8_t end_of_ppdu_drop_cnt; 352 uint16_t tlv_drop_cnt; 353 }; 354 355 static inline QDF_STATUS hal_rx_reo_ent_get_src_link_id(hal_soc_handle_t hal_soc_hdl,hal_rxdma_desc_t rx_desc,uint8_t * src_link_id)356 hal_rx_reo_ent_get_src_link_id(hal_soc_handle_t hal_soc_hdl, 357 hal_rxdma_desc_t rx_desc, 358 uint8_t *src_link_id) 359 { 360 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 361 362 if (!hal_soc || !hal_soc->ops) { 363 hal_err("hal handle is NULL"); 364 QDF_BUG(0); 365 return QDF_STATUS_E_INVAL; 366 } 367 368 if (hal_soc->ops->hal_rx_reo_ent_get_src_link_id) 369 return hal_soc->ops->hal_rx_reo_ent_get_src_link_id(rx_desc, 370 src_link_id); 371 372 return QDF_STATUS_E_INVAL; 373 } 374 375 /** 376 * hal_rx_reo_ent_buf_paddr_get() - Gets the physical address and cookie from 377 * the REO entrance ring element 378 * @hal_soc_hdl: HAL version of the SOC pointer 379 * @rx_desc: rx descriptor 380 * @buf_info: structure to return the buffer information 381 * @msdu_cnt: pointer to msdu count in MPDU 382 * 383 * CAUTION: This API calls a hal_soc ops, so be careful before calling this in 384 * per packet path 385 * 386 * Return: void 387 */ 388 static inline hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl,hal_rxdma_desc_t rx_desc,struct hal_buf_info * buf_info,uint32_t * msdu_cnt)389 void hal_rx_reo_ent_buf_paddr_get(hal_soc_handle_t hal_soc_hdl, 390 hal_rxdma_desc_t rx_desc, 391 struct hal_buf_info *buf_info, 392 uint32_t *msdu_cnt) 393 { 394 struct reo_entrance_ring *reo_ent_ring = 395 (struct reo_entrance_ring *)rx_desc; 396 struct buffer_addr_info *buf_addr_info; 397 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details; 398 uint32_t loop_cnt; 399 400 rx_mpdu_desc_info_details = 401 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 402 403 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details, 404 HAL_RX_MPDU_DESC_INFO, MSDU_COUNT); 405 406 loop_cnt = HAL_RX_GET(reo_ent_ring, HAL_REO_ENTRANCE_RING, 407 LOOPING_COUNT); 408 409 buf_addr_info = 410 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 411 412 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 413 buf_info); 414 buf_info->paddr = 415 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 416 ((uint64_t) 417 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 418 419 dp_nofl_debug("[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d", 420 __func__, __LINE__, reo_ent_ring, buf_addr_info, 421 (unsigned long long)buf_info->paddr, loop_cnt); 422 } 423 424 static inline hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl,void * rx_msdu_link_desc,struct hal_buf_info * buf_info)425 void hal_rx_mon_next_link_desc_get(hal_soc_handle_t hal_soc_hdl, 426 void *rx_msdu_link_desc, 427 struct hal_buf_info *buf_info) 428 { 429 struct rx_msdu_link *msdu_link = 430 (struct rx_msdu_link *)rx_msdu_link_desc; 431 struct buffer_addr_info *buf_addr_info; 432 433 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info; 434 435 hal_rx_buf_cookie_rbm_get(hal_soc_hdl, (uint32_t *)buf_addr_info, 436 buf_info); 437 438 buf_info->paddr = 439 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 440 ((uint64_t) 441 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 442 } 443 444 static inline HAL_RX_MON_DEST_GET_DESC(uint8_t * data)445 uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data) 446 { 447 return data; 448 } 449 450 static inline uint32_t hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl,void * hw_desc_addr)451 hal_rx_tlv_mpdu_len_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 452 { 453 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 454 455 if (!hal_soc || !hal_soc->ops) { 456 hal_err("hal handle is NULL"); 457 QDF_BUG(0); 458 return 0; 459 } 460 461 if (hal_soc->ops->hal_rx_tlv_mpdu_len_err_get) 462 return hal_soc->ops->hal_rx_tlv_mpdu_len_err_get(hw_desc_addr); 463 464 return 0; 465 } 466 467 static inline uint32_t hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl,void * hw_desc_addr)468 hal_rx_tlv_mpdu_fcs_err_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr) 469 { 470 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 471 472 if (!hal_soc || !hal_soc->ops) { 473 hal_err("hal handle is NULL"); 474 QDF_BUG(0); 475 return 0; 476 } 477 478 if (hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get) 479 return hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get(hw_desc_addr); 480 481 return 0; 482 } 483 484 #ifdef notyet 485 /* 486 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU 487 * start TLV of Hardware TLV descriptor 488 * @hw_desc_addr: Hardware descriptor address 489 * 490 * Return: bool: if TLV tag match 491 */ 492 static inline HAL_RX_HW_DESC_MPDU_VALID(void * hw_desc_addr)493 bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr) 494 { 495 struct rx_mon_pkt_tlvs *rx_desc = 496 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 497 uint32_t tlv_tag; 498 499 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 500 501 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 502 } 503 #endif 504 505 /* 506 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV user id in MPDU 507 * start TLV of Hardware TLV descriptor 508 * @hw_desc_addr: Hardware descriptor address 509 * 510 * Return: unit32_t: user id 511 */ 512 static inline uint32_t hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl,void * hw_desc_addr)513 hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl, 514 void *hw_desc_addr) 515 { 516 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 517 518 if (!hal_soc || !hal_soc->ops) { 519 hal_err("hal handle is NULL"); 520 QDF_BUG(0); 521 return 0; 522 } 523 524 if (hal_soc->ops->hal_rx_hw_desc_mpdu_user_id) 525 return hal_soc->ops->hal_rx_hw_desc_mpdu_user_id(hw_desc_addr); 526 527 return 0; 528 } 529 530 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */ 531 532 /** 533 * hal_rx_mon_msdu_link_desc_set() - Retrieves MSDU Link Descriptor to WBM 534 * @hal_soc_hdl: HAL version of the SOC pointer 535 * @src_srng_desc: void pointer to the WBM Release Ring descriptor 536 * @buf_addr_info: void pointer to the buffer_addr_info 537 * 538 * Return: void 539 */ 540 static inline hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,void * src_srng_desc,hal_buff_addrinfo_t buf_addr_info)541 void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl, 542 void *src_srng_desc, 543 hal_buff_addrinfo_t buf_addr_info) 544 { 545 struct buffer_addr_info *wbm_srng_buffer_addr_info = 546 (struct buffer_addr_info *)src_srng_desc; 547 uint64_t paddr; 548 struct buffer_addr_info *p_buffer_addr_info = 549 (struct buffer_addr_info *)buf_addr_info; 550 551 paddr = 552 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | 553 ((uint64_t) 554 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32)); 555 556 dp_nofl_debug("[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx", 557 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr, 558 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie); 559 560 /* Structure copy !!! */ 561 *wbm_srng_buffer_addr_info = 562 *((struct buffer_addr_info *)buf_addr_info); 563 } 564 565 /** 566 * hal_get_rx_msdu_link_desc_size() - Get msdu link descriptor size 567 * 568 * Return: size of rx_msdu_link 569 */ 570 static inline hal_get_rx_msdu_link_desc_size(void)571 uint32_t hal_get_rx_msdu_link_desc_size(void) 572 { 573 return sizeof(struct rx_msdu_link); 574 } 575 576 enum { 577 HAL_PKT_TYPE_OFDM = 0, 578 HAL_PKT_TYPE_CCK, 579 HAL_PKT_TYPE_HT, 580 HAL_PKT_TYPE_VHT, 581 HAL_PKT_TYPE_HE, 582 }; 583 584 enum { 585 HAL_SGI_0_8_US, 586 HAL_SGI_0_4_US, 587 HAL_SGI_1_6_US, 588 HAL_SGI_3_2_US, 589 }; 590 591 #ifdef WLAN_FEATURE_11BE 592 enum { 593 HAL_FULL_RX_BW_20, 594 HAL_FULL_RX_BW_40, 595 HAL_FULL_RX_BW_80, 596 HAL_FULL_RX_BW_160, 597 HAL_FULL_RX_BW_320, 598 }; 599 #else 600 enum { 601 HAL_FULL_RX_BW_20, 602 HAL_FULL_RX_BW_40, 603 HAL_FULL_RX_BW_80, 604 HAL_FULL_RX_BW_160, 605 }; 606 #endif 607 608 enum { 609 HAL_RX_TYPE_SU, 610 HAL_RX_TYPE_MU_MIMO, 611 HAL_RX_TYPE_MU_OFDMA, 612 HAL_RX_TYPE_MU_OFDMA_MIMO, 613 }; 614 615 enum { 616 HAL_RX_TYPE_DL, 617 HAL_RX_TYPE_UL, 618 }; 619 620 /** 621 * enum 622 * @HAL_RECEPTION_TYPE_SU: Basic SU reception 623 * @HAL_RECEPTION_TYPE_DL_MU_MIMO: DL MU_MIMO reception 624 * @HAL_RECEPTION_TYPE_DL_MU_OFMA: DL MU_OFMA reception 625 * @HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: DL MU_OFDMA_MIMO reception 626 * @HAL_RECEPTION_TYPE_UL_MU_MIMO: UL MU_MIMO reception 627 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA: UL MU_OFMA reception 628 * @HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: UL MU_OFDMA_MIMO reception 629 */ 630 enum { 631 HAL_RECEPTION_TYPE_SU, 632 HAL_RECEPTION_TYPE_DL_MU_MIMO, 633 HAL_RECEPTION_TYPE_DL_MU_OFMA, 634 HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, 635 HAL_RECEPTION_TYPE_UL_MU_MIMO, 636 HAL_RECEPTION_TYPE_UL_MU_OFDMA, 637 HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO 638 }; 639 640 /** 641 * enum 642 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL 643 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decoded in HAL 644 * @HAL_RX_MON_PPDU_RESET: Not PPDU start and end TLV 645 */ 646 enum { 647 HAL_RX_MON_PPDU_START = 0, 648 HAL_RX_MON_PPDU_END, 649 HAL_RX_MON_PPDU_RESET, 650 }; 651 652 /** 653 * struct hal_rx_ppdu_common_info - common ppdu info 654 * @ppdu_id: ppdu id number 655 * @ppdu_timestamp: timestamp at ppdu received 656 * @mpdu_cnt_fcs_ok: mpdu count in ppdu with fcs ok 657 * @mpdu_cnt_fcs_err: mpdu count in ppdu with fcs err 658 * @num_users: num users 659 * @mpdu_fcs_ok_bitmap: fcs ok mpdu count in ppdu bitmap 660 * @last_ppdu_id: last received ppdu id 661 * @mpdu_cnt: total mpdu count 662 */ 663 struct hal_rx_ppdu_common_info { 664 uint32_t ppdu_id; 665 uint64_t ppdu_timestamp; 666 uint16_t mpdu_cnt_fcs_ok; 667 uint8_t mpdu_cnt_fcs_err; 668 uint8_t num_users; 669 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; 670 uint32_t last_ppdu_id; 671 uint16_t mpdu_cnt; 672 }; 673 674 /** 675 * struct hal_rx_msdu_payload_info - msdu payload info 676 * @first_msdu_payload: pointer to first msdu payload 677 * @payload_len: payload len 678 */ 679 struct hal_rx_msdu_payload_info { 680 uint8_t *first_msdu_payload; 681 uint16_t payload_len; 682 }; 683 684 /** 685 * struct hal_rx_nac_info - struct for neighbour info 686 * @fc_valid: flag indicate if it has valid frame control information 687 * @frame_control: frame control from each MPDU 688 * @to_ds_flag: flag indicate to_ds bit 689 * @mac_addr2_valid: flag indicate if mac_addr2 is valid 690 * @mcast_bcast: multicast/broadcast 691 * @mac_addr2: mac address2 in wh 692 */ 693 struct hal_rx_nac_info { 694 uint32_t fc_valid : 1, 695 frame_control : 16, 696 to_ds_flag : 1, 697 mac_addr2_valid : 1, 698 mcast_bcast : 1; 699 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE]; 700 }; 701 702 /** 703 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs 704 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV 705 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV 706 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred 707 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not 708 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV 709 */ 710 struct hal_rx_ppdu_msdu_info { 711 uint32_t fse_metadata; 712 uint32_t cce_metadata : 16, 713 is_flow_idx_timeout : 1, 714 is_flow_idx_invalid : 1; 715 uint32_t flow_idx : 20; 716 }; 717 718 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 719 /** 720 * struct hal_rx_ppdu_cfr_user_info - struct for storing peer info extracted 721 * from HW TLVs, this will be used for correlating CFR data with multiple peers 722 * in MU PPDUs 723 * 724 * @peer_macaddr: macaddr of the peer 725 * @ast_index: AST index of the peer 726 */ 727 struct hal_rx_ppdu_cfr_user_info { 728 uint8_t peer_macaddr[QDF_MAC_ADDR_SIZE]; 729 uint16_t ast_index; 730 }; 731 732 /** 733 * struct hal_rx_ppdu_cfr_info - struct for storing ppdu info extracted from HW 734 * TLVs, this will be used for CFR correlation 735 * 736 * @bb_captured_channel : Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is 737 * sent to PHY, SW checks it to correlate current PPDU TLVs with uploaded 738 * channel information. 739 * 740 * @bb_captured_timeout : Set by RxPCU to indicate channel capture condition is 741 * met, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due to AST delay, 742 * which means the rx_frame_falling edge to FREEZE TLV ready time exceeds 743 * the threshold time defined by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 744 * Bb_captured_reason is still valid in this case. 745 * 746 * @rx_location_info_valid: Indicates whether CFR DMA address in the PPDU TLV 747 * is valid 748 * <enum 0 rx_location_info_is_not_valid> 749 * <enum 1 rx_location_info_is_valid> 750 * <legal all> 751 * 752 * @bb_captured_reason : Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL 753 * TLV to here for FW usage. Valid when bb_captured_channel or 754 * bb_captured_timeout is set. 755 * <enum 0 freeze_reason_TM> 756 * <enum 1 freeze_reason_FTM> 757 * <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 758 * <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 759 * <enum 4 freeze_reason_NDPA_NDP> 760 * <enum 5 freeze_reason_ALL_PACKET> 761 * <legal 0-5> 762 * 763 * @rtt_che_buffer_pointer_low32 : The low 32 bits of the 40 bits pointer to 764 * external RTT channel information buffer 765 * 766 * @rtt_che_buffer_pointer_high8 : The high 8 bits of the 40 bits pointer to 767 * external RTT channel information buffer 768 * 769 * @chan_capture_status : capture status reported by ucode 770 * a. CAPTURE_IDLE: FW has disabled "REPETITIVE_CHE_CAPTURE_CTRL" 771 * b. CAPTURE_BUSY: previous PPDU’s channel capture upload DMA ongoing. (Note 772 * that this upload is triggered after receiving freeze_channel_capture TLV 773 * after last PPDU is rx) 774 * c. CAPTURE_ACTIVE: channel capture is enabled and no previous channel 775 * capture ongoing 776 * d. CAPTURE_NO_BUFFER: next buffer in IPC ring not available 777 * 778 * @cfr_user_info: Peer mac for upto 4 MU users 779 * 780 * @rtt_cfo_measurement : raw cfo data extracted from hardware, which is 14 bit 781 * signed number. The first bit used for sign representation and 13 bits for 782 * fractional part. 783 * 784 * @agc_gain_info0: Chain 0 & chain 1 agc gain information reported by PHY 785 * 786 * @agc_gain_info1: Chain 2 & chain 3 agc gain information reported by PHY 787 * 788 * @agc_gain_info2: Chain 4 & chain 5 agc gain information reported by PHY 789 * 790 * @agc_gain_info3: Chain 6 & chain 7 agc gain information reported by PHY 791 * 792 * @rx_start_ts: Rx packet timestamp, the time the first L-STF ADC sample 793 * arrived at Rx antenna. 794 * 795 * @mcs_rate: Indicates the mcs/rate in which packet is received. 796 * If HT, 797 * 0-7: MCS0-MCS7 798 * If VHT, 799 * 0-9: MCS0 to MCS9 800 * If HE, 801 * 0-11: MCS0 to MCS11, 802 * 12-13: 4096QAM, 803 * 14-15: reserved 804 * If Legacy, 805 * 0: 48 Mbps 806 * 1: 24 Mbps 807 * 2: 12 Mbps 808 * 3: 6 Mbps 809 * 4: 54 Mbps 810 * 5: 36 Mbps 811 * 6: 18 Mbps 812 * 7: 9 Mbps 813 * 814 * @gi_type: Indicates the guard interval. 815 * 0: 0.8 us 816 * 1: 0.4 us 817 * 2: 1.6 us 818 * 3: 3.2 us 819 */ 820 struct hal_rx_ppdu_cfr_info { 821 bool bb_captured_channel; 822 bool bb_captured_timeout; 823 uint8_t bb_captured_reason; 824 bool rx_location_info_valid; 825 uint8_t chan_capture_status; 826 uint8_t rtt_che_buffer_pointer_high8; 827 uint32_t rtt_che_buffer_pointer_low32; 828 int16_t rtt_cfo_measurement; 829 uint32_t agc_gain_info0; 830 uint32_t agc_gain_info1; 831 uint32_t agc_gain_info2; 832 uint32_t agc_gain_info3; 833 uint32_t rx_start_ts; 834 uint32_t mcs_rate; 835 uint32_t gi_type; 836 }; 837 #else 838 struct hal_rx_ppdu_cfr_info {}; 839 #endif 840 841 struct mon_rx_info { 842 uint8_t qos_control_info_valid; 843 uint16_t qos_control; 844 uint8_t mac_addr1_valid; 845 uint8_t mac_addr1[QDF_MAC_ADDR_SIZE]; 846 uint16_t user_id; 847 }; 848 849 struct mon_rx_user_info { 850 uint16_t qos_control; 851 uint8_t qos_control_info_valid; 852 }; 853 854 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 855 struct hal_rx_frm_type_info { 856 uint8_t rx_mgmt_cnt; 857 uint8_t rx_ctrl_cnt; 858 uint8_t rx_data_cnt; 859 }; 860 #else 861 struct hal_rx_frm_type_info {}; 862 #endif 863 864 struct hal_mon_usig_cmn { 865 uint32_t phy_version : 3, 866 bw : 3, 867 ul_dl : 1, 868 bss_color : 6, 869 txop : 7, 870 disregard : 5, 871 validate_0 : 1, 872 reserved : 6; 873 }; 874 875 struct hal_mon_usig_tb { 876 uint32_t ppdu_type_comp_mode : 2, 877 validate_1 : 1, 878 spatial_reuse_1 : 4, 879 spatial_reuse_2 : 4, 880 disregard_1 : 5, 881 crc : 4, 882 tail : 6, 883 reserved : 5, 884 rx_integrity_check_passed : 1; 885 }; 886 887 struct hal_mon_usig_mu { 888 uint32_t ppdu_type_comp_mode : 2, 889 validate_1 : 1, 890 punc_ch_info : 5, 891 validate_2 : 1, 892 eht_sig_mcs : 2, 893 num_eht_sig_sym : 5, 894 crc : 4, 895 tail : 6, 896 reserved : 5, 897 rx_integrity_check_passed : 1; 898 }; 899 900 /** 901 * union hal_mon_usig_non_cmn: Version dependent USIG fields 902 * @tb: trigger based frame USIG header 903 * @mu: MU frame USIG header 904 */ 905 union hal_mon_usig_non_cmn { 906 struct hal_mon_usig_tb tb; 907 struct hal_mon_usig_mu mu; 908 }; 909 910 /** 911 * struct hal_mon_usig_hdr: U-SIG header for EHT (and subsequent) frames 912 * @usig_1: USIG common header fields 913 * @usig_2: USIG version dependent fields 914 */ 915 struct hal_mon_usig_hdr { 916 struct hal_mon_usig_cmn usig_1; 917 union hal_mon_usig_non_cmn usig_2; 918 }; 919 920 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK 0x0000000300000000 921 #define HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB 32 922 923 #define HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(usig_tlv_ptr) \ 924 ((*((uint64_t *)(usig_tlv_ptr)) & \ 925 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_MASK) >> \ 926 HAL_RX_MON_USIG_PPDU_TYPE_N_COMP_MODE_LSB) 927 928 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 929 #define HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB 63 930 931 #define HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(usig_tlv_ptr) \ 932 ((*((uint64_t *)(usig_tlv_ptr)) & \ 933 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_MASK) >> \ 934 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB) 935 936 /** 937 * enum hal_eht_bw - Reception bandwidth 938 * @HAL_EHT_BW_20: 20Mhz 939 * @HAL_EHT_BW_40: 40Mhz 940 * @HAL_EHT_BW_80: 80Mhz 941 * @HAL_EHT_BW_160: 160Mhz 942 * @HAL_EHT_BW_320_1: 320_1 band 943 * @HAL_EHT_BW_320_2: 320_2 band 944 */ 945 enum hal_eht_bw { 946 HAL_EHT_BW_20 = 0, 947 HAL_EHT_BW_40, 948 HAL_EHT_BW_80, 949 HAL_EHT_BW_160, 950 HAL_EHT_BW_320_1, 951 HAL_EHT_BW_320_2, 952 }; 953 954 struct hal_eht_sig_mu_mimo_user_info { 955 uint32_t sta_id : 11, 956 mcs : 4, 957 coding : 1, 958 spatial_coding : 6, 959 crc : 4; 960 }; 961 962 struct hal_eht_sig_non_mu_mimo_user_info { 963 uint32_t sta_id : 11, 964 mcs : 4, 965 validate : 1, 966 nss : 4, 967 beamformed : 1, 968 coding : 1, 969 crc : 4; 970 }; 971 972 /** 973 * union hal_eht_sig_user_field - User field in EHTSIG 974 * @mu_mimo_usr: MU-MIMO user field information in EHTSIG 975 * @non_mu_mimo_usr: Non MU-MIMO user field information in EHTSIG 976 */ 977 union hal_eht_sig_user_field { 978 struct hal_eht_sig_mu_mimo_user_info mu_mimo_usr; 979 struct hal_eht_sig_non_mu_mimo_user_info non_mu_mimo_usr; 980 }; 981 982 struct hal_eht_sig_ofdma_cmn_eb1 { 983 uint64_t spatial_reuse : 4, 984 gi_ltf : 2, 985 num_ltf_sym : 3, 986 ldpc_extra_sym : 1, 987 pre_fec_pad_factor : 2, 988 pe_disambiguity : 1, 989 disregard : 4, 990 ru_allocation1_1 : 9, 991 ru_allocation1_2 : 9, 992 crc : 4; 993 }; 994 995 struct hal_eht_sig_ofdma_cmn_eb2 { 996 uint64_t ru_allocation2_1 : 9, 997 ru_allocation2_2 : 9, 998 ru_allocation2_3 : 9, 999 ru_allocation2_4 : 9, 1000 ru_allocation2_5 : 9, 1001 ru_allocation2_6 : 9, 1002 crc : 4; 1003 }; 1004 1005 struct hal_eht_sig_cc_usig_overflow { 1006 uint32_t spatial_reuse : 4, 1007 gi_ltf : 2, 1008 num_ltf_sym : 3, 1009 ldpc_extra_sym : 1, 1010 pre_fec_pad_factor : 2, 1011 pe_disambiguity : 1, 1012 disregard : 4; 1013 }; 1014 1015 struct hal_eht_sig_non_ofdma_cmn_eb { 1016 uint32_t spatial_reuse : 4, 1017 gi_ltf : 2, 1018 num_ltf_sym : 3, 1019 ldpc_extra_sym : 1, 1020 pre_fec_pad_factor : 2, 1021 pe_disambiguity : 1, 1022 disregard : 4, 1023 num_users : 3; 1024 union hal_eht_sig_user_field user_field; 1025 }; 1026 1027 struct hal_eht_sig_ndp_cmn_eb { 1028 uint32_t spatial_reuse : 4, 1029 gi_ltf : 2, 1030 num_ltf_sym : 3, 1031 nss : 4, 1032 beamformed : 1, 1033 disregard : 2, 1034 crc : 4; 1035 }; 1036 1037 /* Different allowed RU in 11BE */ 1038 #define HAL_EHT_RU_26 0ULL 1039 #define HAL_EHT_RU_52 1ULL 1040 #define HAL_EHT_RU_78 2ULL 1041 #define HAL_EHT_RU_106 3ULL 1042 #define HAL_EHT_RU_132 4ULL 1043 #define HAL_EHT_RU_242 5ULL 1044 #define HAL_EHT_RU_484 6ULL 1045 #define HAL_EHT_RU_726 7ULL 1046 #define HAL_EHT_RU_996 8ULL 1047 #define HAL_EHT_RU_996x2 9ULL 1048 #define HAL_EHT_RU_996x3 10ULL 1049 #define HAL_EHT_RU_996x4 11ULL 1050 #define HAL_EHT_RU_NONE 15ULL 1051 #define HAL_EHT_RU_INVALID 31ULL 1052 /* 1053 * MRUs spanning above 80Mhz 1054 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved) 1055 */ 1056 #define HAL_EHT_RU_996_484 18ULL 1057 #define HAL_EHT_RU_996x2_484 28ULL 1058 #define HAL_EHT_RU_996x3_484 40ULL 1059 #define HAL_EHT_RU_996_484_242 23ULL 1060 1061 /** 1062 * enum ieee80211_eht_ru_size: RU type id in EHTSIG radiotap header 1063 * @IEEE80211_EHT_RU_26: RU26 1064 * @IEEE80211_EHT_RU_52: RU52 1065 * @IEEE80211_EHT_RU_106: RU106 1066 * @IEEE80211_EHT_RU_242: RU242 1067 * @IEEE80211_EHT_RU_484: RU484 1068 * @IEEE80211_EHT_RU_996: RU996 1069 * @IEEE80211_EHT_RU_996x2: RU996x2 1070 * @IEEE80211_EHT_RU_996x4: RU996x4 1071 * @IEEE80211_EHT_RU_52_26: RU52+RU26 1072 * @IEEE80211_EHT_RU_106_26: RU106+RU26 1073 * @IEEE80211_EHT_RU_484_242: RU484+RU242 1074 * @IEEE80211_EHT_RU_996_484: RU996+RU484 1075 * @IEEE80211_EHT_RU_996_484_242: RU996+RU484+RU242 1076 * @IEEE80211_EHT_RU_996x2_484: RU996x2 + RU484 1077 * @IEEE80211_EHT_RU_996x3: RU996x3 1078 * @IEEE80211_EHT_RU_996x3_484: RU996x3 + RU484 1079 * @IEEE80211_EHT_RU_INVALID: Invalid/Max RU 1080 */ 1081 enum ieee80211_eht_ru_size { 1082 IEEE80211_EHT_RU_26, 1083 IEEE80211_EHT_RU_52, 1084 IEEE80211_EHT_RU_106, 1085 IEEE80211_EHT_RU_242, 1086 IEEE80211_EHT_RU_484, 1087 IEEE80211_EHT_RU_996, 1088 IEEE80211_EHT_RU_996x2, 1089 IEEE80211_EHT_RU_996x4, 1090 IEEE80211_EHT_RU_52_26, 1091 IEEE80211_EHT_RU_106_26, 1092 IEEE80211_EHT_RU_484_242, 1093 IEEE80211_EHT_RU_996_484, 1094 IEEE80211_EHT_RU_996_484_242, 1095 IEEE80211_EHT_RU_996x2_484, 1096 IEEE80211_EHT_RU_996x3, 1097 IEEE80211_EHT_RU_996x3_484, 1098 IEEE80211_EHT_RU_INVALID, 1099 }; 1100 1101 #define NUM_RU_BITS_PER80 16 1102 #define NUM_RU_BITS_PER20 4 1103 1104 /* Different per_80Mhz band in 320Mhz bandwidth */ 1105 #define HAL_80_0 0 1106 #define HAL_80_1 1 1107 #define HAL_80_2 2 1108 #define HAL_80_3 3 1109 1110 #define HAL_RU_SHIFT(num_80mhz_band, ru_index_per_80) \ 1111 ((NUM_RU_BITS_PER80 * (num_80mhz_band)) + \ 1112 (NUM_RU_BITS_PER20 * (ru_index_per_80))) 1113 1114 /* MRU-996+484 */ 1115 #define HAL_EHT_RU_996_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1116 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1117 #define HAL_EHT_RU_996_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1118 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) 1119 #define HAL_EHT_RU_996_484_2 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1120 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1))) 1121 #define HAL_EHT_RU_996_484_3 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1122 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0))) 1123 #define HAL_EHT_RU_996_484_4 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1124 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1125 #define HAL_EHT_RU_996_484_5 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1126 (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) 1127 #define HAL_EHT_RU_996_484_6 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1128 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1129 #define HAL_EHT_RU_996_484_7 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1130 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1131 1132 /* MRU-996x2+484 */ 1133 #define HAL_EHT_RU_996x2_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1134 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1135 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1136 #define HAL_EHT_RU_996x2_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1137 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1138 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1139 #define HAL_EHT_RU_996x2_484_2 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1140 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1141 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1142 #define HAL_EHT_RU_996x2_484_3 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1143 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1144 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) 1145 #define HAL_EHT_RU_996x2_484_4 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1146 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1147 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1))) 1148 #define HAL_EHT_RU_996x2_484_5 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1149 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1150 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0))) 1151 #define HAL_EHT_RU_996x2_484_6 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1152 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1153 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1154 #define HAL_EHT_RU_996x2_484_7 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1155 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1156 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1157 #define HAL_EHT_RU_996x2_484_8 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1158 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1159 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1160 #define HAL_EHT_RU_996x2_484_9 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1161 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1162 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) 1163 #define HAL_EHT_RU_996x2_484_10 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1164 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1165 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1166 #define HAL_EHT_RU_996x2_484_11 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1167 (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1168 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1169 1170 /* MRU-996x3+484 */ 1171 #define HAL_EHT_RU_996x3_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ 1172 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1173 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1174 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1175 #define HAL_EHT_RU_996x3_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1176 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1177 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1178 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1179 #define HAL_EHT_RU_996x3_484_2 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1180 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ 1181 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1182 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1183 #define HAL_EHT_RU_996x3_484_3 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1184 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1185 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1186 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1187 #define HAL_EHT_RU_996x3_484_4 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1188 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1189 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ 1190 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1191 #define HAL_EHT_RU_996x3_484_5 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1192 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1193 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1194 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) 1195 #define HAL_EHT_RU_996x3_484_6 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1196 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1197 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1198 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) 1199 #define HAL_EHT_RU_996x3_484_7 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ 1200 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ 1201 (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ 1202 (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) 1203 1204 #define HAL_RX_MON_MAX_AGGR_SIZE 192 1205 1206 /** 1207 * struct hal_rx_tlv_aggr_info - Data structure to hold 1208 * metadata for aggregatng repeated TLVs 1209 * @in_progress: Flag to indicate if TLV aggregation is in progress 1210 * @rd_idx: idx to current section of TLV 1211 * @cur_len: Total length of currently aggregated TLV 1212 * @tlv_tag: TLV tag which is currently being aggregated 1213 * @buf: Buffer containing aggregated TLV data 1214 */ 1215 struct hal_rx_tlv_aggr_info { 1216 uint8_t in_progress; 1217 uint8_t rd_idx; 1218 uint16_t cur_len; 1219 uint32_t tlv_tag; 1220 uint8_t buf[HAL_RX_MON_MAX_AGGR_SIZE]; 1221 }; 1222 1223 /** 1224 * struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used 1225 * for other header field parsing. 1226 * @ul_dl: UL or DL 1227 * @bw: EHT BW 1228 * @ppdu_type_comp_mode: PPDU TYPE 1229 * @eht_sig_mcs: EHT SIG MCS 1230 * @num_eht_sig_sym: Number of EHT SIG symbols 1231 */ 1232 struct hal_rx_u_sig_info { 1233 uint32_t ul_dl : 1, 1234 bw : 3, 1235 ppdu_type_comp_mode : 2, 1236 eht_sig_mcs : 2, 1237 num_eht_sig_sym : 5; 1238 }; 1239 1240 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 1241 struct hal_rx_user_ctrl_frm_info { 1242 uint8_t bar : 1, 1243 ndpa : 1; 1244 }; 1245 #else 1246 struct hal_rx_user_ctrl_frm_info {}; 1247 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 1248 1249 #ifdef MONITOR_TLV_RECORDING_ENABLE 1250 /** 1251 * struct hal_rx_tlv_info - TLV info to pass to dp layer 1252 * @tlv_tag: Tag of the TLV 1253 * @tlv_category: Category of TLV 1254 * 1255 */ 1256 struct hal_rx_tlv_info { 1257 uint32_t tlv_tag; 1258 uint8_t tlv_category; 1259 }; 1260 #endif 1261 1262 struct hal_rx_ppdu_info { 1263 struct hal_rx_ppdu_common_info com_info; 1264 struct hal_rx_u_sig_info u_sig_info; 1265 struct mon_rx_status rx_status; 1266 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS]; 1267 struct mon_rx_info rx_info; 1268 struct mon_rx_user_info rx_user_info[HAL_MAX_UL_MU_USERS]; 1269 struct hal_rx_msdu_payload_info msdu_info; 1270 struct hal_rx_msdu_payload_info fcs_ok_msdu_info; 1271 struct hal_rx_nac_info nac_info; 1272 /* status ring PPDU start and end state */ 1273 uint8_t rx_state; 1274 /* MU user id for status ring TLV */ 1275 uint8_t user_id; 1276 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */ 1277 unsigned char *data; 1278 /* MPDU/MSDU truncated to 128 bytes header real length */ 1279 uint32_t hdr_len; 1280 /* MPDU FCS error */ 1281 bool fcs_err; 1282 /* Id to indicate how to process mpdu */ 1283 uint8_t sw_frame_group_id; 1284 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS]; 1285 /* fcs passed mpdu count in rx monitor status buffer */ 1286 uint8_t fcs_ok_cnt; 1287 /* fcs error mpdu count in rx monitor status buffer */ 1288 uint8_t fcs_err_cnt; 1289 /* MPDU FCS passed */ 1290 bool is_fcs_passed; 1291 /* first msdu payload for all mpdus in rx monitor status buffer */ 1292 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER]; 1293 /* evm info */ 1294 struct hal_rx_su_evm_info evm_info; 1295 /** 1296 * Will be used to store ppdu info extracted from HW TLVs, 1297 * and for CFR correlation as well 1298 */ 1299 struct hal_rx_ppdu_cfr_info cfr_info; 1300 /* per frame type counts */ 1301 struct hal_rx_frm_type_info frm_type_info; 1302 /* TLV aggregation metadata context */ 1303 struct hal_rx_tlv_aggr_info tlv_aggr; 1304 /* EHT SIG user info */ 1305 uint32_t eht_sig_user_info; 1306 /*per user mpdu count */ 1307 uint8_t mpdu_count[HAL_MAX_UL_MU_USERS]; 1308 /*per user msdu count */ 1309 uint8_t msdu_count[HAL_MAX_UL_MU_USERS]; 1310 /* Placeholder to update per user last processed msdu’s info */ 1311 struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS]; 1312 /* Placeholder to update per user last processed mpdu’s info */ 1313 struct hal_rx_mon_mpdu_info mpdu_info[HAL_MAX_UL_MU_USERS]; 1314 /* placeholder to hold packet buffer info */ 1315 struct hal_mon_packet_info packet_info; 1316 #if defined(WLAN_PKT_CAPTURE_RX_2_0) && defined(QCA_MONITOR_2_0_PKT_SUPPORT) 1317 /* per user per MPDU queue */ 1318 qdf_nbuf_queue_t mpdu_q[HAL_MAX_UL_MU_USERS]; 1319 /* ppdu info list element */ 1320 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem; 1321 /* ppdu info free list element */ 1322 TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_free_list_elem; 1323 /* placeholder to track if RX_HDR is received */ 1324 uint8_t rx_hdr_rcvd[HAL_MAX_UL_MU_USERS]; 1325 #endif 1326 /* Per user BAR and NDPA bit flag */ 1327 struct hal_rx_user_ctrl_frm_info ctrl_frm_info[HAL_MAX_UL_MU_USERS]; 1328 /* PPDU end user stats count */ 1329 uint8_t end_user_stats_cnt; 1330 /* PPDU start user info count */ 1331 uint8_t start_user_info_cnt; 1332 /* PPDU drop cnt */ 1333 struct hal_rx_ppdu_drop_cnt drop_cnt; 1334 #ifdef MONITOR_TLV_RECORDING_ENABLE 1335 /*TLV Recording*/ 1336 struct hal_rx_tlv_info rx_tlv_info; 1337 #endif 1338 }; 1339 1340 static inline uint32_t hal_get_rx_status_buf_size(void)1341 hal_get_rx_status_buf_size(void) { 1342 /* RX status buffer size is hard coded for now */ 1343 return 2048; 1344 } 1345 1346 static inline uint8_t* hal_rx_status_get_next_tlv(uint8_t * rx_tlv,bool is_tlv_hdr_64_bit)1347 hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) { 1348 uint32_t tlv_len, tlv_tag, tlv_hdr_size; 1349 1350 if (is_tlv_hdr_64_bit) { 1351 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1352 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1353 1354 tlv_hdr_size = HAL_RX_TLV64_HDR_SIZE; 1355 } else { 1356 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv); 1357 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1358 1359 tlv_hdr_size = HAL_RX_TLV32_HDR_SIZE; 1360 } 1361 1362 /* The actual length of PPDU_END is the combined length of many PHY 1363 * TLVs that follow. Skip the TLV header and 1364 * rx_rxpcu_classification_overview that follows the header to get to 1365 * next TLV. 1366 */ 1367 if (tlv_tag == WIFIRX_PPDU_END_E) 1368 tlv_len = sizeof(struct rx_rxpcu_classification_overview); 1369 1370 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)rx_tlv + 1371 tlv_len + 1372 tlv_hdr_size), 1373 tlv_hdr_size); 1374 } 1375 1376 /** 1377 * hal_rx_parse_eht_sig_hdr() 1378 * - process eht sig header 1379 * @hal_soc: HAL soc handle 1380 * @tlv: pointer to EHT SIG TLV buffer 1381 * @ppdu_info: pointer to ppdu_info 1382 * 1383 * Return: None 1384 */ hal_rx_parse_eht_sig_hdr(struct hal_soc * hal_soc,uint8_t * tlv,struct hal_rx_ppdu_info * ppdu_info)1385 static inline void hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, 1386 uint8_t *tlv, 1387 struct hal_rx_ppdu_info 1388 *ppdu_info) 1389 { 1390 hal_soc->ops->hal_rx_parse_eht_sig_hdr(hal_soc, tlv, (void *)ppdu_info); 1391 } 1392 1393 /** 1394 * hal_rx_proc_phyrx_other_receive_info_tlv() 1395 * - process other receive info TLV 1396 * @hal_soc: HAL soc object 1397 * @rx_tlv_hdr: pointer to TLV header 1398 * @ppdu_info: pointer to ppdu_info 1399 * 1400 * Return: None 1401 */ 1402 static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc * hal_soc,void * rx_tlv_hdr,struct hal_rx_ppdu_info * ppdu_info)1403 hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc, 1404 void *rx_tlv_hdr, 1405 struct hal_rx_ppdu_info 1406 *ppdu_info) 1407 { 1408 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, 1409 (void *)ppdu_info); 1410 } 1411 1412 /** 1413 * hal_rx_status_get_tlv_info() - process receive info TLV 1414 * @rx_tlv_hdr: pointer to TLV header 1415 * @ppdu_info: pointer to ppdu_info 1416 * @hal_soc_hdl: HAL soc handle 1417 * @nbuf: PPDU status network buffer 1418 * 1419 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 1420 */ 1421 static inline uint32_t hal_rx_status_get_tlv_info(void * rx_tlv_hdr,void * ppdu_info,hal_soc_handle_t hal_soc_hdl,qdf_nbuf_t nbuf)1422 hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info, 1423 hal_soc_handle_t hal_soc_hdl, 1424 qdf_nbuf_t nbuf) 1425 { 1426 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1427 1428 return hal_soc->ops->hal_rx_status_get_tlv_info( 1429 rx_tlv_hdr, 1430 ppdu_info, 1431 hal_soc_hdl, 1432 nbuf); 1433 } 1434 1435 static inline hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl)1436 uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl) 1437 { 1438 return HAL_RX_TLV32_HDR_SIZE; 1439 } 1440 1441 static inline QDF_STATUS hal_get_rx_status_done(uint8_t * rx_tlv)1442 hal_get_rx_status_done(uint8_t *rx_tlv) 1443 { 1444 uint32_t tlv_tag; 1445 1446 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 1447 1448 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E) 1449 return QDF_STATUS_SUCCESS; 1450 else 1451 return QDF_STATUS_E_EMPTY; 1452 } 1453 1454 static inline QDF_STATUS hal_clear_rx_status_done(uint8_t * rx_tlv)1455 hal_clear_rx_status_done(uint8_t *rx_tlv) 1456 { 1457 *(uint32_t *)rx_tlv = 0; 1458 return QDF_STATUS_SUCCESS; 1459 } 1460 1461 #ifdef WLAN_PKT_CAPTURE_TX_2_0 1462 /** 1463 * struct hal_txmon_word_mask_config - hal tx monitor word mask filter setting 1464 * @pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask 1465 * @tx_peer_entry: TX_PEER_ENTRY TLV word mask 1466 * @tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask 1467 * @tx_fes_status_end: TX_FES_STATUS_END TLV word mask 1468 * @response_end_status: RESPONSE_END_STATUS TLV word mask 1469 * @tx_fes_status_prot: TX_FES_STATUS_PROT TLV word mask 1470 * @tx_fes_setup: TX_FES_SETUP TLV word mask 1471 * @tx_msdu_start: TX_MSDU_START TLV word mask 1472 * @tx_mpdu_start: TX_MPDU_START TLV word mask 1473 * @rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask 1474 * @compaction_enable: flag to enable word mask compaction 1475 */ 1476 struct hal_txmon_word_mask_config { 1477 uint32_t pcu_ppdu_setup_init; 1478 uint16_t tx_peer_entry; 1479 uint16_t tx_queue_ext; 1480 uint16_t tx_fes_status_end; 1481 uint16_t response_end_status; 1482 uint16_t tx_fes_status_prot; 1483 uint8_t tx_fes_setup; 1484 uint8_t tx_msdu_start; 1485 uint8_t tx_mpdu_start; 1486 uint8_t rxpcu_user_setup; 1487 uint8_t compaction_enable; 1488 }; 1489 1490 /* 1491 * typedef hal_txmon_word_mask_config_t - handle for tx monitor word mask 1492 */ 1493 typedef struct hal_txmon_word_mask_config hal_txmon_word_mask_config_t; 1494 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 1495 #endif 1496