1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tools/testing/selftests/kvm/include/x86_64/apic.h
4 *
5 * Copyright (C) 2021, Google LLC.
6 */
7
8 #ifndef SELFTEST_KVM_APIC_H
9 #define SELFTEST_KVM_APIC_H
10
11 #include <stdint.h>
12
13 #include "processor.h"
14 #include "ucall_common.h"
15
16 #define APIC_DEFAULT_GPA 0xfee00000ULL
17
18 /* APIC base address MSR and fields */
19 #define MSR_IA32_APICBASE 0x0000001b
20 #define MSR_IA32_APICBASE_BSP (1<<8)
21 #define MSR_IA32_APICBASE_EXTD (1<<10)
22 #define MSR_IA32_APICBASE_ENABLE (1<<11)
23 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
24 #define GET_APIC_BASE(x) (((x) >> 12) << 12)
25
26 #define APIC_BASE_MSR 0x800
27 #define X2APIC_ENABLE (1UL << 10)
28 #define APIC_ID 0x20
29 #define APIC_LVR 0x30
30 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
31 #define APIC_TASKPRI 0x80
32 #define APIC_PROCPRI 0xA0
33 #define APIC_EOI 0xB0
34 #define APIC_SPIV 0xF0
35 #define APIC_SPIV_FOCUS_DISABLED (1 << 9)
36 #define APIC_SPIV_APIC_ENABLED (1 << 8)
37 #define APIC_IRR 0x200
38 #define APIC_ICR 0x300
39 #define APIC_LVTCMCI 0x2f0
40 #define APIC_DEST_SELF 0x40000
41 #define APIC_DEST_ALLINC 0x80000
42 #define APIC_DEST_ALLBUT 0xC0000
43 #define APIC_ICR_RR_MASK 0x30000
44 #define APIC_ICR_RR_INVALID 0x00000
45 #define APIC_ICR_RR_INPROG 0x10000
46 #define APIC_ICR_RR_VALID 0x20000
47 #define APIC_INT_LEVELTRIG 0x08000
48 #define APIC_INT_ASSERT 0x04000
49 #define APIC_ICR_BUSY 0x01000
50 #define APIC_DEST_LOGICAL 0x00800
51 #define APIC_DEST_PHYSICAL 0x00000
52 #define APIC_DM_FIXED 0x00000
53 #define APIC_DM_FIXED_MASK 0x00700
54 #define APIC_DM_LOWEST 0x00100
55 #define APIC_DM_SMI 0x00200
56 #define APIC_DM_REMRD 0x00300
57 #define APIC_DM_NMI 0x00400
58 #define APIC_DM_INIT 0x00500
59 #define APIC_DM_STARTUP 0x00600
60 #define APIC_DM_EXTINT 0x00700
61 #define APIC_VECTOR_MASK 0x000FF
62 #define APIC_ICR2 0x310
63 #define SET_APIC_DEST_FIELD(x) ((x) << 24)
64 #define APIC_LVTT 0x320
65 #define APIC_LVT_TIMER_ONESHOT (0 << 17)
66 #define APIC_LVT_TIMER_PERIODIC (1 << 17)
67 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)
68 #define APIC_LVT_MASKED (1 << 16)
69 #define APIC_TMICT 0x380
70 #define APIC_TMCCT 0x390
71 #define APIC_TDCR 0x3E0
72
73 void apic_disable(void);
74 void xapic_enable(void);
75 void x2apic_enable(void);
76
get_bsp_flag(void)77 static inline uint32_t get_bsp_flag(void)
78 {
79 return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP;
80 }
81
xapic_read_reg(unsigned int reg)82 static inline uint32_t xapic_read_reg(unsigned int reg)
83 {
84 return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2];
85 }
86
xapic_write_reg(unsigned int reg,uint32_t val)87 static inline void xapic_write_reg(unsigned int reg, uint32_t val)
88 {
89 ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val;
90 }
91
x2apic_read_reg(unsigned int reg)92 static inline uint64_t x2apic_read_reg(unsigned int reg)
93 {
94 return rdmsr(APIC_BASE_MSR + (reg >> 4));
95 }
96
x2apic_write_reg_safe(unsigned int reg,uint64_t value)97 static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value)
98 {
99 return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value);
100 }
101
x2apic_write_reg(unsigned int reg,uint64_t value)102 static inline void x2apic_write_reg(unsigned int reg, uint64_t value)
103 {
104 uint8_t fault = x2apic_write_reg_safe(reg, value);
105
106 __GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n",
107 fault, APIC_BASE_MSR + (reg >> 4), value);
108 }
109
x2apic_write_reg_fault(unsigned int reg,uint64_t value)110 static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value)
111 {
112 uint8_t fault = x2apic_write_reg_safe(reg, value);
113
114 __GUEST_ASSERT(fault == GP_VECTOR,
115 "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n",
116 APIC_BASE_MSR + (reg >> 4), value, fault);
117 }
118
119
120 #endif /* SELFTEST_KVM_APIC_H */
121