1 /* 2 * GFX_8_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef GFX_8_0_SH_MASK_H 25 #define GFX_8_0_SH_MASK_H 26 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff 28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff 30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff 32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff 34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 37 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2 38 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 39 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c 40 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 41 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 42 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 43 #define CB_COLOR_CONTROL__MODE_MASK 0x70 44 #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 45 #define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 46 #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 47 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f 48 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 49 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 50 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 51 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 52 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 53 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 54 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 55 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 56 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 57 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 58 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 59 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 60 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 61 #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 62 #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e 63 #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 64 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f 65 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f 66 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 67 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 68 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 69 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 70 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 71 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 72 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 73 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 74 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 75 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 76 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 77 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 78 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 79 #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 80 #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e 81 #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 82 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f 83 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f 84 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 85 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 86 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 87 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 88 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 89 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 90 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 91 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 92 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 93 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 94 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 95 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 96 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 97 #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 98 #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e 99 #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 100 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f 101 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f 102 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 103 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 104 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 105 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 106 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 107 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 108 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 109 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 110 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 111 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 112 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 113 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 114 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 115 #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 116 #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e 117 #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 118 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f 119 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f 120 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 121 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 122 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 123 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 124 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 125 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 126 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 127 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 128 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 129 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 130 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 131 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 132 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 133 #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 134 #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e 135 #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 136 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f 137 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f 138 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 139 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 140 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 141 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 142 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 143 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 144 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 145 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 146 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 147 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 148 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 149 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 150 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 151 #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 152 #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e 153 #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 154 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f 155 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f 156 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 157 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 158 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 159 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 160 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 161 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 162 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 163 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 164 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 165 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 166 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 167 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 168 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 169 #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 170 #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e 171 #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 172 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f 173 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f 174 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 175 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 176 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 177 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 178 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 179 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 180 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 181 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 182 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 183 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 184 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 185 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 186 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 187 #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 188 #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e 189 #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 190 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f 191 #define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff 192 #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 193 #define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff 194 #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 195 #define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff 196 #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 197 #define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff 198 #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 199 #define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff 200 #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 201 #define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff 202 #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 203 #define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff 204 #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 205 #define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff 206 #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 207 #define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff 208 #define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 209 #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 210 #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 211 #define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff 212 #define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 213 #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 214 #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 215 #define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff 216 #define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 217 #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 218 #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 219 #define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff 220 #define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 221 #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 222 #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 223 #define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff 224 #define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 225 #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 226 #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 227 #define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff 228 #define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 229 #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 230 #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 231 #define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff 232 #define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 233 #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 234 #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 235 #define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff 236 #define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 237 #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 238 #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 239 #define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff 240 #define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 241 #define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff 242 #define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 243 #define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff 244 #define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 245 #define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff 246 #define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 247 #define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff 248 #define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 249 #define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff 250 #define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 251 #define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff 252 #define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 253 #define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff 254 #define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 255 #define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff 256 #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 257 #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 258 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd 259 #define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff 260 #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 261 #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 262 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd 263 #define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff 264 #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 265 #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 266 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd 267 #define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff 268 #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 269 #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 270 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd 271 #define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff 272 #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 273 #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 274 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd 275 #define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff 276 #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 277 #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 278 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd 279 #define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff 280 #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 281 #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 282 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd 283 #define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff 284 #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 285 #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 286 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd 287 #define CB_COLOR0_INFO__ENDIAN_MASK 0x3 288 #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 289 #define CB_COLOR0_INFO__FORMAT_MASK 0x7c 290 #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 291 #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 292 #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 293 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 294 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 295 #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 296 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb 297 #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 298 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd 299 #define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 300 #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe 301 #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 302 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf 303 #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 304 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 305 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 306 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 307 #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 308 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 309 #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 310 #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 311 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 312 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 313 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 314 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 315 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 316 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 317 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 318 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 319 #define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000 320 #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c 321 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 322 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 323 #define CB_COLOR1_INFO__ENDIAN_MASK 0x3 324 #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 325 #define CB_COLOR1_INFO__FORMAT_MASK 0x7c 326 #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 327 #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 328 #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 329 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 330 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 331 #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 332 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb 333 #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 334 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd 335 #define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 336 #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe 337 #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 338 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf 339 #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 340 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 341 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 342 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 343 #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 344 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 345 #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 346 #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 347 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 348 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 349 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 350 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 351 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 352 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 353 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 354 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 355 #define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000 356 #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c 357 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 358 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 359 #define CB_COLOR2_INFO__ENDIAN_MASK 0x3 360 #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 361 #define CB_COLOR2_INFO__FORMAT_MASK 0x7c 362 #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 363 #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 364 #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 365 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 366 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 367 #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 368 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb 369 #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 370 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd 371 #define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 372 #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe 373 #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 374 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf 375 #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 376 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 377 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 378 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 379 #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 380 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 381 #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 382 #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 383 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 384 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 385 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 386 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 387 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 388 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 389 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 390 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 391 #define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000 392 #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c 393 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 394 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 395 #define CB_COLOR3_INFO__ENDIAN_MASK 0x3 396 #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 397 #define CB_COLOR3_INFO__FORMAT_MASK 0x7c 398 #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 399 #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 400 #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 401 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 402 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 403 #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 404 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb 405 #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 406 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd 407 #define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 408 #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe 409 #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 410 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf 411 #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 412 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 413 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 414 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 415 #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 416 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 417 #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 418 #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 419 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 420 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 421 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 422 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 423 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 424 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 425 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 426 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 427 #define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000 428 #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c 429 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 430 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 431 #define CB_COLOR4_INFO__ENDIAN_MASK 0x3 432 #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 433 #define CB_COLOR4_INFO__FORMAT_MASK 0x7c 434 #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 435 #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 436 #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 437 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 438 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 439 #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 440 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb 441 #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 442 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd 443 #define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 444 #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe 445 #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 446 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf 447 #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 448 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 449 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 450 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 451 #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 452 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 453 #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 454 #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 455 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 456 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 457 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 458 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 459 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 460 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 461 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 462 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 463 #define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000 464 #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c 465 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 466 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 467 #define CB_COLOR5_INFO__ENDIAN_MASK 0x3 468 #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 469 #define CB_COLOR5_INFO__FORMAT_MASK 0x7c 470 #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 471 #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 472 #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 473 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 474 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 475 #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 476 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb 477 #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 478 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd 479 #define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 480 #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe 481 #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 482 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf 483 #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 484 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 485 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 486 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 487 #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 488 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 489 #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 490 #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 491 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 492 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 493 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 494 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 495 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 496 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 497 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 498 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 499 #define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000 500 #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c 501 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 502 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 503 #define CB_COLOR6_INFO__ENDIAN_MASK 0x3 504 #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 505 #define CB_COLOR6_INFO__FORMAT_MASK 0x7c 506 #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 507 #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 508 #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 509 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 510 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 511 #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 512 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb 513 #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 514 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd 515 #define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 516 #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe 517 #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 518 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf 519 #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 520 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 521 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 522 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 523 #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 524 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 525 #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 526 #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 527 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 528 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 529 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 530 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 531 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 532 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 533 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 534 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 535 #define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000 536 #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c 537 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 538 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 539 #define CB_COLOR7_INFO__ENDIAN_MASK 0x3 540 #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 541 #define CB_COLOR7_INFO__FORMAT_MASK 0x7c 542 #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 543 #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 544 #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 545 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 546 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 547 #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 548 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb 549 #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 550 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd 551 #define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 552 #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe 553 #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 554 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf 555 #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 556 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 557 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 558 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 559 #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 560 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 561 #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 562 #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 563 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 564 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 565 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 566 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 567 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 568 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 569 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 570 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 571 #define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000 572 #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c 573 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 574 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 575 #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 576 #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 577 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 578 #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 579 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 580 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 581 #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 582 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc 583 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 584 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 585 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 586 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 587 #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 588 #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 589 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 590 #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 591 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 592 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 593 #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 594 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc 595 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 596 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 597 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 598 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 599 #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 600 #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 601 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 602 #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 603 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 604 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 605 #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 606 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc 607 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 608 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 609 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 610 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 611 #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 612 #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 613 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 614 #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 615 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 616 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 617 #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 618 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc 619 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 620 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 621 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 622 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 623 #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 624 #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 625 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 626 #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 627 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 628 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 629 #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 630 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc 631 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 632 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 633 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 634 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 635 #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 636 #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 637 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 638 #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 639 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 640 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 641 #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 642 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc 643 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 644 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 645 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 646 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 647 #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 648 #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 649 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 650 #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 651 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 652 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 653 #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 654 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc 655 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 656 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 657 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 658 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 659 #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f 660 #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 661 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 662 #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 663 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 664 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 665 #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 666 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc 667 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 668 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 669 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 670 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 671 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 672 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 673 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 674 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 675 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 676 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 677 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 678 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 679 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 680 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 681 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 682 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 683 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 684 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 685 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 686 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 687 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 688 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 689 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 690 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 691 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 692 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 693 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 694 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 695 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 696 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 697 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 698 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 699 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 700 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 701 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 702 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 703 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 704 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 705 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 706 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 707 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 708 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 709 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 710 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 711 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 712 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 713 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 714 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 715 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 716 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 717 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 718 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 719 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 720 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 721 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 722 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 723 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 724 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 725 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 726 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 727 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 728 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 729 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 730 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 731 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 732 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 733 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 734 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 735 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 736 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 737 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 738 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 739 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 740 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 741 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 742 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 743 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 744 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 745 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 746 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 747 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 748 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 749 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 750 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 751 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 752 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 753 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 754 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 755 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 756 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 757 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 758 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 759 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 760 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 761 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 762 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 763 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 764 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 765 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 766 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 767 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 768 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 769 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 770 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 771 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 772 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 773 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 774 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 775 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 776 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 777 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 778 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 779 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 780 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 781 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 782 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 783 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 784 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 785 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 786 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 787 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 788 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 789 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 790 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 791 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 792 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 793 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 794 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 795 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 796 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 797 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 798 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 799 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 800 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 801 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc 802 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 803 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 804 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 805 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 806 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 807 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 808 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 809 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 810 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 811 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 812 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 813 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 814 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 815 #define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff 816 #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 817 #define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff 818 #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 819 #define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff 820 #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 821 #define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff 822 #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 823 #define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff 824 #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 825 #define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff 826 #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 827 #define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff 828 #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 829 #define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff 830 #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 831 #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff 832 #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 833 #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff 834 #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 835 #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff 836 #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 837 #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff 838 #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 839 #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff 840 #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 841 #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff 842 #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 843 #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff 844 #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 845 #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff 846 #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 847 #define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff 848 #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 849 #define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff 850 #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 851 #define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff 852 #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 853 #define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff 854 #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 855 #define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff 856 #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 857 #define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff 858 #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 859 #define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff 860 #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 861 #define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff 862 #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 863 #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 864 #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 865 #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 866 #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 867 #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 868 #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 869 #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 870 #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 871 #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 872 #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 873 #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 874 #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 875 #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 876 #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 877 #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff 878 #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 879 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 880 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 881 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 882 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 883 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 884 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 885 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 886 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 887 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 888 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 889 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 890 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 891 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 892 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 893 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff 894 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 895 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 896 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 897 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 898 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 899 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 900 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 901 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 902 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 903 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 904 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 905 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 906 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 907 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 908 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 909 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff 910 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 911 #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff 912 #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 913 #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff 914 #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 915 #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff 916 #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 917 #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff 918 #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 919 #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff 920 #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 921 #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff 922 #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 923 #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff 924 #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 925 #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff 926 #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 927 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf 928 #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 929 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 930 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 931 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 932 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 933 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 934 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc 935 #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 936 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 937 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 938 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 939 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 940 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 941 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 942 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c 943 #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf 944 #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 945 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 946 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 947 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 948 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 949 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 950 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc 951 #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 952 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 953 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 954 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 955 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 956 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 957 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 958 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c 959 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf 960 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 961 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 962 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 963 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 964 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc 965 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 966 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 967 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 968 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 969 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 970 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 971 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 972 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 973 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 974 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 975 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 976 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 977 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 978 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 979 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 980 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 981 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 982 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 983 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 984 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a 985 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 986 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b 987 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 988 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c 989 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 990 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 991 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 992 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e 993 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 994 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f 995 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f 996 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 997 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 998 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 999 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 1000 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb 1001 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 1002 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 1003 #define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 1004 #define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a 1005 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff 1006 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 1007 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 1008 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 1009 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 1010 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf 1011 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000 1012 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 1013 #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000 1014 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c 1015 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 1016 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 1017 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2 1018 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 1019 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4 1020 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 1021 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8 1022 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 1023 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10 1024 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 1025 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20 1026 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 1027 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40 1028 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 1029 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80 1030 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 1031 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100 1032 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 1033 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f 1034 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 1035 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20 1036 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 1037 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40 1038 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 1039 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00 1040 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 1041 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000 1042 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 1043 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000 1044 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 1045 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000 1046 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c 1047 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 1048 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 1049 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe 1050 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 1051 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 1052 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 1053 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 1054 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 1055 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 1056 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa 1057 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 1058 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb 1059 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 1060 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc 1061 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 1062 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd 1063 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 1064 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 1065 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 1066 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 1067 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 1068 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 1069 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 1070 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 1071 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff 1072 #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 1073 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 1074 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 1075 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 1076 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 1077 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 1078 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 1079 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 1080 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 1081 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff 1082 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 1083 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 1084 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 1085 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 1086 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 1087 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 1088 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 1089 #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff 1090 #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 1091 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 1092 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 1093 #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff 1094 #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 1095 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 1096 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 1097 #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff 1098 #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 1099 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 1100 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 1101 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 1102 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 1103 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 1104 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 1105 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 1106 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 1107 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 1108 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 1109 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 1110 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 1111 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 1112 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 1113 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 1114 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 1115 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 1116 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 1117 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 1118 #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 1119 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1120 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1121 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 1122 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 1123 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 1124 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 1125 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 1126 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 1127 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 1128 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 1129 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 1130 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 1131 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 1132 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 1133 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 1134 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 1135 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 1136 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 1137 #define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1 1138 #define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0 1139 #define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2 1140 #define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1 1141 #define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4 1142 #define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2 1143 #define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8 1144 #define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3 1145 #define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10 1146 #define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4 1147 #define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20 1148 #define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5 1149 #define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40 1150 #define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6 1151 #define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80 1152 #define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7 1153 #define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100 1154 #define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8 1155 #define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200 1156 #define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9 1157 #define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400 1158 #define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa 1159 #define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800 1160 #define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb 1161 #define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1 1162 #define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0 1163 #define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2 1164 #define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1 1165 #define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4 1166 #define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2 1167 #define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8 1168 #define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3 1169 #define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10 1170 #define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4 1171 #define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20 1172 #define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5 1173 #define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40 1174 #define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6 1175 #define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80 1176 #define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7 1177 #define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100 1178 #define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8 1179 #define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200 1180 #define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9 1181 #define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400 1182 #define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa 1183 #define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800 1184 #define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb 1185 #define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000 1186 #define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc 1187 #define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000 1188 #define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd 1189 #define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000 1190 #define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe 1191 #define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000 1192 #define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf 1193 #define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000 1194 #define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10 1195 #define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000 1196 #define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11 1197 #define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000 1198 #define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12 1199 #define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000 1200 #define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13 1201 #define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000 1202 #define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14 1203 #define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000 1204 #define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15 1205 #define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3 1206 #define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0 1207 #define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4 1208 #define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2 1209 #define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8 1210 #define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3 1211 #define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10 1212 #define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4 1213 #define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20 1214 #define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5 1215 #define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40 1216 #define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6 1217 #define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80 1218 #define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7 1219 #define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100 1220 #define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8 1221 #define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200 1222 #define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9 1223 #define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400 1224 #define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa 1225 #define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800 1226 #define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb 1227 #define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000 1228 #define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc 1229 #define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000 1230 #define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd 1231 #define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000 1232 #define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe 1233 #define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000 1234 #define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf 1235 #define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000 1236 #define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10 1237 #define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000 1238 #define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11 1239 #define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000 1240 #define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12 1241 #define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f 1242 #define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0 1243 #define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0 1244 #define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6 1245 #define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000 1246 #define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc 1247 #define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000 1248 #define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd 1249 #define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000 1250 #define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe 1251 #define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000 1252 #define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10 1253 #define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000 1254 #define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11 1255 #define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000 1256 #define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12 1257 #define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 1258 #define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 1259 #define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 1260 #define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 1261 #define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 1262 #define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 1263 #define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000 1264 #define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17 1265 #define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1 1266 #define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0 1267 #define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2 1268 #define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1 1269 #define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4 1270 #define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2 1271 #define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8 1272 #define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3 1273 #define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10 1274 #define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4 1275 #define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20 1276 #define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5 1277 #define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40 1278 #define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6 1279 #define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80 1280 #define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7 1281 #define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff 1282 #define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0 1283 #define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000 1284 #define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc 1285 #define CP_DFY_CNTL__POLICY_MASK 0x1 1286 #define CP_DFY_CNTL__POLICY__SHIFT 0x0 1287 #define CP_DFY_CNTL__MTYPE_MASK 0xc 1288 #define CP_DFY_CNTL__MTYPE__SHIFT 0x2 1289 #define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000 1290 #define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c 1291 #define CP_DFY_CNTL__MODE_MASK 0x60000000 1292 #define CP_DFY_CNTL__MODE__SHIFT 0x1d 1293 #define CP_DFY_CNTL__ENABLE_MASK 0x80000000 1294 #define CP_DFY_CNTL__ENABLE__SHIFT 0x1f 1295 #define CP_DFY_STAT__BURST_COUNT_MASK 0xffff 1296 #define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 1297 #define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000 1298 #define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 1299 #define CP_DFY_STAT__BUSY_MASK 0x80000000 1300 #define CP_DFY_STAT__BUSY__SHIFT 0x1f 1301 #define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff 1302 #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 1303 #define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 1304 #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 1305 #define CP_DFY_DATA_0__DATA_MASK 0xffffffff 1306 #define CP_DFY_DATA_0__DATA__SHIFT 0x0 1307 #define CP_DFY_DATA_1__DATA_MASK 0xffffffff 1308 #define CP_DFY_DATA_1__DATA__SHIFT 0x0 1309 #define CP_DFY_DATA_2__DATA_MASK 0xffffffff 1310 #define CP_DFY_DATA_2__DATA__SHIFT 0x0 1311 #define CP_DFY_DATA_3__DATA_MASK 0xffffffff 1312 #define CP_DFY_DATA_3__DATA__SHIFT 0x0 1313 #define CP_DFY_DATA_4__DATA_MASK 0xffffffff 1314 #define CP_DFY_DATA_4__DATA__SHIFT 0x0 1315 #define CP_DFY_DATA_5__DATA_MASK 0xffffffff 1316 #define CP_DFY_DATA_5__DATA__SHIFT 0x0 1317 #define CP_DFY_DATA_6__DATA_MASK 0xffffffff 1318 #define CP_DFY_DATA_6__DATA__SHIFT 0x0 1319 #define CP_DFY_DATA_7__DATA_MASK 0xffffffff 1320 #define CP_DFY_DATA_7__DATA__SHIFT 0x0 1321 #define CP_DFY_DATA_8__DATA_MASK 0xffffffff 1322 #define CP_DFY_DATA_8__DATA__SHIFT 0x0 1323 #define CP_DFY_DATA_9__DATA_MASK 0xffffffff 1324 #define CP_DFY_DATA_9__DATA__SHIFT 0x0 1325 #define CP_DFY_DATA_10__DATA_MASK 0xffffffff 1326 #define CP_DFY_DATA_10__DATA__SHIFT 0x0 1327 #define CP_DFY_DATA_11__DATA_MASK 0xffffffff 1328 #define CP_DFY_DATA_11__DATA__SHIFT 0x0 1329 #define CP_DFY_DATA_12__DATA_MASK 0xffffffff 1330 #define CP_DFY_DATA_12__DATA__SHIFT 0x0 1331 #define CP_DFY_DATA_13__DATA_MASK 0xffffffff 1332 #define CP_DFY_DATA_13__DATA__SHIFT 0x0 1333 #define CP_DFY_DATA_14__DATA_MASK 0xffffffff 1334 #define CP_DFY_DATA_14__DATA__SHIFT 0x0 1335 #define CP_DFY_DATA_15__DATA_MASK 0xffffffff 1336 #define CP_DFY_DATA_15__DATA__SHIFT 0x0 1337 #define CP_DFY_CMD__OFFSET_MASK 0x1ff 1338 #define CP_DFY_CMD__OFFSET__SHIFT 0x0 1339 #define CP_DFY_CMD__SIZE_MASK 0xffff0000 1340 #define CP_DFY_CMD__SIZE__SHIFT 0x10 1341 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff 1342 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 1343 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00 1344 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 1345 #define CP_RB0_BASE__RB_BASE_MASK 0xffffffff 1346 #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 1347 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff 1348 #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 1349 #define CP_RB_BASE__RB_BASE_MASK 0xffffffff 1350 #define CP_RB_BASE__RB_BASE__SHIFT 0x0 1351 #define CP_RB1_BASE__RB_BASE_MASK 0xffffffff 1352 #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 1353 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff 1354 #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 1355 #define CP_RB2_BASE__RB_BASE_MASK 0xffffffff 1356 #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 1357 #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f 1358 #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 1359 #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 1360 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 1361 #define CP_RB0_CNTL__MTYPE_MASK 0x18000 1362 #define CP_RB0_CNTL__MTYPE__SHIFT 0xf 1363 #define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000 1364 #define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 1365 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 1366 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 1367 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1368 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1369 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 1370 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 1371 #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 1372 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1373 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1374 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1375 #define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f 1376 #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 1377 #define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 1378 #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 1379 #define CP_RB_CNTL__MTYPE_MASK 0x18000 1380 #define CP_RB_CNTL__MTYPE__SHIFT 0xf 1381 #define CP_RB_CNTL__BUF_SWAP_MASK 0x60000 1382 #define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11 1383 #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 1384 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 1385 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1386 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1387 #define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000 1388 #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 1389 #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 1390 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1391 #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1392 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1393 #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f 1394 #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 1395 #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 1396 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 1397 #define CP_RB1_CNTL__MTYPE_MASK 0x18000 1398 #define CP_RB1_CNTL__MTYPE__SHIFT 0xf 1399 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 1400 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 1401 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1402 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1403 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 1404 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 1405 #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 1406 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1407 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1408 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1409 #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f 1410 #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 1411 #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 1412 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 1413 #define CP_RB2_CNTL__MTYPE_MASK 0x18000 1414 #define CP_RB2_CNTL__MTYPE__SHIFT 0xf 1415 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 1416 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 1417 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 1418 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 1419 #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000 1420 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 1421 #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 1422 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b 1423 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 1424 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 1425 #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff 1426 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 1427 #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1428 #define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1429 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1430 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1431 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1432 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1433 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1434 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1435 #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1436 #define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1437 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1438 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1439 #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 1440 #define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 1441 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc 1442 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 1443 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1444 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1445 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1446 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1447 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1448 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1449 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff 1450 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 1451 #define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff 1452 #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 1453 #define CP_RB_WPTR__RB_WPTR_MASK 0xfffff 1454 #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 1455 #define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff 1456 #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 1457 #define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff 1458 #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 1459 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc 1460 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 1461 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff 1462 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 1463 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 1464 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 1465 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1466 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1467 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1468 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1469 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000 1470 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 1471 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1472 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1473 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1474 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1475 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000 1476 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 1477 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1478 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1479 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1480 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1481 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1482 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1483 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1484 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1485 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1486 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1487 #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1488 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1489 #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1490 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1491 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1492 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1493 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 1494 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 1495 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1496 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1497 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1498 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1499 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000 1500 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 1501 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1502 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1503 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1504 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1505 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000 1506 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 1507 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1508 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1509 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 1510 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 1511 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1512 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1513 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1514 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1515 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1516 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1517 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 1518 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 1519 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 1520 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e 1521 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 1522 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f 1523 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 1524 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 1525 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1526 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1527 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1528 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1529 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000 1530 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 1531 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1532 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1533 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1534 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1535 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000 1536 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 1537 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1538 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1539 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 1540 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 1541 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1542 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1543 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1544 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1545 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1546 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1547 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 1548 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 1549 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 1550 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e 1551 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 1552 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f 1553 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 1554 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 1555 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1556 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1557 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1558 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1559 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000 1560 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 1561 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 1562 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 1563 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 1564 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 1565 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000 1566 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 1567 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 1568 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 1569 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 1570 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 1571 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1572 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1573 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1574 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1575 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1576 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1577 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 1578 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 1579 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 1580 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e 1581 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 1582 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f 1583 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 1584 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 1585 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1586 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1587 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1588 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1589 #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000 1590 #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 1591 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 1592 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 1593 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 1594 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1595 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 1596 #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 1597 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 1598 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 1599 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 1600 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 1601 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1602 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1603 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 1604 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a 1605 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1606 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1607 #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 1608 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 1609 #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 1610 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e 1611 #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 1612 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f 1613 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 1614 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 1615 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1616 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1617 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1618 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1619 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000 1620 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 1621 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000 1622 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 1623 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 1624 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1625 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000 1626 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 1627 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 1628 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 1629 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 1630 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 1631 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1632 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1633 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 1634 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a 1635 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1636 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1637 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 1638 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 1639 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 1640 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e 1641 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 1642 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f 1643 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 1644 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 1645 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1646 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1647 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1648 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1649 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000 1650 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 1651 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 1652 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 1653 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 1654 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1655 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000 1656 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 1657 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 1658 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 1659 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 1660 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 1661 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1662 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1663 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 1664 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a 1665 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1666 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1667 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 1668 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 1669 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 1670 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e 1671 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 1672 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f 1673 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 1674 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 1675 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 1676 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 1677 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 1678 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 1679 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000 1680 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 1681 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 1682 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 1683 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 1684 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 1685 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000 1686 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 1687 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 1688 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 1689 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 1690 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 1691 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 1692 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 1693 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 1694 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a 1695 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 1696 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 1697 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 1698 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 1699 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 1700 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e 1701 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 1702 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f 1703 #define CP_DEVICE_ID__DEVICE_ID_MASK 0xff 1704 #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 1705 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1706 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1707 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1708 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1709 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1710 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1711 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1712 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1713 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 1714 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 1715 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 1716 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 1717 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 1718 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 1719 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 1720 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 1721 #define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 1722 #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 1723 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 1724 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 1725 #define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 1726 #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 1727 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 1728 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 1729 #define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 1730 #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 1731 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 1732 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 1733 #define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 1734 #define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 1735 #define CP_RB_VMID__RB0_VMID_MASK 0xf 1736 #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 1737 #define CP_RB_VMID__RB1_VMID_MASK 0xf00 1738 #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 1739 #define CP_RB_VMID__RB2_VMID_MASK 0xf0000 1740 #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 1741 #define CP_ME0_PIPE0_VMID__VMID_MASK 0xf 1742 #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 1743 #define CP_ME0_PIPE1_VMID__VMID_MASK 0xf 1744 #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 1745 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc 1746 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 1747 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 1748 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e 1749 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 1750 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f 1751 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc 1752 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 1753 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc 1754 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 1755 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc 1756 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 1757 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc 1758 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 1759 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff 1760 #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1761 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1762 #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1763 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff 1764 #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 1765 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff 1766 #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 1767 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff 1768 #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 1769 #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf 1770 #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 1771 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1772 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1773 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 1774 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1775 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1776 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1777 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1778 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1779 #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf 1780 #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 1781 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1782 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1783 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 1784 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1785 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1786 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1787 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1788 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1789 #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf 1790 #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 1791 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 1792 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1793 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 1794 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 1795 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 1796 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 1797 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 1798 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 1799 #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 1800 #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1801 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1802 #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1803 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff 1804 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1805 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1806 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1807 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff 1808 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 1809 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 1810 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 1811 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1812 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1813 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1814 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1815 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 1816 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 1817 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 1818 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 1819 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 1820 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 1821 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 1822 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 1823 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 1824 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 1825 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 1826 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 1827 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 1828 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 1829 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 1830 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 1831 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 1832 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 1833 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 1834 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 1835 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 1836 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 1837 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 1838 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 1839 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 1840 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 1841 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 1842 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 1843 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 1844 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 1845 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 1846 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 1847 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 1848 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 1849 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 1850 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 1851 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 1852 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 1853 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 1854 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 1855 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 1856 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 1857 #define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff 1858 #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 1859 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 1860 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 1861 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 1862 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 1863 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100 1864 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 1865 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200 1866 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 1867 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 1868 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa 1869 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800 1870 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb 1871 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 1872 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 1873 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000 1874 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 1875 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 1876 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 1877 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 1878 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 1879 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 1880 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 1881 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 1882 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 1883 #define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c 1884 #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 1885 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80 1886 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 1887 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 1888 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 1889 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 1890 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 1891 #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 1892 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 1893 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 1894 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 1895 #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0 1896 #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 1897 #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300 1898 #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 1899 #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00 1900 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa 1901 #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000 1902 #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc 1903 #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 1904 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 1905 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff 1906 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 1907 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff 1908 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 1909 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff 1910 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 1911 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff 1912 #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 1913 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 1914 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e 1915 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 1916 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f 1917 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff 1918 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 1919 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 1920 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 1921 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1922 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1923 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1924 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1925 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 1926 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 1927 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1928 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1929 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1930 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1931 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1932 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1933 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1934 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1935 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1936 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1937 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1938 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1939 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1940 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1941 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1942 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1943 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 1944 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 1945 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1946 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1947 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1948 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1949 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 1950 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 1951 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1952 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1953 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1954 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1955 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1956 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1957 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1958 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1959 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1960 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1961 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1962 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1963 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1964 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1965 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1966 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1967 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 1968 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 1969 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1970 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1971 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1972 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1973 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 1974 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 1975 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 1976 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 1977 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 1978 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 1979 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 1980 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 1981 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1982 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 1983 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 1984 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 1985 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 1986 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 1987 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 1988 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 1989 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 1990 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 1991 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 1992 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 1993 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 1994 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 1995 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 1996 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 1997 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 1998 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 1999 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2000 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2001 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2002 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2003 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2004 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2005 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2006 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2007 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2008 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2009 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2010 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2011 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2012 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2013 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2014 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2015 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 2016 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 2017 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 2018 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 2019 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 2020 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 2021 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 2022 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 2023 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2024 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2025 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2026 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2027 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2028 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2029 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2030 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2031 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2032 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2033 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2034 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2035 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2036 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2037 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2038 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2039 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 2040 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 2041 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 2042 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 2043 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 2044 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 2045 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 2046 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 2047 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2048 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2049 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2050 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2051 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2052 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2053 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2054 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2055 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2056 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2057 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2058 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2059 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2060 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2061 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2062 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2063 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 2064 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 2065 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 2066 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 2067 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 2068 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 2069 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 2070 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 2071 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2072 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2073 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2074 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2075 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2076 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2077 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2078 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2079 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2080 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2081 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2082 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2083 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2084 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2085 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2086 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2087 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 2088 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 2089 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 2090 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 2091 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 2092 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 2093 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 2094 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 2095 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2096 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2097 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2098 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2099 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2100 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2101 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2102 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2103 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2104 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2105 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2106 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2107 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2108 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2109 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2110 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2111 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 2112 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 2113 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 2114 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 2115 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 2116 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 2117 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 2118 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 2119 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 2120 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 2121 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 2122 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 2123 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 2124 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 2125 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 2126 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 2127 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 2128 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 2129 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 2130 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 2131 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 2132 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 2133 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 2134 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 2135 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2136 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2137 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2138 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2139 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2140 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2141 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2142 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2143 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2144 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2145 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2146 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2147 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2148 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2149 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2150 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2151 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2152 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2153 #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2154 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2155 #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2156 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2157 #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2158 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2159 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2160 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2161 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2162 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2163 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2164 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2165 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2166 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2167 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2168 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2169 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2170 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2171 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2172 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2173 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2174 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2175 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2176 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2177 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2178 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2179 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2180 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2181 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2182 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2183 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2184 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2185 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2186 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2187 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2188 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2189 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2190 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2191 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2192 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2193 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2194 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2195 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2196 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2197 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2198 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2199 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2200 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2201 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2202 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2203 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2204 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2205 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2206 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2207 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2208 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2209 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2210 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2211 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2212 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2213 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2214 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2215 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2216 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2217 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2218 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2219 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2220 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2221 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2222 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2223 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2224 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2225 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2226 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2227 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2228 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2229 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2230 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2231 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2232 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2233 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2234 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2235 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2236 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2237 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2238 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2239 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2240 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2241 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2242 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2243 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2244 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2245 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2246 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2247 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2248 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2249 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2250 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2251 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2252 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2253 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2254 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2255 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2256 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2257 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2258 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2259 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2260 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2261 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2262 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2263 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2264 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2265 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2266 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2267 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2268 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2269 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2270 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2271 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2272 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2273 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2274 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2275 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2276 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2277 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2278 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2279 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2280 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2281 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2282 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2283 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2284 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2285 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2286 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2287 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2288 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2289 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2290 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2291 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2292 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2293 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2294 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2295 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2296 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2297 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2298 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2299 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2300 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2301 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2302 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2303 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2304 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2305 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2306 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2307 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2308 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2309 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2310 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2311 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2312 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2313 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2314 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2315 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2316 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2317 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2318 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2319 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2320 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2321 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2322 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2323 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2324 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2325 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2326 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2327 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 2328 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 2329 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 2330 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 2331 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 2332 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 2333 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2334 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2335 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 2336 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 2337 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 2338 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 2339 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 2340 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 2341 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 2342 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 2343 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 2344 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 2345 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 2346 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 2347 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 2348 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 2349 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 2350 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 2351 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 2352 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc 2353 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 2354 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd 2355 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 2356 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 2357 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2358 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2359 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 2360 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 2361 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 2362 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 2363 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 2364 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 2365 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 2366 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 2367 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 2368 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 2369 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 2370 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2371 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 2372 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 2373 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 2374 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 2375 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 2376 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc 2377 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 2378 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd 2379 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 2380 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 2381 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 2382 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 2383 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 2384 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 2385 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 2386 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 2387 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 2388 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 2389 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 2390 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 2391 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 2392 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 2393 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 2394 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 2395 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 2396 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 2397 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 2398 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 2399 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 2400 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 2401 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 2402 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 2403 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 2404 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 2405 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 2406 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 2407 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 2408 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 2409 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 2410 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 2411 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 2412 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 2413 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 2414 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 2415 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff 2416 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 2417 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 2418 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 2419 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 2420 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 2421 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 2422 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 2423 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 2424 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 2425 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 2426 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 2427 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 2428 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 2429 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 2430 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 2431 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff 2432 #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 2433 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff 2434 #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 2435 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff 2436 #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 2437 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff 2438 #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 2439 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff 2440 #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 2441 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff 2442 #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 2443 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff 2444 #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 2445 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff 2446 #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 2447 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff 2448 #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 2449 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff 2450 #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 2451 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 2452 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 2453 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 2454 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 2455 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 2456 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 2457 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 2458 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 2459 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 2460 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 2461 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff 2462 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 2463 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 2464 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 2465 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 2466 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 2467 #define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 2468 #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 2469 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff 2470 #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 2471 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 2472 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 2473 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 2474 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 2475 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 2476 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 2477 #define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff 2478 #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 2479 #define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 2480 #define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 2481 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff 2482 #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 2483 #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000 2484 #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 2485 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff 2486 #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 2487 #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000 2488 #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 2489 #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff 2490 #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 2491 #define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000 2492 #define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c 2493 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 2494 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 2495 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 2496 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 2497 #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000 2498 #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc 2499 #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff 2500 #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 2501 #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf 2502 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 2503 #define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000 2504 #define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17 2505 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000 2506 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 2507 #define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000 2508 #define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b 2509 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1 2510 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 2511 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10 2512 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 2513 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20 2514 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 2515 #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 2516 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 2517 #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 2518 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 2519 #define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 2520 #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 2521 #define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 2522 #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 2523 #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 2524 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 2525 #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 2526 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 2527 #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 2528 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 2529 #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 2530 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 2531 #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 2532 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa 2533 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 2534 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb 2535 #define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 2536 #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc 2537 #define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000 2538 #define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd 2539 #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 2540 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 2541 #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 2542 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e 2543 #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 2544 #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f 2545 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 2546 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 2547 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 2548 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 2549 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 2550 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 2551 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 2552 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 2553 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 2554 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 2555 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 2556 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 2557 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 2558 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 2559 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 2560 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 2561 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 2562 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 2563 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 2564 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 2565 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 2566 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa 2567 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 2568 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb 2569 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 2570 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc 2571 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 2572 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd 2573 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 2574 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 2575 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 2576 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 2577 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 2578 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 2579 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 2580 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 2581 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 2582 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 2583 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 2584 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 2585 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 2586 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 2587 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 2588 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 2589 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 2590 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 2591 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 2592 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 2593 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 2594 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a 2595 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 2596 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b 2597 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 2598 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c 2599 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 2600 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 2601 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 2602 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 2603 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 2604 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 2605 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 2606 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 2607 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 2608 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 2609 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 2610 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 2611 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 2612 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa 2613 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 2614 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd 2615 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 2616 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 2617 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 2618 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 2619 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 2620 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 2621 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 2622 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 2623 #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000 2624 #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16 2625 #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000 2626 #define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17 2627 #define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000 2628 #define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18 2629 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 2630 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 2631 #define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 2632 #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 2633 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 2634 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 2635 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 2636 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 2637 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 2638 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 2639 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 2640 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 2641 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 2642 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 2643 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 2644 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 2645 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 2646 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa 2647 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 2648 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb 2649 #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 2650 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc 2651 #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 2652 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd 2653 #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 2654 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe 2655 #define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 2656 #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf 2657 #define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000 2658 #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 2659 #define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000 2660 #define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11 2661 #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000 2662 #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a 2663 #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000 2664 #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b 2665 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000 2666 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c 2667 #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 2668 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e 2669 #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 2670 #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f 2671 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 2672 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 2673 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 2674 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 2675 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 2676 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 2677 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 2678 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 2679 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 2680 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 2681 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 2682 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 2683 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 2684 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 2685 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 2686 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 2687 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 2688 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 2689 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 2690 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 2691 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 2692 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb 2693 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 2694 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc 2695 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 2696 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd 2697 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 2698 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe 2699 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 2700 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf 2701 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 2702 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 2703 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 2704 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 2705 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 2706 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 2707 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 2708 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 2709 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 2710 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 2711 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 2712 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 2713 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 2714 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 2715 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 2716 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 2717 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 2718 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 2719 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 2720 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 2721 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 2722 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a 2723 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 2724 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b 2725 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 2726 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c 2727 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 2728 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 2729 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 2730 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e 2731 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 2732 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f 2733 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 2734 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 2735 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 2736 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 2737 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 2738 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 2739 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 2740 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 2741 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 2742 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 2743 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 2744 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 2745 #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80 2746 #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7 2747 #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100 2748 #define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8 2749 #define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200 2750 #define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9 2751 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f 2752 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 2753 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 2754 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 2755 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 2756 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 2757 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000 2758 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 2759 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000 2760 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 2761 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000 2762 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 2763 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 2764 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 2765 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000 2766 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 2767 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 2768 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c 2769 #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 2770 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 2771 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 2772 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e 2773 #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 2774 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f 2775 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff 2776 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 2777 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff 2778 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 2779 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff 2780 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 2781 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff 2782 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 2783 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2784 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2785 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2786 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2787 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2788 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2789 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2790 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2791 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2792 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2793 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2794 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2795 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2796 #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2797 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2798 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2799 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2800 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2801 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2802 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2803 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2804 #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2805 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2806 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2807 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2808 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2809 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2810 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2811 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2812 #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2813 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2814 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2815 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2816 #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2817 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2818 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2819 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2820 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2821 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2822 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2823 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 2824 #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 2825 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 2826 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 2827 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 2828 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 2829 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f 2830 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 2831 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 2832 #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 2833 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 2834 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 2835 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 2836 #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 2837 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 2838 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 2839 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 2840 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 2841 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 2842 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 2843 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf 2844 #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 2845 #define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff 2846 #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 2847 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff 2848 #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 2849 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff 2850 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 2851 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff 2852 #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 2853 #define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff 2854 #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 2855 #define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 2856 #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 2857 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 2858 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 2859 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 2860 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 2861 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 2862 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 2863 #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 2864 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 2865 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff 2866 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 2867 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff 2868 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 2869 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 2870 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 2871 #define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc 2872 #define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 2873 #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 2874 #define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa 2875 #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 2876 #define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 2877 #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 2878 #define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 2879 #define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 2880 #define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 2881 #define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000 2882 #define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c 2883 #define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000 2884 #define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e 2885 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff 2886 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 2887 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff 2888 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 2889 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff 2890 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 2891 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff 2892 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 2893 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff 2894 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 2895 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f 2896 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 2897 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 2898 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc 2899 #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000 2900 #define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 2901 #define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000 2902 #define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b 2903 #define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff 2904 #define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 2905 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 2906 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 2907 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 2908 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 2909 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 2910 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 2911 #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff 2912 #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 2913 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc 2914 #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 2915 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff 2916 #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 2917 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff 2918 #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 2919 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff 2920 #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 2921 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff 2922 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 2923 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff 2924 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 2925 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc 2926 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 2927 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff 2928 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 2929 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff 2930 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 2931 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff 2932 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 2933 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff 2934 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 2935 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff 2936 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 2937 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff 2938 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 2939 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff 2940 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 2941 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff 2942 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 2943 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff 2944 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 2945 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff 2946 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 2947 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff 2948 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 2949 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff 2950 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 2951 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff 2952 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 2953 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff 2954 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 2955 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff 2956 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 2957 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff 2958 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 2959 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff 2960 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 2961 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc 2962 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 2963 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff 2964 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 2965 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff 2966 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 2967 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff 2968 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 2969 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff 2970 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 2971 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff 2972 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 2973 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff 2974 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 2975 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff 2976 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 2977 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff 2978 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 2979 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff 2980 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 2981 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff 2982 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 2983 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff 2984 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 2985 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff 2986 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 2987 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff 2988 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 2989 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff 2990 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 2991 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff 2992 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 2993 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff 2994 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 2995 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff 2996 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 2997 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff 2998 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 2999 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff 3000 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 3001 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff 3002 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 3003 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff 3004 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 3005 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff 3006 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 3007 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff 3008 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 3009 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff 3010 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 3011 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff 3012 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 3013 #define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000 3014 #define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19 3015 #define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000 3016 #define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b 3017 #define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000 3018 #define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19 3019 #define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000 3020 #define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b 3021 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 3022 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 3023 #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff 3024 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 3025 #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff 3026 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 3027 #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff 3028 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 3029 #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff 3030 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 3031 #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff 3032 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 3033 #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff 3034 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 3035 #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff 3036 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 3037 #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff 3038 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 3039 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff 3040 #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 3041 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 3042 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 3043 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff 3044 #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 3045 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 3046 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 3047 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 3048 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 3049 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 3050 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 3051 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 3052 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 3053 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 3054 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 3055 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 3056 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 3057 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc 3058 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 3059 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff 3060 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 3061 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 3062 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 3063 #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000 3064 #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 3065 #define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000 3066 #define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b 3067 #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 3068 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 3069 #define CP_APPEND_DATA__DATA_MASK 0xffffffff 3070 #define CP_APPEND_DATA__DATA__SHIFT 0x0 3071 #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff 3072 #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 3073 #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff 3074 #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 3075 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 3076 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 3077 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff 3078 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 3079 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 3080 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 3081 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff 3082 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 3083 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 3084 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 3085 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff 3086 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 3087 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 3088 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 3089 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff 3090 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 3091 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 3092 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 3093 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff 3094 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 3095 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 3096 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 3097 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff 3098 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 3099 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 3100 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 3101 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc 3102 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 3103 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff 3104 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 3105 #define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000 3106 #define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14 3107 #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000 3108 #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 3109 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff 3110 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 3111 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff 3112 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 3113 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 3114 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 3115 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc 3116 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 3117 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff 3118 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 3119 #define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000 3120 #define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14 3121 #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000 3122 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 3123 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff 3124 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 3125 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 3126 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 3127 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 3128 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 3129 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff 3130 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 3131 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 3132 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 3133 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 3134 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 3135 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 3136 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 3137 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 3138 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3139 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 3140 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 3141 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 3142 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 3143 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff 3144 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 3145 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 3146 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 3147 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 3148 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 3149 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 3150 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 3151 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 3152 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 3153 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff 3154 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 3155 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f 3156 #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 3157 #define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 3158 #define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 3159 #define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 3160 #define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 3161 #define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4 3162 #define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2 3163 #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8 3164 #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 3165 #define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 3166 #define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 3167 #define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 3168 #define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 3169 #define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 3170 #define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 3171 #define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 3172 #define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 3173 #define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 3174 #define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa 3175 #define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 3176 #define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb 3177 #define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 3178 #define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc 3179 #define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 3180 #define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd 3181 #define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 3182 #define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe 3183 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 3184 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf 3185 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 3186 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 3187 #define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 3188 #define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 3189 #define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 3190 #define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 3191 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 3192 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 3193 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 3194 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 3195 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 3196 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 3197 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 3198 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a 3199 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 3200 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b 3201 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 3202 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c 3203 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 3204 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 3205 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000 3206 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e 3207 #define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000 3208 #define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f 3209 #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff 3210 #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 3211 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff 3212 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 3213 #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff 3214 #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 3215 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff 3216 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 3217 #define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff 3218 #define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 3219 #define CP_COHER_STATUS__MEID_MASK 0x3000000 3220 #define CP_COHER_STATUS__MEID__SHIFT 0x18 3221 #define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 3222 #define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e 3223 #define CP_COHER_STATUS__STATUS_MASK 0x80000000 3224 #define CP_COHER_STATUS__STATUS__SHIFT 0x1f 3225 #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff 3226 #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 3227 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff 3228 #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 3229 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff 3230 #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 3231 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff 3232 #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 3233 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff 3234 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 3235 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff 3236 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 3237 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff 3238 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 3239 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff 3240 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 3241 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff 3242 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 3243 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff 3244 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 3245 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff 3246 #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 3247 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff 3248 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 3249 #define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00 3250 #define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa 3251 #define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 3252 #define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc 3253 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 3254 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 3255 #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 3256 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 3257 #define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000 3258 #define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16 3259 #define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 3260 #define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 3261 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 3262 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 3263 #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 3264 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 3265 #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff 3266 #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 3267 #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 3268 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 3269 #define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 3270 #define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 3271 #define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 3272 #define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 3273 #define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 3274 #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a 3275 #define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 3276 #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b 3277 #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 3278 #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c 3279 #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 3280 #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 3281 #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 3282 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e 3283 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff 3284 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 3285 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff 3286 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 3287 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff 3288 #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 3289 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff 3290 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 3291 #define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00 3292 #define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa 3293 #define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 3294 #define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc 3295 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 3296 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 3297 #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 3298 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 3299 #define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000 3300 #define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16 3301 #define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 3302 #define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 3303 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 3304 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 3305 #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 3306 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 3307 #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff 3308 #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 3309 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 3310 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 3311 #define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 3312 #define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 3313 #define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 3314 #define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 3315 #define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 3316 #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a 3317 #define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 3318 #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b 3319 #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 3320 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c 3321 #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 3322 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 3323 #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 3324 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e 3325 #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 3326 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 3327 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 3328 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 3329 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 3330 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c 3331 #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 3332 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 3333 #define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 3334 #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e 3335 #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff 3336 #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 3337 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 3338 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c 3339 #define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff 3340 #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 3341 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 3342 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 3343 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 3344 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 3345 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 3346 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 3347 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 3348 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 3349 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff 3350 #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 3351 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff 3352 #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 3353 #define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff 3354 #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 3355 #define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff 3356 #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 3357 #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff 3358 #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 3359 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff 3360 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 3361 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff 3362 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 3363 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff 3364 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 3365 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff 3366 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 3367 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff 3368 #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 3369 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff 3370 #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 3371 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff 3372 #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 3373 #define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff 3374 #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 3375 #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3 3376 #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 3377 #define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3 3378 #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 3379 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1 3380 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 3381 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff 3382 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 3383 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff 3384 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 3385 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff 3386 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 3387 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff 3388 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 3389 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff 3390 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 3391 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff 3392 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 3393 #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff 3394 #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 3395 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff 3396 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 3397 #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff 3398 #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 3399 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff 3400 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 3401 #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3 3402 #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 3403 #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff 3404 #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 3405 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff 3406 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 3407 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1 3408 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 3409 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2 3410 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 3411 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4 3412 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 3413 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8 3414 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 3415 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10 3416 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 3417 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20 3418 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 3419 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40 3420 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 3421 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80 3422 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 3423 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 3424 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 3425 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 3426 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 3427 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 3428 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 3429 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 3430 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa 3431 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 3432 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb 3433 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 3434 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc 3435 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 3436 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd 3437 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000 3438 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe 3439 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 3440 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf 3441 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 3442 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 3443 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 3444 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 3445 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 3446 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 3447 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 3448 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a 3449 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 3450 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b 3451 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 3452 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c 3453 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 3454 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 3455 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 3456 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 3457 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 3458 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 3459 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 3460 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 3461 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 3462 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 3463 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 3464 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 3465 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 3466 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 3467 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 3468 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 3469 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 3470 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa 3471 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 3472 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb 3473 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 3474 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc 3475 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 3476 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd 3477 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 3478 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe 3479 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 3480 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf 3481 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 3482 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 3483 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 3484 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 3485 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 3486 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 3487 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 3488 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 3489 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 3490 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 3491 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 3492 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 3493 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 3494 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 3495 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 3496 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 3497 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 3498 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 3499 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 3500 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 3501 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 3502 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a 3503 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 3504 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b 3505 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 3506 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c 3507 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 3508 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 3509 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 3510 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e 3511 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 3512 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f 3513 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 3514 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 3515 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 3516 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 3517 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 3518 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 3519 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 3520 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 3521 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 3522 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 3523 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 3524 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 3525 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 3526 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 3527 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 3528 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 3529 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 3530 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa 3531 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 3532 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb 3533 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 3534 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc 3535 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 3536 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd 3537 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 3538 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe 3539 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 3540 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf 3541 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000 3542 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 3543 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000 3544 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 3545 #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000 3546 #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12 3547 #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000 3548 #define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13 3549 #define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000 3550 #define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14 3551 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 3552 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 3553 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 3554 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 3555 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 3556 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 3557 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 3558 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 3559 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 3560 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 3561 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 3562 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa 3563 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 3564 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc 3565 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 3566 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd 3567 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 3568 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe 3569 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 3570 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf 3571 #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 3572 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 3573 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 3574 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 3575 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 3576 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 3577 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 3578 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 3579 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 3580 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 3581 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 3582 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 3583 #define CP_STAT__ROQ_RING_BUSY_MASK 0x200 3584 #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 3585 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 3586 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa 3587 #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 3588 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb 3589 #define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 3590 #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc 3591 #define CP_STAT__DC_BUSY_MASK 0x2000 3592 #define CP_STAT__DC_BUSY__SHIFT 0xd 3593 #define CP_STAT__ATCL2IU_BUSY_MASK 0x4000 3594 #define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe 3595 #define CP_STAT__PFP_BUSY_MASK 0x8000 3596 #define CP_STAT__PFP_BUSY__SHIFT 0xf 3597 #define CP_STAT__MEQ_BUSY_MASK 0x10000 3598 #define CP_STAT__MEQ_BUSY__SHIFT 0x10 3599 #define CP_STAT__ME_BUSY_MASK 0x20000 3600 #define CP_STAT__ME_BUSY__SHIFT 0x11 3601 #define CP_STAT__QUERY_BUSY_MASK 0x40000 3602 #define CP_STAT__QUERY_BUSY__SHIFT 0x12 3603 #define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 3604 #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 3605 #define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 3606 #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 3607 #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 3608 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 3609 #define CP_STAT__DMA_BUSY_MASK 0x400000 3610 #define CP_STAT__DMA_BUSY__SHIFT 0x16 3611 #define CP_STAT__RCIU_BUSY_MASK 0x800000 3612 #define CP_STAT__RCIU_BUSY__SHIFT 0x17 3613 #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 3614 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 3615 #define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 3616 #define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 3617 #define CP_STAT__CE_BUSY_MASK 0x4000000 3618 #define CP_STAT__CE_BUSY__SHIFT 0x1a 3619 #define CP_STAT__TCIU_BUSY_MASK 0x8000000 3620 #define CP_STAT__TCIU_BUSY__SHIFT 0x1b 3621 #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 3622 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c 3623 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 3624 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 3625 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 3626 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e 3627 #define CP_STAT__CP_BUSY_MASK 0x80000000 3628 #define CP_STAT__CP_BUSY__SHIFT 0x1f 3629 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff 3630 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 3631 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff 3632 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 3633 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f 3634 #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 3635 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 3636 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 3637 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 3638 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 3639 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff 3640 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 3641 #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf 3642 #define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 3643 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00 3644 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 3645 #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf 3646 #define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 3647 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 3648 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 3649 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 3650 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 3651 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 3652 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 3653 #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000 3654 #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 3655 #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000 3656 #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 3657 #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000 3658 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 3659 #define CP_ME_CNTL__CE_HALT_MASK 0x1000000 3660 #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 3661 #define CP_ME_CNTL__CE_STEP_MASK 0x2000000 3662 #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 3663 #define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 3664 #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a 3665 #define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 3666 #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b 3667 #define CP_ME_CNTL__ME_HALT_MASK 0x10000000 3668 #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c 3669 #define CP_ME_CNTL__ME_STEP_MASK 0x20000000 3670 #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 3671 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff 3672 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 3673 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 3674 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 3675 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 3676 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 3677 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 3678 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c 3679 #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1 3680 #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 3681 #define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff 3682 #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 3683 #define CP_RB_RPTR__RB_RPTR_MASK 0xfffff 3684 #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 3685 #define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff 3686 #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 3687 #define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff 3688 #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 3689 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff 3690 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 3691 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 3692 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c 3693 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff 3694 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 3695 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 3696 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3697 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 3698 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 3699 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff 3700 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 3701 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff 3702 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 3703 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc 3704 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 3705 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff 3706 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 3707 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff 3708 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 3709 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc 3710 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 3711 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff 3712 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 3713 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff 3714 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 3715 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc 3716 #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 3717 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff 3718 #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 3719 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff 3720 #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 3721 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc 3722 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 3723 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff 3724 #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 3725 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff 3726 #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 3727 #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc 3728 #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 3729 #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff 3730 #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 3731 #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff 3732 #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 3733 #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff 3734 #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 3735 #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 3736 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 3737 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff 3738 #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 3739 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff 3740 #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 3741 #define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 3742 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 3743 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 3744 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 3745 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 3746 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 3747 #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff 3748 #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 3749 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 3750 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 3751 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 3752 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 3753 #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 3754 #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 3755 #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff 3756 #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 3757 #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 3758 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 3759 #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 3760 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 3761 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f 3762 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 3763 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 3764 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 3765 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff 3766 #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 3767 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 3768 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 3769 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff 3770 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 3771 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 3772 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 3773 #define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff 3774 #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 3775 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff 3776 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 3777 #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff 3778 #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 3779 #define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff 3780 #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 3781 #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 3782 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc 3783 #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000 3784 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 3785 #define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff 3786 #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 3787 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff 3788 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 3789 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 3790 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 3791 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff 3792 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 3793 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 3794 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 3795 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff 3796 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 3797 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 3798 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 3799 #define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff 3800 #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 3801 #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff 3802 #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 3803 #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff 3804 #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 3805 #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 3806 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 3807 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff 3808 #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 3809 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 3810 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 3811 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff 3812 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 3813 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff 3814 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 3815 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 3816 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 3817 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff 3818 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 3819 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 3820 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 3821 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff 3822 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 3823 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 3824 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 3825 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800 3826 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb 3827 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 3828 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe 3829 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 3830 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 3831 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000 3832 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 3833 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 3834 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 3835 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 3836 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 3837 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000 3838 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 3839 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 3840 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 3841 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 3842 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 3843 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 3844 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 3845 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 3846 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a 3847 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 3848 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b 3849 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 3850 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d 3851 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 3852 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e 3853 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 3854 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f 3855 #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 3856 #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 3857 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 3858 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 3859 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 3860 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 3861 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 3862 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 3863 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 3864 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f 3865 #define CP_RINGID__RINGID_MASK 0x3 3866 #define CP_RINGID__RINGID__SHIFT 0x0 3867 #define CP_PIPEID__PIPE_ID_MASK 0x3 3868 #define CP_PIPEID__PIPE_ID__SHIFT 0x0 3869 #define CP_VMID__VMID_MASK 0xf 3870 #define CP_VMID__VMID__SHIFT 0x0 3871 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 3872 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 3873 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 3874 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 3875 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 3876 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 3877 #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f 3878 #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 3879 #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0 3880 #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 3881 #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00 3882 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 3883 #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc 3884 #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 3885 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff 3886 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 3887 #define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 3888 #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 3889 #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2 3890 #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 3891 #define CP_HQD_VMID__VMID_MASK 0xf 3892 #define CP_HQD_VMID__VMID__SHIFT 0x0 3893 #define CP_HQD_VMID__IB_VMID_MASK 0xf00 3894 #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 3895 #define CP_HQD_VMID__VQID_MASK 0x3ff0000 3896 #define CP_HQD_VMID__VQID__SHIFT 0x10 3897 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 3898 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 3899 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 3900 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 3901 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000 3902 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c 3903 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000 3904 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d 3905 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000 3906 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e 3907 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 3908 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f 3909 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 3910 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 3911 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf 3912 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 3913 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 3914 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 3915 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 3916 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 3917 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 3918 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 3919 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000 3920 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f 3921 #define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff 3922 #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 3923 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff 3924 #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 3925 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff 3926 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 3927 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc 3928 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 3929 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff 3930 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 3931 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc 3932 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 3933 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff 3934 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 3935 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1 3936 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 3937 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2 3938 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 3939 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc 3940 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 3941 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000 3942 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17 3943 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 3944 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c 3945 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 3946 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 3947 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 3948 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e 3949 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 3950 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f 3951 #define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff 3952 #define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 3953 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f 3954 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 3955 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 3956 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 3957 #define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000 3958 #define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf 3959 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000 3960 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 3961 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 3962 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 3963 #define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 3964 #define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 3965 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000 3966 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 3967 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 3968 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 3969 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 3970 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b 3971 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 3972 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c 3973 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 3974 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 3975 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 3976 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e 3977 #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 3978 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f 3979 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc 3980 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 3981 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff 3982 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 3983 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff 3984 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 3985 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff 3986 #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 3987 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 3988 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 3989 #define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 3990 #define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 3991 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000 3992 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 3993 #define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000 3994 #define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b 3995 #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 3996 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f 3997 #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff 3998 #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 3999 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 4000 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 4001 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800 4002 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb 4003 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 4004 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc 4005 #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000 4006 #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe 4007 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 4008 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 4009 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 4010 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 4011 #define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 4012 #define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 4013 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000 4014 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 4015 #define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000 4016 #define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b 4017 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 4018 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 4019 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 4020 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e 4021 #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 4022 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f 4023 #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f 4024 #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 4025 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7 4026 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 4027 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 4028 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 4029 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 4030 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 4031 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200 4032 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 4033 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400 4034 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa 4035 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 4036 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 4037 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1 4038 #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 4039 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2 4040 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 4041 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10 4042 #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 4043 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20 4044 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 4045 #define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 4046 #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 4047 #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 4048 #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 4049 #define CP_HQD_MSG_TYPE__ACTION_MASK 0x7 4050 #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 4051 #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70 4052 #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 4053 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff 4054 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 4055 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff 4056 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 4057 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff 4058 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 4059 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff 4060 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 4061 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff 4062 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 4063 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3 4064 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 4065 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc 4066 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 4067 #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70 4068 #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 4069 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80 4070 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 4071 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100 4072 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 4073 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200 4074 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 4075 #define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00 4076 #define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa 4077 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff 4078 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 4079 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff 4080 #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 4081 #define CP_MQD_CONTROL__VMID_MASK 0xf 4082 #define CP_MQD_CONTROL__VMID__SHIFT 0x0 4083 #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000 4084 #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc 4085 #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000 4086 #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd 4087 #define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 4088 #define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 4089 #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000 4090 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 4091 #define CP_MQD_CONTROL__MTYPE_MASK 0x18000000 4092 #define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b 4093 #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff 4094 #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 4095 #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff 4096 #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 4097 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff 4098 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 4099 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff 4100 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 4101 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f 4102 #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 4103 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 4104 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 4105 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 4106 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc 4107 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 4108 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd 4109 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 4110 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe 4111 #define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000 4112 #define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf 4113 #define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000 4114 #define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 4115 #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000 4116 #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 4117 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 4118 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d 4119 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 4120 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f 4121 #define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff 4122 #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 4123 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 4124 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e 4125 #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000 4126 #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f 4127 #define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff 4128 #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 4129 #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000 4130 #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 4131 #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff 4132 #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 4133 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000 4134 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 4135 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000 4136 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc 4137 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff 4138 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 4139 #define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1 4140 #define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0 4141 #define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6 4142 #define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1 4143 #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8 4144 #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 4145 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc 4146 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 4147 #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000 4148 #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc 4149 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc 4150 #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 4151 #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000 4152 #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc 4153 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1 4154 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 4155 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2 4156 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 4157 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0 4158 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 4159 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000 4160 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc 4161 #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf 4162 #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 4163 #define CP_HQD_ERROR__SUA_ERROR_MASK 0x10 4164 #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 4165 #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff 4166 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 4167 #define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff 4168 #define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0 4169 #define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff 4170 #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 4171 #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff 4172 #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 4173 #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff 4174 #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 4175 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff 4176 #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 4177 #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf 4178 #define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 4179 #define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 4180 #define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 4181 #define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 4182 #define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 4183 #define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 4184 #define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd 4185 #define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 4186 #define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf 4187 #define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 4188 #define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 4189 #define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 4190 #define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 4191 #define DB_Z_INFO__FORMAT_MASK 0x3 4192 #define DB_Z_INFO__FORMAT__SHIFT 0x0 4193 #define DB_Z_INFO__NUM_SAMPLES_MASK 0xc 4194 #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 4195 #define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 4196 #define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd 4197 #define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 4198 #define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 4199 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000 4200 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 4201 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 4202 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 4203 #define DB_Z_INFO__READ_SIZE_MASK 0x10000000 4204 #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c 4205 #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 4206 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 4207 #define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000 4208 #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e 4209 #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 4210 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f 4211 #define DB_STENCIL_INFO__FORMAT_MASK 0x1 4212 #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 4213 #define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 4214 #define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd 4215 #define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 4216 #define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 4217 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 4218 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 4219 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 4220 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 4221 #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000 4222 #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e 4223 #define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff 4224 #define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 4225 #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 4226 #define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb 4227 #define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff 4228 #define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 4229 #define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff 4230 #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 4231 #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 4232 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd 4233 #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 4234 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 4235 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 4236 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 4237 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 4238 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 4239 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 4240 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 4241 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 4242 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 4243 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 4244 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 4245 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 4246 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 4247 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 4248 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 4249 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 4250 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 4251 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 4252 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 4253 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 4254 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 4255 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000 4256 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc 4257 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 4258 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 4259 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 4260 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 4261 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 4262 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 4263 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 4264 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 4265 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 4266 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc 4267 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 4268 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 4269 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 4270 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 4271 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 4272 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 4273 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 4274 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c 4275 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 4276 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 4277 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc 4278 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 4279 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 4280 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 4281 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 4282 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 4283 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 4284 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 4285 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 4286 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 4287 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 4288 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 4289 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 4290 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa 4291 #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 4292 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb 4293 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 4294 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc 4295 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 4296 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd 4297 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 4298 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf 4299 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 4300 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 4301 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 4302 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 4303 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 4304 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 4305 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 4306 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 4307 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 4308 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 4309 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 4310 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a 4311 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 4312 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b 4313 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 4314 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c 4315 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 4316 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 4317 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 4318 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e 4319 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 4320 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f 4321 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 4322 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 4323 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c 4324 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 4325 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 4326 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 4327 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 4328 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 4329 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 4330 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 4331 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 4332 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 4333 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 4334 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 4335 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 4336 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa 4337 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 4338 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb 4339 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 4340 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc 4341 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 4342 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf 4343 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 4344 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 4345 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 4346 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 4347 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 4348 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 4349 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 4350 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 4351 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 4352 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 4353 #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 4354 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 4355 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 4356 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 4357 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 4358 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc 4359 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 4360 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 4361 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 4362 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 4363 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 4364 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 4365 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 4366 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 4367 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 4368 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 4369 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 4370 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 4371 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 4372 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 4373 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 4374 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b 4375 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 4376 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 4377 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 4378 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 4379 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 4380 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 4381 #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 4382 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 4383 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 4384 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 4385 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 4386 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 4387 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 4388 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 4389 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 4390 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 4391 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 4392 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa 4393 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 4394 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb 4395 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 4396 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc 4397 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 4398 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd 4399 #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff 4400 #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 4401 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff 4402 #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 4403 #define DB_STENCIL_CLEAR__CLEAR_MASK 0xff 4404 #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 4405 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff 4406 #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 4407 #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff 4408 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 4409 #define DB_HTILE_SURFACE__LINEAR_MASK 0x1 4410 #define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 4411 #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 4412 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 4413 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 4414 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 4415 #define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 4416 #define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 4417 #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 4418 #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 4419 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 4420 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa 4421 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 4422 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 4423 #define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000 4424 #define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11 4425 #define DB_PRELOAD_CONTROL__START_X_MASK 0xff 4426 #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 4427 #define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 4428 #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 4429 #define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 4430 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 4431 #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 4432 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 4433 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff 4434 #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 4435 #define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 4436 #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 4437 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 4438 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 4439 #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 4440 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 4441 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff 4442 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 4443 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 4444 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 4445 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 4446 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 4447 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 4448 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 4449 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 4450 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 4451 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 4452 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 4453 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 4454 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc 4455 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 4456 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 4457 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 4458 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 4459 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 4460 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 4461 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 4462 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc 4463 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 4464 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 4465 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 4466 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 4467 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 4468 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 4469 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 4470 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 4471 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 4472 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 4473 #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 4474 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 4475 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 4476 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 4477 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 4478 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 4479 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 4480 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 4481 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 4482 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e 4483 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 4484 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f 4485 #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf 4486 #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 4487 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 4488 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 4489 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 4490 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 4491 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 4492 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc 4493 #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 4494 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 4495 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 4496 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 4497 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 4498 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 4499 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 4500 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 4501 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 4502 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa 4503 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 4504 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc 4505 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 4506 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe 4507 #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 4508 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 4509 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 4510 #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 4511 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 4512 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 4513 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 4514 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 4515 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 4516 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 4517 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 4518 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 4519 #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 4520 #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 4521 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 4522 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 4523 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 4524 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 4525 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 4526 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 4527 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 4528 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 4529 #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 4530 #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 4531 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 4532 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 4533 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 4534 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 4535 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 4536 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 4537 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 4538 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 4539 #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 4540 #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 4541 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 4542 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 4543 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 4544 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 4545 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 4546 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 4547 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 4548 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 4549 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 4550 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 4551 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 4552 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 4553 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 4554 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 4555 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 4556 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 4557 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 4558 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 4559 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 4560 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 4561 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 4562 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 4563 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 4564 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 4565 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 4566 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 4567 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 4568 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 4569 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 4570 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 4571 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 4572 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 4573 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 4574 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 4575 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 4576 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 4577 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 4578 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 4579 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 4580 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 4581 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 4582 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 4583 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 4584 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 4585 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 4586 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 4587 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 4588 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 4589 #define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 4590 #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 4591 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 4592 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 4593 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 4594 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 4595 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 4596 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 4597 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 4598 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa 4599 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 4600 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc 4601 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 4602 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe 4603 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 4604 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf 4605 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 4606 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 4607 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 4608 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 4609 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 4610 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 4611 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 4612 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 4613 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 4614 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 4615 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 4616 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 4617 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 4618 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 4619 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 4620 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 4621 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 4622 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c 4623 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 4624 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 4625 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 4626 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e 4627 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 4628 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f 4629 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 4630 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 4631 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 4632 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 4633 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 4634 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 4635 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 4636 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 4637 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 4638 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 4639 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 4640 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 4641 #define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 4642 #define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 4643 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 4644 #define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 4645 #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 4646 #define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 4647 #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 4648 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 4649 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 4650 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe 4651 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 4652 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf 4653 #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 4654 #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 4655 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 4656 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 4657 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 4658 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 4659 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 4660 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 4661 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 4662 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c 4663 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 4664 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 4665 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 4666 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e 4667 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 4668 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f 4669 #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 4670 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 4671 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 4672 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 4673 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 4674 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 4675 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 4676 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 4677 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 4678 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 4679 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 4680 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 4681 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 4682 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 4683 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 4684 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 4685 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 4686 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa 4687 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 4688 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb 4689 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 4690 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc 4691 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 4692 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd 4693 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 4694 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe 4695 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 4696 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf 4697 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 4698 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 4699 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 4700 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 4701 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 4702 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 4703 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 4704 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 4705 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 4706 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 4707 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 4708 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 4709 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 4710 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 4711 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 4712 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 4713 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 4714 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 4715 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 4716 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 4717 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 4718 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a 4719 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 4720 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b 4721 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 4722 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c 4723 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 4724 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 4725 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000 4726 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e 4727 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000 4728 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f 4729 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 4730 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 4731 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 4732 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 4733 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 4734 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 4735 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 4736 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 4737 #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0 4738 #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4 4739 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f 4740 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 4741 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 4742 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 4743 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 4744 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa 4745 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 4746 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 4747 #define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f 4748 #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 4749 #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 4750 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 4751 #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 4752 #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb 4753 #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 4754 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf 4755 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 4756 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 4757 #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 4758 #define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b 4759 #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 4760 #define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c 4761 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 4762 #define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d 4763 #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 4764 #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e 4765 #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 4766 #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f 4767 #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 4768 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 4769 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc 4770 #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 4771 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 4772 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 4773 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 4774 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 4775 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 4776 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 4777 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 4778 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa 4779 #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 4780 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc 4781 #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 4782 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe 4783 #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 4784 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 4785 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 4786 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 4787 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f 4788 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 4789 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 4790 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 4791 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 4792 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe 4793 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 4794 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 4795 #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 4796 #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 4797 #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f 4798 #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 4799 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 4800 #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 4801 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 4802 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa 4803 #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 4804 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 4805 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 4806 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 4807 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff 4808 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 4809 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 4810 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 4811 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 4812 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf 4813 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 4814 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 4815 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf 4816 #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 4817 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 4818 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 4819 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 4820 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc 4821 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 4822 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 4823 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 4824 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 4825 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 4826 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a 4827 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 4828 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b 4829 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 4830 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c 4831 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 4832 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 4833 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 4834 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e 4835 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 4836 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f 4837 #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff 4838 #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 4839 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff 4840 #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 4841 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 4842 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 4843 #define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff 4844 #define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 4845 #define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff 4846 #define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 4847 #define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff 4848 #define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 4849 #define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff 4850 #define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 4851 #define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff 4852 #define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 4853 #define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff 4854 #define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 4855 #define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff 4856 #define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 4857 #define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff 4858 #define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 4859 #define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff 4860 #define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 4861 #define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff 4862 #define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 4863 #define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff 4864 #define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 4865 #define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff 4866 #define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 4867 #define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff 4868 #define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 4869 #define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff 4870 #define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 4871 #define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff 4872 #define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 4873 #define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff 4874 #define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 4875 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff 4876 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 4877 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff 4878 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 4879 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff 4880 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 4881 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff 4882 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 4883 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff 4884 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 4885 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff 4886 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 4887 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff 4888 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 4889 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff 4890 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 4891 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 4892 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 4893 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 4894 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 4895 #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 4896 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 4897 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 4898 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 4899 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 4900 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 4901 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 4902 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 4903 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 4904 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 4905 #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 4906 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 4907 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 4908 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 4909 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 4910 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 4911 #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 4912 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4913 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 4914 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 4915 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 4916 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4917 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 4918 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 4919 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 4920 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 4921 #define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 4922 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 4923 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 4924 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 4925 #define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 4926 #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 4927 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 4928 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 4929 #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff 4930 #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 4931 #define GB_GPU_ID__GPU_ID_MASK 0xf 4932 #define GB_GPU_ID__GPU_ID__SHIFT 0x0 4933 #define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf 4934 #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 4935 #define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 4936 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 4937 #define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 4938 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 4939 #define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 4940 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc 4941 #define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 4942 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 4943 #define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 4944 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 4945 #define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 4946 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 4947 #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 4948 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c 4949 #define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c 4950 #define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 4951 #define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 4952 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 4953 #define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 4954 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb 4955 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4956 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 4957 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 4958 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 4959 #define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c 4960 #define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 4961 #define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 4962 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 4963 #define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 4964 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb 4965 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4966 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 4967 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 4968 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 4969 #define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c 4970 #define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 4971 #define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 4972 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 4973 #define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 4974 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb 4975 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4976 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 4977 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 4978 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 4979 #define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c 4980 #define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 4981 #define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 4982 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 4983 #define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 4984 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb 4985 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4986 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 4987 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 4988 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 4989 #define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c 4990 #define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 4991 #define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 4992 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 4993 #define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 4994 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb 4995 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 4996 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 4997 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 4998 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 4999 #define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c 5000 #define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 5001 #define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 5002 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 5003 #define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 5004 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb 5005 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5006 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 5007 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 5008 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 5009 #define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c 5010 #define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 5011 #define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 5012 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 5013 #define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 5014 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb 5015 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5016 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 5017 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 5018 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 5019 #define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c 5020 #define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 5021 #define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 5022 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 5023 #define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 5024 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb 5025 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5026 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 5027 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 5028 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 5029 #define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c 5030 #define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 5031 #define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 5032 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 5033 #define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 5034 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb 5035 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5036 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 5037 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 5038 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 5039 #define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c 5040 #define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 5041 #define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 5042 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 5043 #define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 5044 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb 5045 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5046 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 5047 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 5048 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 5049 #define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c 5050 #define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 5051 #define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 5052 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 5053 #define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 5054 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb 5055 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5056 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 5057 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 5058 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 5059 #define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c 5060 #define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 5061 #define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 5062 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 5063 #define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 5064 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb 5065 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5066 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 5067 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 5068 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 5069 #define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c 5070 #define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 5071 #define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 5072 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 5073 #define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 5074 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb 5075 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5076 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 5077 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 5078 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 5079 #define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c 5080 #define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 5081 #define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 5082 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 5083 #define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 5084 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb 5085 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5086 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 5087 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 5088 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 5089 #define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c 5090 #define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 5091 #define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 5092 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 5093 #define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 5094 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb 5095 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5096 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 5097 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 5098 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 5099 #define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c 5100 #define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 5101 #define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 5102 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 5103 #define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 5104 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb 5105 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5106 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 5107 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 5108 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 5109 #define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c 5110 #define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 5111 #define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 5112 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 5113 #define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 5114 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb 5115 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5116 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 5117 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 5118 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 5119 #define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c 5120 #define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 5121 #define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 5122 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 5123 #define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 5124 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb 5125 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5126 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 5127 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 5128 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 5129 #define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c 5130 #define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 5131 #define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 5132 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 5133 #define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 5134 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb 5135 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5136 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 5137 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 5138 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 5139 #define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c 5140 #define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 5141 #define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 5142 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 5143 #define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 5144 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb 5145 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5146 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 5147 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 5148 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 5149 #define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c 5150 #define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 5151 #define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 5152 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 5153 #define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 5154 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb 5155 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5156 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 5157 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 5158 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 5159 #define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c 5160 #define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 5161 #define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 5162 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 5163 #define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 5164 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb 5165 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5166 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 5167 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 5168 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 5169 #define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c 5170 #define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 5171 #define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 5172 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 5173 #define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 5174 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb 5175 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5176 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 5177 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 5178 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 5179 #define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c 5180 #define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 5181 #define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 5182 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 5183 #define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 5184 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb 5185 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5186 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 5187 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 5188 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 5189 #define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c 5190 #define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 5191 #define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 5192 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 5193 #define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 5194 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb 5195 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5196 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 5197 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 5198 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 5199 #define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c 5200 #define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 5201 #define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 5202 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 5203 #define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 5204 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb 5205 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5206 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 5207 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 5208 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 5209 #define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c 5210 #define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 5211 #define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 5212 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 5213 #define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 5214 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb 5215 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5216 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 5217 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 5218 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 5219 #define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c 5220 #define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 5221 #define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 5222 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 5223 #define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 5224 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb 5225 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5226 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 5227 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 5228 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 5229 #define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c 5230 #define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 5231 #define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 5232 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 5233 #define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 5234 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb 5235 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5236 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 5237 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 5238 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 5239 #define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c 5240 #define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 5241 #define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 5242 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 5243 #define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 5244 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb 5245 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5246 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 5247 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 5248 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 5249 #define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c 5250 #define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 5251 #define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 5252 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 5253 #define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 5254 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb 5255 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5256 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 5257 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 5258 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 5259 #define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c 5260 #define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 5261 #define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 5262 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 5263 #define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 5264 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb 5265 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 5266 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 5267 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 5268 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 5269 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 5270 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 5271 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc 5272 #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 5273 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 5274 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 5275 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 5276 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 5277 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 5278 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 5279 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc 5280 #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 5281 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 5282 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 5283 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 5284 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 5285 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 5286 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 5287 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc 5288 #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 5289 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 5290 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 5291 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 5292 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 5293 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 5294 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 5295 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc 5296 #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 5297 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 5298 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 5299 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 5300 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 5301 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 5302 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 5303 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc 5304 #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 5305 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 5306 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 5307 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 5308 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 5309 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 5310 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 5311 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc 5312 #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 5313 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 5314 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 5315 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 5316 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 5317 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 5318 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 5319 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc 5320 #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 5321 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 5322 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 5323 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 5324 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 5325 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 5326 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 5327 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc 5328 #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 5329 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 5330 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 5331 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 5332 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 5333 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 5334 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 5335 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc 5336 #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 5337 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 5338 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 5339 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 5340 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 5341 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 5342 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 5343 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc 5344 #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 5345 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 5346 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 5347 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 5348 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 5349 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 5350 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 5351 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc 5352 #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 5353 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 5354 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 5355 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 5356 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 5357 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 5358 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 5359 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc 5360 #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 5361 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 5362 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 5363 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 5364 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 5365 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 5366 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 5367 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc 5368 #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 5369 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 5370 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 5371 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 5372 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 5373 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 5374 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 5375 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc 5376 #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 5377 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 5378 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 5379 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 5380 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 5381 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 5382 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 5383 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc 5384 #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 5385 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 5386 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 5387 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 5388 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 5389 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 5390 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 5391 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc 5392 #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 5393 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 5394 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 5395 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 5396 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 5397 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 5398 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 5399 #define GB_EDC_MODE__DED_MODE_MASK 0x300000 5400 #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 5401 #define GB_EDC_MODE__PROP_FED_MASK 0x20000000 5402 #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 5403 #define GB_EDC_MODE__BYPASS_MASK 0x80000000 5404 #define GB_EDC_MODE__BYPASS__SHIFT 0x1f 5405 #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 5406 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 5407 #define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 5408 #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 5409 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff 5410 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 5411 #define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5412 #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 5413 #define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5414 #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 5415 #define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff 5416 #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 5417 #define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff 5418 #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 5419 #define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5420 #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 5421 #define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5422 #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 5423 #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5424 #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 5425 #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5426 #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 5427 #define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5428 #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 5429 #define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5430 #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 5431 #define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff 5432 #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 5433 #define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff 5434 #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 5435 #define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff 5436 #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 5437 #define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff 5438 #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 5439 #define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff 5440 #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 5441 #define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff 5442 #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 5443 #define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5444 #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 5445 #define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5446 #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 5447 #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5448 #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 5449 #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5450 #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 5451 #define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5452 #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 5453 #define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5454 #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 5455 #define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5456 #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 5457 #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff 5458 #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 5459 #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5460 #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 5461 #define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff 5462 #define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 5463 #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7 5464 #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 5465 #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 5466 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 5467 #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff 5468 #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 5469 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 5470 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 5471 #define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 5472 #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 5473 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 5474 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 5475 #define GRBM_CNTL__READ_TIMEOUT_MASK 0xff 5476 #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 5477 #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000 5478 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f 5479 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f 5480 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 5481 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 5482 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 5483 #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3 5484 #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 5485 #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc 5486 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 5487 #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30 5488 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 5489 #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0 5490 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 5491 #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000 5492 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe 5493 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000 5494 #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf 5495 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf 5496 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 5497 #define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 5498 #define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 5499 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 5500 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 5501 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 5502 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 5503 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 5504 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 5505 #define GRBM_STATUS__DB_CLEAN_MASK 0x1000 5506 #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc 5507 #define GRBM_STATUS__CB_CLEAN_MASK 0x2000 5508 #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd 5509 #define GRBM_STATUS__TA_BUSY_MASK 0x4000 5510 #define GRBM_STATUS__TA_BUSY__SHIFT 0xe 5511 #define GRBM_STATUS__GDS_BUSY_MASK 0x8000 5512 #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf 5513 #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 5514 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 5515 #define GRBM_STATUS__VGT_BUSY_MASK 0x20000 5516 #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 5517 #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 5518 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 5519 #define GRBM_STATUS__IA_BUSY_MASK 0x80000 5520 #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 5521 #define GRBM_STATUS__SX_BUSY_MASK 0x100000 5522 #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 5523 #define GRBM_STATUS__WD_BUSY_MASK 0x200000 5524 #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 5525 #define GRBM_STATUS__SPI_BUSY_MASK 0x400000 5526 #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 5527 #define GRBM_STATUS__BCI_BUSY_MASK 0x800000 5528 #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 5529 #define GRBM_STATUS__SC_BUSY_MASK 0x1000000 5530 #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 5531 #define GRBM_STATUS__PA_BUSY_MASK 0x2000000 5532 #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 5533 #define GRBM_STATUS__DB_BUSY_MASK 0x4000000 5534 #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a 5535 #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 5536 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c 5537 #define GRBM_STATUS__CP_BUSY_MASK 0x20000000 5538 #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 5539 #define GRBM_STATUS__CB_BUSY_MASK 0x40000000 5540 #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e 5541 #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 5542 #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f 5543 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf 5544 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 5545 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 5546 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 5547 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 5548 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 5549 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 5550 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 5551 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 5552 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 5553 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 5554 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 5555 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 5556 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 5557 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 5558 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa 5559 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 5560 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb 5561 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 5562 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc 5563 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 5564 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd 5565 #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 5566 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe 5567 #define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 5568 #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 5569 #define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 5570 #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 5571 #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000 5572 #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a 5573 #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 5574 #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c 5575 #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 5576 #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 5577 #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 5578 #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e 5579 #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 5580 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 5581 #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 5582 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 5583 #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 5584 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 5585 #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 5586 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 5587 #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 5588 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 5589 #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 5590 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 5591 #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 5592 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a 5593 #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 5594 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b 5595 #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 5596 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 5597 #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 5598 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e 5599 #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 5600 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f 5601 #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 5602 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 5603 #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 5604 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 5605 #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 5606 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 5607 #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 5608 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 5609 #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 5610 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 5611 #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 5612 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 5613 #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 5614 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a 5615 #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 5616 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b 5617 #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 5618 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 5619 #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 5620 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e 5621 #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 5622 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f 5623 #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 5624 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 5625 #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 5626 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 5627 #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 5628 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 5629 #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 5630 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 5631 #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 5632 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 5633 #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 5634 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 5635 #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 5636 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a 5637 #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 5638 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b 5639 #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 5640 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 5641 #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 5642 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e 5643 #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 5644 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f 5645 #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 5646 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 5647 #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 5648 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 5649 #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 5650 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 5651 #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 5652 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 5653 #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 5654 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 5655 #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 5656 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 5657 #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 5658 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a 5659 #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 5660 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b 5661 #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 5662 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 5663 #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 5664 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e 5665 #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 5666 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f 5667 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 5668 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 5669 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 5670 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 5671 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 5672 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 5673 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 5674 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 5675 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 5676 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 5677 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 5678 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 5679 #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000 5680 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 5681 #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f 5682 #define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 5683 #define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff 5684 #define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 5685 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff 5686 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 5687 #define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 5688 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 5689 #define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 5690 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 5691 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 5692 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 5693 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 5694 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 5695 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 5696 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f 5697 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 5698 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 5699 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 5700 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 5701 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff 5702 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 5703 #define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 5704 #define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 5705 #define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 5706 #define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 5707 #define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 5708 #define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 5709 #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 5710 #define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 5711 #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 5712 #define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 5713 #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 5714 #define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc 5715 #define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000 5716 #define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd 5717 #define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000 5718 #define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f 5719 #define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 5720 #define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 5721 #define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 5722 #define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 5723 #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 5724 #define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 5725 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 5726 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 5727 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 5728 #define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 5729 #define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 5730 #define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 5731 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 5732 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 5733 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 5734 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 5735 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 5736 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 5737 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 5738 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 5739 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 5740 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa 5741 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 5742 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb 5743 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 5744 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc 5745 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 5746 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd 5747 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 5748 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe 5749 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 5750 #define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf 5751 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 5752 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 5753 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 5754 #define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 5755 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 5756 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 5757 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 5758 #define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 5759 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 5760 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 5761 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 5762 #define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 5763 #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 5764 #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 5765 #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 5766 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 5767 #define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 5768 #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 5769 #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 5770 #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 5771 #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 5772 #define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 5773 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 5774 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 5775 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 5776 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 5777 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 5778 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 5779 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 5780 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 5781 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 5782 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 5783 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 5784 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 5785 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 5786 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 5787 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 5788 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 5789 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 5790 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a 5791 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 5792 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b 5793 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 5794 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c 5795 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 5796 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 5797 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 5798 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e 5799 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 5800 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f 5801 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 5802 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 5803 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 5804 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 5805 #define GRBM_TRAP_OP__RW_MASK 0x1 5806 #define GRBM_TRAP_OP__RW__SHIFT 0x0 5807 #define GRBM_TRAP_ADDR__DATA_MASK 0xffff 5808 #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 5809 #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff 5810 #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 5811 #define GRBM_TRAP_WD__DATA_MASK 0xffffffff 5812 #define GRBM_TRAP_WD__DATA__SHIFT 0x0 5813 #define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff 5814 #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 5815 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3 5816 #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 5817 #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4 5818 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 5819 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1 5820 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 5821 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2 5822 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1 5823 #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c 5824 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 5825 #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0 5826 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 5827 #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000 5828 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc 5829 #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000 5830 #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd 5831 #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000 5832 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 5833 #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000 5834 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 5835 #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000 5836 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f 5837 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 5838 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 5839 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5840 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5841 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5842 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5843 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 5844 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5845 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 5846 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5847 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 5848 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 5849 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 5850 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5851 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 5852 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5853 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 5854 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5855 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 5856 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5857 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 5858 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5859 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 5860 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5861 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 5862 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 5863 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 5864 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 5865 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 5866 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 5867 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 5868 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 5869 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 5870 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 5871 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 5872 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 5873 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 5874 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 5875 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 5876 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 5877 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5878 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5879 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5880 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5881 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 5882 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5883 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 5884 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5885 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 5886 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 5887 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 5888 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5889 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 5890 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5891 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 5892 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5893 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 5894 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5895 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 5896 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5897 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 5898 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5899 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 5900 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 5901 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 5902 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 5903 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 5904 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 5905 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 5906 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 5907 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 5908 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 5909 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 5910 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 5911 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 5912 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 5913 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5914 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5915 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5916 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5917 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5918 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5919 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5920 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5921 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5922 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5923 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5924 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5925 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5926 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5927 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5928 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5929 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5930 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5931 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5932 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5933 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5934 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5935 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5936 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5937 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5938 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5939 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5940 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5941 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5942 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5943 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5944 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5945 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5946 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5947 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5948 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5949 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5950 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5951 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5952 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5953 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5954 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5955 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5956 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5957 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5958 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5959 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5960 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5961 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5962 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5963 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5964 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5965 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5966 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5967 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5968 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5969 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5970 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5971 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5972 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5973 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5974 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5975 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 5976 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 5977 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 5978 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 5979 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 5980 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 5981 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 5982 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 5983 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 5984 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 5985 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f 5986 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 5987 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 5988 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 5989 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 5990 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 5991 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 5992 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 5993 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 5994 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 5995 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 5996 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 5997 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 5998 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 5999 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 6000 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 6001 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 6002 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 6003 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 6004 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 6005 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 6006 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 6007 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 6008 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 6009 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 6010 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 6011 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 6012 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 6013 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 6014 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 6015 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 6016 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 6017 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 6018 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 6019 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 6020 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 6021 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 6022 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 6023 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 6024 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 6025 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 6026 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 6027 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 6028 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 6029 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff 6030 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 6031 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff 6032 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 6033 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff 6034 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 6035 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff 6036 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 6037 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff 6038 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 6039 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff 6040 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 6041 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff 6042 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 6043 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff 6044 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 6045 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff 6046 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 6047 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff 6048 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 6049 #define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff 6050 #define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 6051 #define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff 6052 #define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 6053 #define GRBM_NOWHERE__DATA_MASK 0xffffffff 6054 #define GRBM_NOWHERE__DATA__SHIFT 0x0 6055 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff 6056 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 6057 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff 6058 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 6059 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff 6060 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 6061 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff 6062 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 6063 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff 6064 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 6065 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff 6066 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 6067 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff 6068 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 6069 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff 6070 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 6071 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff 6072 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 6073 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff 6074 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 6075 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff 6076 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 6077 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff 6078 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 6079 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff 6080 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 6081 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff 6082 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 6083 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff 6084 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 6085 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff 6086 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 6087 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff 6088 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 6089 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff 6090 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 6091 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff 6092 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 6093 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff 6094 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 6095 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff 6096 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 6097 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff 6098 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 6099 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff 6100 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 6101 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff 6102 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 6103 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff 6104 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 6105 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff 6106 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 6107 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff 6108 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 6109 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff 6110 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 6111 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff 6112 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 6113 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff 6114 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 6115 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff 6116 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 6117 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff 6118 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 6119 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff 6120 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 6121 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff 6122 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 6123 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff 6124 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 6125 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff 6126 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 6127 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff 6128 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 6129 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff 6130 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 6131 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff 6132 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 6133 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff 6134 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 6135 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff 6136 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 6137 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff 6138 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 6139 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff 6140 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 6141 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff 6142 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 6143 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff 6144 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 6145 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff 6146 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 6147 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff 6148 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 6149 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff 6150 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 6151 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff 6152 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 6153 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff 6154 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 6155 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff 6156 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 6157 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff 6158 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 6159 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff 6160 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 6161 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff 6162 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 6163 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff 6164 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 6165 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff 6166 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 6167 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff 6168 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 6169 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff 6170 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 6171 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff 6172 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 6173 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff 6174 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 6175 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff 6176 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 6177 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff 6178 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 6179 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff 6180 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 6181 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff 6182 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 6183 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff 6184 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 6185 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff 6186 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 6187 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff 6188 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 6189 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff 6190 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 6191 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff 6192 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 6193 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff 6194 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 6195 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff 6196 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 6197 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff 6198 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 6199 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff 6200 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 6201 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff 6202 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 6203 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff 6204 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 6205 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff 6206 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 6207 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff 6208 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 6209 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff 6210 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 6211 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff 6212 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 6213 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff 6214 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 6215 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff 6216 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 6217 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff 6218 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 6219 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff 6220 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 6221 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff 6222 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 6223 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff 6224 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 6225 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff 6226 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 6227 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff 6228 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 6229 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff 6230 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 6231 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff 6232 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 6233 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff 6234 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 6235 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff 6236 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 6237 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff 6238 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 6239 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff 6240 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 6241 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff 6242 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 6243 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff 6244 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 6245 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff 6246 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 6247 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 6248 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 6249 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 6250 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 6251 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 6252 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 6253 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 6254 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 6255 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 6256 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 6257 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 6258 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 6259 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 6260 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 6261 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 6262 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 6263 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 6264 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa 6265 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 6266 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb 6267 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 6268 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 6269 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 6270 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 6271 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 6272 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 6273 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 6274 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 6275 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 6276 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 6277 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 6278 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 6279 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 6280 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 6281 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 6282 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 6283 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 6284 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 6285 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 6286 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 6287 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 6288 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa 6289 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 6290 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb 6291 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 6292 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc 6293 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 6294 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd 6295 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 6296 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe 6297 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 6298 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf 6299 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 6300 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 6301 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 6302 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 6303 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 6304 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 6305 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 6306 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 6307 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 6308 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 6309 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 6310 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 6311 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 6312 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 6313 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 6314 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 6315 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 6316 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 6317 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 6318 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 6319 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000 6320 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a 6321 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 6322 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 6323 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 6324 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 6325 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 6326 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 6327 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 6328 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 6329 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 6330 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 6331 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 6332 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 6333 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 6334 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 6335 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 6336 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 6337 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 6338 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 6339 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 6340 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 6341 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 6342 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa 6343 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 6344 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb 6345 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 6346 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc 6347 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 6348 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd 6349 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 6350 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe 6351 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 6352 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 6353 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 6354 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 6355 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 6356 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 6357 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 6358 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 6359 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 6360 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 6361 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 6362 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 6363 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 6364 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 6365 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 6366 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd 6367 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 6368 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe 6369 #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 6370 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 6371 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 6372 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 6373 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 6374 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 6375 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 6376 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 6377 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 6378 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 6379 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 6380 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 6381 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 6382 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 6383 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 6384 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 6385 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 6386 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 6387 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 6388 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a 6389 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 6390 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b 6391 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff 6392 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 6393 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff 6394 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 6395 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff 6396 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 6397 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff 6398 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 6399 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff 6400 #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 6401 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff 6402 #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 6403 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff 6404 #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 6405 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff 6406 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 6407 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff 6408 #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 6409 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff 6410 #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 6411 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff 6412 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 6413 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff 6414 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 6415 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff 6416 #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 6417 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff 6418 #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 6419 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff 6420 #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 6421 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff 6422 #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 6423 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff 6424 #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 6425 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff 6426 #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 6427 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff 6428 #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 6429 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff 6430 #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 6431 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff 6432 #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 6433 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff 6434 #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 6435 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff 6436 #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 6437 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff 6438 #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 6439 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff 6440 #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 6441 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff 6442 #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 6443 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff 6444 #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 6445 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff 6446 #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 6447 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff 6448 #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 6449 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff 6450 #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 6451 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff 6452 #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 6453 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff 6454 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 6455 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 6456 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 6457 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 6458 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 6459 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 6460 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 6461 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 6462 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 6463 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 6464 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 6465 #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 6466 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c 6467 #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 6468 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 6469 #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 6470 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e 6471 #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 6472 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f 6473 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 6474 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 6475 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 6476 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 6477 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 6478 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 6479 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 6480 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 6481 #define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff 6482 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 6483 #define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 6484 #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 6485 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff 6486 #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 6487 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 6488 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 6489 #define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff 6490 #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 6491 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 6492 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 6493 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 6494 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 6495 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 6496 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 6497 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 6498 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 6499 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff 6500 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 6501 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 6502 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 6503 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 6504 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 6505 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 6506 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 6507 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 6508 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 6509 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 6510 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 6511 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 6512 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 6513 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 6514 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 6515 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 6516 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 6517 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 6518 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 6519 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 6520 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e 6521 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 6522 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f 6523 #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 6524 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 6525 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 6526 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 6527 #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 6528 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 6529 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 6530 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 6531 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 6532 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 6533 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 6534 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 6535 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 6536 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb 6537 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 6538 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc 6539 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 6540 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd 6541 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 6542 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 6543 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 6544 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 6545 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 6546 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 6547 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 6548 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 6549 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff 6550 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 6551 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 6552 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 6553 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff 6554 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 6555 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff 6556 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 6557 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff 6558 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 6559 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff 6560 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 6561 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff 6562 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 6563 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff 6564 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 6565 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 6566 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 6567 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff 6568 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 6569 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 6570 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 6571 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 6572 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 6573 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 6574 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 6575 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 6576 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 6577 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 6578 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 6579 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 6580 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 6581 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 6582 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 6583 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 6584 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 6585 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 6586 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 6587 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 6588 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 6589 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 6590 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 6591 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 6592 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 6593 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 6594 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 6595 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 6596 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 6597 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 6598 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 6599 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff 6600 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 6601 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 6602 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 6603 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff 6604 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 6605 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 6606 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 6607 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff 6608 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 6609 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 6610 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 6611 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff 6612 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 6613 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 6614 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 6615 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 6616 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 6617 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 6618 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd 6619 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 6620 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 6621 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 6622 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 6623 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff 6624 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 6625 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 6626 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 6627 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff 6628 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 6629 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 6630 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 6631 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf 6632 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 6633 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 6634 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 6635 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 6636 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 6637 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 6638 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc 6639 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 6640 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 6641 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 6642 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 6643 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 6644 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 6645 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 6646 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c 6647 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf 6648 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 6649 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 6650 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 6651 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 6652 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 6653 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 6654 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc 6655 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 6656 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 6657 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 6658 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 6659 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 6660 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 6661 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 6662 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c 6663 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf 6664 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 6665 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 6666 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 6667 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 6668 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 6669 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 6670 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc 6671 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 6672 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 6673 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 6674 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 6675 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 6676 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 6677 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 6678 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c 6679 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf 6680 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 6681 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 6682 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 6683 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 6684 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 6685 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 6686 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc 6687 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 6688 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 6689 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 6690 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 6691 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 6692 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 6693 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 6694 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c 6695 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf 6696 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 6697 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 6698 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 6699 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 6700 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 6701 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 6702 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc 6703 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 6704 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 6705 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 6706 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 6707 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 6708 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 6709 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 6710 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c 6711 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf 6712 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 6713 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 6714 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 6715 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 6716 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 6717 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 6718 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc 6719 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 6720 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 6721 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 6722 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 6723 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 6724 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 6725 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 6726 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c 6727 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf 6728 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 6729 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 6730 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 6731 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 6732 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 6733 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 6734 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc 6735 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 6736 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 6737 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 6738 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 6739 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 6740 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 6741 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 6742 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c 6743 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf 6744 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 6745 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 6746 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 6747 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 6748 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 6749 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 6750 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc 6751 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 6752 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 6753 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 6754 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 6755 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 6756 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 6757 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 6758 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c 6759 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf 6760 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 6761 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 6762 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 6763 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 6764 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 6765 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 6766 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc 6767 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 6768 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 6769 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 6770 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 6771 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 6772 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 6773 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 6774 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c 6775 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf 6776 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 6777 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 6778 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 6779 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 6780 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 6781 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 6782 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc 6783 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 6784 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 6785 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 6786 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 6787 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 6788 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 6789 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 6790 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c 6791 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf 6792 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 6793 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 6794 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 6795 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 6796 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 6797 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 6798 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc 6799 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 6800 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 6801 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 6802 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 6803 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 6804 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 6805 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 6806 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c 6807 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf 6808 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 6809 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 6810 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 6811 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 6812 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 6813 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 6814 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc 6815 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 6816 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 6817 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 6818 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 6819 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 6820 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 6821 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 6822 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c 6823 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf 6824 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 6825 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 6826 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 6827 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 6828 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 6829 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 6830 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc 6831 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 6832 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 6833 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 6834 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 6835 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 6836 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 6837 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 6838 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c 6839 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf 6840 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 6841 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 6842 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 6843 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 6844 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 6845 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 6846 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc 6847 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 6848 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 6849 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 6850 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 6851 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 6852 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 6853 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 6854 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c 6855 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf 6856 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 6857 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 6858 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 6859 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 6860 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 6861 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 6862 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc 6863 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 6864 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 6865 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 6866 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 6867 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 6868 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 6869 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 6870 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c 6871 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf 6872 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 6873 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 6874 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 6875 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 6876 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 6877 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 6878 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc 6879 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 6880 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 6881 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 6882 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 6883 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 6884 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 6885 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 6886 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c 6887 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf 6888 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 6889 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 6890 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 6891 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 6892 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 6893 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 6894 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc 6895 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 6896 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 6897 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 6898 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 6899 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 6900 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 6901 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 6902 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c 6903 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf 6904 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 6905 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 6906 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 6907 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 6908 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 6909 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 6910 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc 6911 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 6912 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 6913 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 6914 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 6915 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 6916 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 6917 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 6918 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c 6919 #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff 6920 #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 6921 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 6922 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 6923 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff 6924 #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 6925 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 6926 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 6927 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff 6928 #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 6929 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 6930 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 6931 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff 6932 #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 6933 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 6934 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 6935 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff 6936 #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 6937 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 6938 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 6939 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff 6940 #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 6941 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 6942 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 6943 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff 6944 #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 6945 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 6946 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 6947 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff 6948 #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 6949 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 6950 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 6951 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff 6952 #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 6953 #define PA_SC_EDGERULE__ER_TRI_MASK 0xf 6954 #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 6955 #define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 6956 #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 6957 #define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 6958 #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 6959 #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 6960 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc 6961 #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 6962 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 6963 #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 6964 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 6965 #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 6966 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c 6967 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 6968 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 6969 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 6970 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa 6971 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 6972 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb 6973 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 6974 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc 6975 #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff 6976 #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 6977 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 6978 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 6979 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 6980 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c 6981 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 6982 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 6983 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 6984 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 6985 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 6986 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 6987 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 6988 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 6989 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 6990 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 6991 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 6992 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 6993 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 6994 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 6995 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 6996 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 6997 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 6998 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 6999 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 7000 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 7001 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 7002 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 7003 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 7004 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 7005 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 7006 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 7007 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 7008 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa 7009 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 7010 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb 7011 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 7012 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc 7013 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 7014 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd 7015 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 7016 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe 7017 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 7018 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf 7019 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 7020 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 7021 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 7022 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 7023 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 7024 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 7025 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 7026 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 7027 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 7028 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 7029 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 7030 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 7031 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 7032 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 7033 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 7034 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a 7035 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 7036 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b 7037 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 7038 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c 7039 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 7040 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 7041 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc 7042 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 7043 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 7044 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 7045 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 7046 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 7047 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 7048 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 7049 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 7050 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 7051 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 7052 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa 7053 #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 7054 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc 7055 #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 7056 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe 7057 #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 7058 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 7059 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 7060 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 7061 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 7062 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 7063 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 7064 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 7065 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 7066 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a 7067 #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 7068 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c 7069 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 7070 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 7071 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc 7072 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 7073 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 7074 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 7075 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 7076 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 7077 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc 7078 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 7079 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff 7080 #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 7081 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 7082 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 7083 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7084 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7085 #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff 7086 #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 7087 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 7088 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 7089 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff 7090 #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 7091 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 7092 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 7093 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff 7094 #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 7095 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 7096 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 7097 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff 7098 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 7099 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 7100 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 7101 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff 7102 #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 7103 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 7104 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 7105 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7106 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7107 #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff 7108 #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 7109 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 7110 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 7111 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff 7112 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 7113 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 7114 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 7115 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7116 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7117 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff 7118 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 7119 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 7120 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 7121 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7122 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7123 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff 7124 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 7125 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 7126 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 7127 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7128 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7129 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff 7130 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 7131 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 7132 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 7133 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7134 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7135 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff 7136 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 7137 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 7138 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 7139 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7140 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7141 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff 7142 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 7143 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 7144 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 7145 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7146 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7147 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff 7148 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 7149 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 7150 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 7151 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7152 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7153 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff 7154 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 7155 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 7156 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 7157 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7158 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7159 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff 7160 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 7161 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 7162 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 7163 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7164 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7165 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff 7166 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 7167 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 7168 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 7169 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7170 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7171 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff 7172 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 7173 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 7174 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 7175 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7176 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7177 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff 7178 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 7179 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 7180 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 7181 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7182 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7183 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff 7184 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 7185 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 7186 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 7187 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7188 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7189 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff 7190 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 7191 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 7192 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 7193 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7194 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7195 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff 7196 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 7197 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 7198 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 7199 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7200 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7201 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff 7202 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 7203 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 7204 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 7205 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 7206 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 7207 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff 7208 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 7209 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 7210 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 7211 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff 7212 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 7213 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 7214 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 7215 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff 7216 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 7217 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 7218 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 7219 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff 7220 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 7221 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 7222 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 7223 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff 7224 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 7225 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 7226 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 7227 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff 7228 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 7229 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 7230 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 7231 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff 7232 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 7233 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 7234 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 7235 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff 7236 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 7237 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 7238 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 7239 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff 7240 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 7241 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 7242 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 7243 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff 7244 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 7245 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 7246 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 7247 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff 7248 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 7249 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 7250 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 7251 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff 7252 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 7253 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 7254 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 7255 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff 7256 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 7257 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 7258 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 7259 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff 7260 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 7261 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 7262 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 7263 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff 7264 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 7265 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 7266 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 7267 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff 7268 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 7269 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 7270 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 7271 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff 7272 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 7273 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff 7274 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 7275 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff 7276 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 7277 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff 7278 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 7279 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff 7280 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 7281 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff 7282 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 7283 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff 7284 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 7285 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff 7286 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 7287 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff 7288 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 7289 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff 7290 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 7291 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff 7292 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 7293 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff 7294 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 7295 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff 7296 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 7297 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff 7298 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 7299 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff 7300 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 7301 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff 7302 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 7303 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff 7304 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 7305 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff 7306 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 7307 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff 7308 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 7309 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff 7310 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 7311 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff 7312 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 7313 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff 7314 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 7315 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff 7316 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 7317 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff 7318 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 7319 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff 7320 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 7321 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff 7322 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 7323 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff 7324 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 7325 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff 7326 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 7327 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff 7328 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 7329 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff 7330 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 7331 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff 7332 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 7333 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff 7334 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 7335 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 7336 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 7337 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 7338 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 7339 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 7340 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 7341 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 7342 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 7343 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 7344 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 7345 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 7346 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 7347 #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 7348 #define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 7349 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 7350 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 7351 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 7352 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 7353 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 7354 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa 7355 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 7356 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb 7357 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 7358 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc 7359 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 7360 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd 7361 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 7362 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe 7363 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 7364 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf 7365 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 7366 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 7367 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 7368 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 7369 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 7370 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 7371 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 7372 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 7373 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 7374 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 7375 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 7376 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 7377 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 7378 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 7379 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 7380 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 7381 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 7382 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 7383 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 7384 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 7385 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 7386 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a 7387 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 7388 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b 7389 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 7390 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c 7391 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 7392 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d 7393 #define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 7394 #define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e 7395 #define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 7396 #define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f 7397 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f 7398 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 7399 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 7400 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 7401 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 7402 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf 7403 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 7404 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 7405 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f 7406 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 7407 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 7408 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 7409 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 7410 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc 7411 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 7412 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 7413 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff 7414 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 7415 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 7416 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 7417 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf 7418 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 7419 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 7420 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 7421 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff 7422 #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 7423 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 7424 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 7425 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff 7426 #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 7427 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 7428 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 7429 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff 7430 #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 7431 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 7432 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 7433 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff 7434 #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 7435 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 7436 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 7437 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 7438 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 7439 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 7440 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 7441 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 7442 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 7443 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 7444 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 7445 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 7446 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 7447 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 7448 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 7449 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 7450 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 7451 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 7452 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 7453 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff 7454 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 7455 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff 7456 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 7457 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff 7458 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 7459 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff 7460 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 7461 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 7462 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 7463 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 7464 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 7465 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 7466 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 7467 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 7468 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 7469 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 7470 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 7471 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 7472 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 7473 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 7474 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 7475 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 7476 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 7477 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 7478 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 7479 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 7480 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 7481 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 7482 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 7483 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 7484 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 7485 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff 7486 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 7487 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff 7488 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 7489 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff 7490 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 7491 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff 7492 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 7493 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 7494 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 7495 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 7496 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 7497 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 7498 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 7499 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 7500 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 7501 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 7502 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 7503 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 7504 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 7505 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 7506 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 7507 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 7508 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 7509 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 7510 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 7511 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 7512 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 7513 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 7514 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 7515 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 7516 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 7517 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 7518 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 7519 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 7520 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 7521 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff 7522 #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 7523 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff 7524 #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 7525 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff 7526 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 7527 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff 7528 #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 7529 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 7530 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 7531 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 7532 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 7533 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 7534 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 7535 #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 7536 #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f 7537 #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 7538 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f 7539 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff 7540 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 7541 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf 7542 #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 7543 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 7544 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7545 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 7546 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 7547 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 7548 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 7549 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 7550 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 7551 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 7552 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 7553 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 7554 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 7555 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 7556 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 7557 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 7558 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e 7559 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 7560 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f 7561 #define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf 7562 #define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 7563 #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 7564 #define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7565 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 7566 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 7567 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 7568 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 7569 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 7570 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 7571 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 7572 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 7573 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 7574 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 7575 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 7576 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 7577 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 7578 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 7579 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 7580 #define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 7581 #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f 7582 #define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 7583 #define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff 7584 #define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 7585 #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f 7586 #define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 7587 #define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff 7588 #define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 7589 #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff 7590 #define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 7591 #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 7592 #define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 7593 #define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 7594 #define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 7595 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 7596 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb 7597 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 7598 #define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc 7599 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 7600 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd 7601 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 7602 #define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe 7603 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 7604 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf 7605 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 7606 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 7607 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 7608 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 7609 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 7610 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 7611 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 7612 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 7613 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 7614 #define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 7615 #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 7616 #define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 7617 #define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 7618 #define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 7619 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 7620 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 7621 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 7622 #define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 7623 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 7624 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 7625 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 7626 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a 7627 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 7628 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b 7629 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 7630 #define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c 7631 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 7632 #define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d 7633 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 7634 #define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e 7635 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 7636 #define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f 7637 #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff 7638 #define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 7639 #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 7640 #define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 7641 #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 7642 #define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb 7643 #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 7644 #define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe 7645 #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 7646 #define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 7647 #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 7648 #define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 7649 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 7650 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 7651 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 7652 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 7653 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 7654 #define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 7655 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 7656 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 7657 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 7658 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 7659 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 7660 #define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a 7661 #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 7662 #define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c 7663 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 7664 #define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d 7665 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 7666 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e 7667 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 7668 #define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f 7669 #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 7670 #define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 7671 #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 7672 #define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 7673 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 7674 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 7675 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 7676 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 7677 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 7678 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc 7679 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 7680 #define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 7681 #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 7682 #define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 7683 #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 7684 #define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 7685 #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 7686 #define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 7687 #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 7688 #define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 7689 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 7690 #define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 7691 #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 7692 #define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 7693 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 7694 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a 7695 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 7696 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b 7697 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 7698 #define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c 7699 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 7700 #define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d 7701 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 7702 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e 7703 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 7704 #define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f 7705 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff 7706 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 7707 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 7708 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe 7709 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 7710 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 7711 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 7712 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 7713 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 7714 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 7715 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 7716 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 7717 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 7718 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c 7719 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 7720 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d 7721 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 7722 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e 7723 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 7724 #define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7725 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7726 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7727 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7728 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7729 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7730 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7731 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7732 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7733 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 7734 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d 7735 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 7736 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e 7737 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 7738 #define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7739 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff 7740 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 7741 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 7742 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe 7743 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 7744 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 7745 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 7746 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 7747 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 7748 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 7749 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 7750 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 7751 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 7752 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c 7753 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 7754 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d 7755 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 7756 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e 7757 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 7758 #define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f 7759 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7760 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7761 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7762 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7763 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7764 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7765 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7766 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7767 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 7768 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d 7769 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 7770 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e 7771 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 7772 #define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f 7773 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff 7774 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 7775 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 7776 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe 7777 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 7778 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 7779 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 7780 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 7781 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 7782 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 7783 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 7784 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 7785 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 7786 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c 7787 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 7788 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7789 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 7790 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e 7791 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 7792 #define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f 7793 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7794 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7795 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7796 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7797 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7798 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7799 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7800 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7801 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 7802 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d 7803 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 7804 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e 7805 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 7806 #define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f 7807 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff 7808 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 7809 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 7810 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe 7811 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 7812 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 7813 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 7814 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 7815 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 7816 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 7817 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 7818 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b 7819 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 7820 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c 7821 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 7822 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7823 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 7824 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e 7825 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 7826 #define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f 7827 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe 7828 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 7829 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 7830 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb 7831 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 7832 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 7833 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 7834 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 7835 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 7836 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d 7837 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 7838 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e 7839 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 7840 #define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f 7841 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 7842 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 7843 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 7844 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 7845 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 7846 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 7847 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 7848 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 7849 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 7850 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 7851 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 7852 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 7853 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 7854 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 7855 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 7856 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 7857 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 7858 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 7859 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 7860 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc 7861 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 7862 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 7863 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 7864 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 7865 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 7866 #define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 7867 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 7868 #define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 7869 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 7870 #define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a 7871 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 7872 #define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b 7873 #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 7874 #define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c 7875 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 7876 #define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d 7877 #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 7878 #define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e 7879 #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 7880 #define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f 7881 #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff 7882 #define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 7883 #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 7884 #define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 7885 #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 7886 #define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd 7887 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 7888 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 7889 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 7890 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 7891 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 7892 #define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 7893 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 7894 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 7895 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 7896 #define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 7897 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 7898 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a 7899 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 7900 #define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b 7901 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 7902 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c 7903 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 7904 #define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d 7905 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 7906 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e 7907 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 7908 #define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7909 #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 7910 #define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 7911 #define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 7912 #define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 7913 #define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 7914 #define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 7915 #define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 7916 #define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 7917 #define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 7918 #define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 7919 #define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 7920 #define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 7921 #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 7922 #define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 7923 #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 7924 #define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc 7925 #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 7926 #define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe 7927 #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 7928 #define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf 7929 #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 7930 #define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 7931 #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 7932 #define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 7933 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 7934 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 7935 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 7936 #define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 7937 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 7938 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 7939 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 7940 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d 7941 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 7942 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e 7943 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 7944 #define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f 7945 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f 7946 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 7947 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 7948 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 7949 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 7950 #define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc 7951 #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 7952 #define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 7953 #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 7954 #define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 7955 #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 7956 #define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 7957 #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 7958 #define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 7959 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 7960 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 7961 #define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 7962 #define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e 7963 #define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 7964 #define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f 7965 #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff 7966 #define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 7967 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 7968 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 7969 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 7970 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 7971 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 7972 #define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a 7973 #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 7974 #define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f 7975 #define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f 7976 #define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 7977 #define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 7978 #define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 7979 #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 7980 #define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 7981 #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 7982 #define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd 7983 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 7984 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 7985 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 7986 #define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 7987 #define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 7988 #define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 7989 #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 7990 #define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 7991 #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 7992 #define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c 7993 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 7994 #define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d 7995 #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 7996 #define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e 7997 #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 7998 #define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f 7999 #define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f 8000 #define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 8001 #define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 8002 #define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 8003 #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 8004 #define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 8005 #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 8006 #define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd 8007 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 8008 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 8009 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 8010 #define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 8011 #define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 8012 #define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 8013 #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 8014 #define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 8015 #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 8016 #define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c 8017 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 8018 #define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d 8019 #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 8020 #define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e 8021 #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 8022 #define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f 8023 #define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f 8024 #define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 8025 #define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 8026 #define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 8027 #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 8028 #define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 8029 #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 8030 #define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd 8031 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 8032 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 8033 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 8034 #define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 8035 #define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 8036 #define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 8037 #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 8038 #define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 8039 #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 8040 #define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c 8041 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 8042 #define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d 8043 #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 8044 #define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e 8045 #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 8046 #define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f 8047 #define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f 8048 #define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 8049 #define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 8050 #define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 8051 #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 8052 #define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 8053 #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 8054 #define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd 8055 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 8056 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 8057 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 8058 #define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 8059 #define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 8060 #define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 8061 #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 8062 #define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b 8063 #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 8064 #define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c 8065 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 8066 #define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d 8067 #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 8068 #define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e 8069 #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 8070 #define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f 8071 #define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f 8072 #define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 8073 #define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 8074 #define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 8075 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 8076 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 8077 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 8078 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc 8079 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 8080 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 8081 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 8082 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a 8083 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 8084 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c 8085 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 8086 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e 8087 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 8088 #define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f 8089 #define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f 8090 #define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 8091 #define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 8092 #define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 8093 #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 8094 #define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa 8095 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 8096 #define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf 8097 #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 8098 #define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 8099 #define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 8100 #define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 8101 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 8102 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 8103 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 8104 #define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 8105 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 8106 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 8107 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 8108 #define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c 8109 #define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f 8110 #define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 8111 #define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 8112 #define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 8113 #define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 8114 #define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 8115 #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 8116 #define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf 8117 #define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 8118 #define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 8119 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 8120 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 8121 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 8122 #define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a 8123 #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff 8124 #define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 8125 #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 8126 #define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 8127 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 8128 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc 8129 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 8130 #define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd 8131 #define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 8132 #define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe 8133 #define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 8134 #define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 8135 #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 8136 #define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 8137 #define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 8138 #define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 8139 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 8140 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 8141 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 8142 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a 8143 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 8144 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b 8145 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 8146 #define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c 8147 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 8148 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d 8149 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 8150 #define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e 8151 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 8152 #define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f 8153 #define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 8154 #define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 8155 #define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c 8156 #define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 8157 #define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 8158 #define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 8159 #define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 8160 #define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe 8161 #define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 8162 #define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf 8163 #define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 8164 #define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 8165 #define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 8166 #define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 8167 #define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 8168 #define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 8169 #define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 8170 #define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 8171 #define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 8172 #define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 8173 #define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 8174 #define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 8175 #define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 8176 #define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c 8177 #define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 8178 #define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d 8179 #define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 8180 #define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e 8181 #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 8182 #define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f 8183 #define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff 8184 #define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 8185 #define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 8186 #define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 8187 #define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff 8188 #define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 8189 #define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 8190 #define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 8191 #define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff 8192 #define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 8193 #define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 8194 #define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 8195 #define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff 8196 #define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 8197 #define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 8198 #define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe 8199 #define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 8200 #define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf 8201 #define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 8202 #define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 8203 #define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 8204 #define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 8205 #define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 8206 #define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 8207 #define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 8208 #define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 8209 #define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 8210 #define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 8211 #define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 8212 #define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a 8213 #define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 8214 #define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d 8215 #define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 8216 #define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f 8217 #define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff 8218 #define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 8219 #define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 8220 #define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe 8221 #define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 8222 #define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c 8223 #define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 8224 #define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e 8225 #define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 8226 #define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f 8227 #define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 8228 #define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 8229 #define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc 8230 #define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 8231 #define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 8232 #define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 8233 #define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc 8234 #define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 8235 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 8236 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 8237 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 8238 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 8239 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 8240 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 8241 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 8242 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 8243 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 8244 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 8245 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 8246 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 8247 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 8248 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 8249 #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 8250 #define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 8251 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 8252 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa 8253 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 8254 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb 8255 #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 8256 #define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc 8257 #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 8258 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe 8259 #define COMPUTE_DIM_X__SIZE_MASK 0xffffffff 8260 #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 8261 #define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff 8262 #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 8263 #define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff 8264 #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 8265 #define COMPUTE_START_X__START_MASK 0xffffffff 8266 #define COMPUTE_START_X__START__SHIFT 0x0 8267 #define COMPUTE_START_Y__START_MASK 0xffffffff 8268 #define COMPUTE_START_Y__START__SHIFT 0x0 8269 #define COMPUTE_START_Z__START_MASK 0xffffffff 8270 #define COMPUTE_START_Z__START__SHIFT 0x0 8271 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff 8272 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 8273 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 8274 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 8275 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff 8276 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 8277 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 8278 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 8279 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff 8280 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 8281 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 8282 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 8283 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 8284 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 8285 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 8286 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 8287 #define COMPUTE_PGM_LO__DATA_MASK 0xffffffff 8288 #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 8289 #define COMPUTE_PGM_HI__DATA_MASK 0xff 8290 #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 8291 #define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 8292 #define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 8293 #define COMPUTE_TBA_LO__DATA_MASK 0xffffffff 8294 #define COMPUTE_TBA_LO__DATA__SHIFT 0x0 8295 #define COMPUTE_TBA_HI__DATA_MASK 0xff 8296 #define COMPUTE_TBA_HI__DATA__SHIFT 0x0 8297 #define COMPUTE_TMA_LO__DATA_MASK 0xffffffff 8298 #define COMPUTE_TMA_LO__DATA__SHIFT 0x0 8299 #define COMPUTE_TMA_HI__DATA_MASK 0xff 8300 #define COMPUTE_TMA_HI__DATA__SHIFT 0x0 8301 #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f 8302 #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 8303 #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 8304 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 8305 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 8306 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa 8307 #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 8308 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc 8309 #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 8310 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 8311 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 8312 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 8313 #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 8314 #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 8315 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 8316 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 8317 #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 8318 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 8319 #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 8320 #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 8321 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 8322 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 8323 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e 8324 #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 8325 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 8326 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 8327 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 8328 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 8329 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 8330 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 8331 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 8332 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 8333 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 8334 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa 8335 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 8336 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb 8337 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 8338 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd 8339 #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 8340 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf 8341 #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 8342 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 8343 #define COMPUTE_VMID__DATA_MASK 0xf 8344 #define COMPUTE_VMID__DATA__SHIFT 0x0 8345 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff 8346 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 8347 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 8348 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc 8349 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 8350 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 8351 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 8352 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 8353 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 8354 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 8355 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 8356 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 8357 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff 8358 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 8359 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 8360 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 8361 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff 8362 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 8363 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 8364 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 8365 #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff 8366 #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 8367 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 8368 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 8369 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff 8370 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 8371 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 8372 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 8373 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff 8374 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 8375 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 8376 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 8377 #define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff 8378 #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 8379 #define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff 8380 #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 8381 #define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff 8382 #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 8383 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 8384 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 8385 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 8386 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 8387 #define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 8388 #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 8389 #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 8390 #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 8391 #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 8392 #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 8393 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0 8394 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 8395 #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff 8396 #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 8397 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff 8398 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 8399 #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff 8400 #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 8401 #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000 8402 #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e 8403 #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000 8404 #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f 8405 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff 8406 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 8407 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff 8408 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 8409 #define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1 8410 #define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0 8411 #define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6 8412 #define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1 8413 #define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff 8414 #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 8415 #define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff 8416 #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 8417 #define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff 8418 #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 8419 #define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff 8420 #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 8421 #define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff 8422 #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 8423 #define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff 8424 #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 8425 #define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff 8426 #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 8427 #define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff 8428 #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 8429 #define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff 8430 #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 8431 #define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff 8432 #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 8433 #define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff 8434 #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 8435 #define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff 8436 #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 8437 #define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff 8438 #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 8439 #define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff 8440 #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 8441 #define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff 8442 #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 8443 #define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff 8444 #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 8445 #define COMPUTE_NOWHERE__DATA_MASK 0xffffffff 8446 #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 8447 #define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff 8448 #define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 8449 #define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 8450 #define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 8451 #define CSPRIV_CONNECT__VMID_MASK 0x3c000000 8452 #define CSPRIV_CONNECT__VMID__SHIFT 0x1a 8453 #define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 8454 #define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f 8455 #define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff 8456 #define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 8457 #define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff 8458 #define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 8459 #define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff 8460 #define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 8461 #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff 8462 #define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 8463 #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 8464 #define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc 8465 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 8466 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 8467 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 8468 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 8469 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 8470 #define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a 8471 #define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 8472 #define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b 8473 #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 8474 #define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c 8475 #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f 8476 #define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 8477 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 8478 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 8479 #define RLC_CNTL__FORCE_RETRY_MASK 0x2 8480 #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 8481 #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 8482 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 8483 #define RLC_CNTL__RLC_STEP_F32_MASK 0x8 8484 #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 8485 #define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 8486 #define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 8487 #define RLC_CNTL__RESERVED_MASK 0xffffff00 8488 #define RLC_CNTL__RESERVED__SHIFT 0x8 8489 #define RLC_DEBUG_SELECT__SELECT_MASK 0xff 8490 #define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 8491 #define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 8492 #define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 8493 #define RLC_DEBUG__DATA_MASK 0xffffffff 8494 #define RLC_DEBUG__DATA__SHIFT 0x0 8495 #define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 8496 #define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 8497 #define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 8498 #define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 8499 #define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 8500 #define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 8501 #define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 8502 #define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 8503 #define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 8504 #define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 8505 #define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 8506 #define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 8507 #define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 8508 #define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd 8509 #define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 8510 #define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 8511 #define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 8512 #define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 8513 #define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 8514 #define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a 8515 #define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 8516 #define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b 8517 #define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 8518 #define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c 8519 #define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 8520 #define RLC_MC_CNTL__RESERVED__SHIFT 0x1d 8521 #define RLC_STAT__RLC_BUSY_MASK 0x1 8522 #define RLC_STAT__RLC_BUSY__SHIFT 0x0 8523 #define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 8524 #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 8525 #define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 8526 #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 8527 #define RLC_STAT__RESERVED_MASK 0xfffffff8 8528 #define RLC_STAT__RESERVED__SHIFT 0x3 8529 #define RLC_SAFE_MODE__CMD_MASK 0x1 8530 #define RLC_SAFE_MODE__CMD__SHIFT 0x0 8531 #define RLC_SAFE_MODE__MESSAGE_MASK 0x1e 8532 #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 8533 #define RLC_SAFE_MODE__RESERVED1_MASK 0xe0 8534 #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 8535 #define RLC_SAFE_MODE__RESPONSE_MASK 0xf00 8536 #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 8537 #define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000 8538 #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc 8539 #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1 8540 #define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0 8541 #define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe 8542 #define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1 8543 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 8544 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 8545 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 8546 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 8547 #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c 8548 #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 8549 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80 8550 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 8551 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 8552 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 8553 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 8554 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 8555 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 8556 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 8557 #define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff 8558 #define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 8559 #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1 8560 #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 8561 #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e 8562 #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 8563 #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0 8564 #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 8565 #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00 8566 #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 8567 #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000 8568 #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc 8569 #define RLC_SMU_SAFE_MODE__CMD_MASK 0x1 8570 #define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 8571 #define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e 8572 #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 8573 #define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0 8574 #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 8575 #define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00 8576 #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 8577 #define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000 8578 #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc 8579 #define RLC_RLCV_COMMAND__CMD_MASK 0xf 8580 #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 8581 #define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0 8582 #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 8583 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1 8584 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 8585 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 8586 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 8587 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 8588 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 8589 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff 8590 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 8591 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff 8592 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 8593 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 8594 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 8595 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 8596 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 8597 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 8598 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 8599 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 8600 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 8601 #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf 8602 #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 8603 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 8604 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8605 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 8606 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 8607 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 8608 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 8609 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 8610 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 8611 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 8612 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 8613 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 8614 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 8615 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 8616 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 8617 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 8618 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 8619 #define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 8620 #define RLC_LB_CNTL__RESERVED__SHIFT 0xc 8621 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff 8622 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 8623 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff 8624 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 8625 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff 8626 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 8627 #define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff 8628 #define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0 8629 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff 8630 #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 8631 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1 8632 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0 8633 #define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe 8634 #define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1 8635 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10 8636 #define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4 8637 #define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0 8638 #define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5 8639 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff 8640 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 8641 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 8642 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 8643 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 8644 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 8645 #define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff 8646 #define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 8647 #define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300 8648 #define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8 8649 #define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00 8650 #define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa 8651 #define RLC_GPM_DEBUG__DATA_MASK 0xffffffff 8652 #define RLC_GPM_DEBUG__DATA__SHIFT 0x0 8653 #define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 8654 #define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 8655 #define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 8656 #define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc 8657 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 8658 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 8659 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 8660 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc 8661 #define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 8662 #define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 8663 #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 8664 #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 8665 #define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1 8666 #define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0 8667 #define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2 8668 #define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1 8669 #define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c 8670 #define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2 8671 #define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80 8672 #define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7 8673 #define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000 8674 #define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18 8675 #define RLC_ROM_CNTL__USE_ROM_MASK 0x1 8676 #define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0 8677 #define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2 8678 #define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1 8679 #define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4 8680 #define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2 8681 #define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8 8682 #define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3 8683 #define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10 8684 #define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4 8685 #define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0 8686 #define RLC_ROM_CNTL__RESERVED__SHIFT 0x5 8687 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff 8688 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 8689 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff 8690 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 8691 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 8692 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 8693 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe 8694 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 8695 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff 8696 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 8697 #define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 8698 #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 8699 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 8700 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 8701 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 8702 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 8703 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 8704 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 8705 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 8706 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 8707 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20 8708 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 8709 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40 8710 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 8711 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80 8712 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 8713 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100 8714 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 8715 #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200 8716 #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 8717 #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400 8718 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa 8719 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800 8720 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb 8721 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000 8722 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc 8723 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000 8724 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd 8725 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000 8726 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe 8727 #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000 8728 #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf 8729 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000 8730 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 8731 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000 8732 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 8733 #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000 8734 #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 8735 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f 8736 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 8737 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 8738 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 8739 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff 8740 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 8741 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 8742 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 8743 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 8744 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 8745 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 8746 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 8747 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 8748 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 8749 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10 8750 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 8751 #define RLC_PG_CNTL__RESERVED_MASK 0x3fe0 8752 #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 8753 #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000 8754 #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe 8755 #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000 8756 #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf 8757 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 8758 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 8759 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 8760 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 8761 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 8762 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 8763 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000 8764 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 8765 #define RLC_PG_CNTL__QUICK_PG_ENABLE_MASK 0x100000 8766 #define RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT 0x14 8767 #define RLC_PG_CNTL__RESERVED1_MASK 0xe00000 8768 #define RLC_PG_CNTL__RESERVED1__SHIFT 0x15 8769 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff 8770 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 8771 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 8772 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 8773 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 8774 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 8775 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 8776 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 8777 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 8778 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 8779 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 8780 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 8781 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 8782 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 8783 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 8784 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 8785 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 8786 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 8787 #define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf 8788 #define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 8789 #define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0 8790 #define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4 8791 #define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700 8792 #define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8 8793 #define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800 8794 #define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb 8795 #define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf 8796 #define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 8797 #define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0 8798 #define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4 8799 #define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700 8800 #define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8 8801 #define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800 8802 #define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb 8803 #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff 8804 #define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 8805 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 8806 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 8807 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 8808 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 8809 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc 8810 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 8811 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 8812 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 8813 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 8814 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b 8815 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 8816 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c 8817 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 8818 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 8819 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000 8820 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f 8821 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf 8822 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 8823 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 8824 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 8825 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 8826 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 8827 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 8828 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc 8829 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 8830 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 8831 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 8832 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c 8833 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff 8834 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 8835 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff 8836 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 8837 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff 8838 #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 8839 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 8840 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 8841 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 8842 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 8843 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 8844 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 8845 #define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff 8846 #define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 8847 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff 8848 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 8849 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff 8850 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 8851 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 8852 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 8853 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe 8854 #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 8855 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 8856 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 8857 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 8858 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 8859 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff 8860 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 8861 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 8862 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 8863 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 8864 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 8865 #define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 8866 #define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 8867 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff 8868 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 8869 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff 8870 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 8871 #define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 8872 #define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 8873 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 8874 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 8875 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 8876 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 8877 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 8878 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 8879 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 8880 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 8881 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 8882 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 8883 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 8884 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 8885 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe 8886 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 8887 #define RLC_SMU_PG_CTRL__START_PG_MASK 0x1 8888 #define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0 8889 #define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe 8890 #define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1 8891 #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1 8892 #define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0 8893 #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe 8894 #define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1 8895 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf 8896 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 8897 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 8898 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 8899 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 8900 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 8901 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 8902 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 8903 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 8904 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa 8905 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800 8906 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb 8907 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000 8908 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf 8909 #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000 8910 #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11 8911 #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff 8912 #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 8913 #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff 8914 #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 8915 #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff 8916 #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 8917 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff 8918 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 8919 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff 8920 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 8921 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 8922 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 8923 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000 8924 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 8925 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000 8926 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 8927 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000 8928 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 8929 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000 8930 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 8931 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000 8932 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 8933 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000 8934 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 8935 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000 8936 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 8937 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000 8938 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18 8939 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff 8940 #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 8941 #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 8942 #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 8943 #define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 8944 #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 8945 #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 8946 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa 8947 #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 8948 #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb 8949 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 8950 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc 8951 #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 8952 #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd 8953 #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000 8954 #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe 8955 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000 8956 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf 8957 #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000 8958 #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 8959 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000 8960 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a 8961 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000 8962 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b 8963 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 8964 #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c 8965 #define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff 8966 #define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 8967 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff 8968 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 8969 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff 8970 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 8971 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 8972 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 8973 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000 8974 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 8975 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000 8976 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 8977 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000 8978 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 8979 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000 8980 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 8981 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000 8982 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 8983 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000 8984 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 8985 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000 8986 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 8987 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000 8988 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18 8989 #define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff 8990 #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 8991 #define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff 8992 #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 8993 #define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff 8994 #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 8995 #define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff 8996 #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 8997 #define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff 8998 #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 8999 #define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff 9000 #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 9001 #define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff 9002 #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 9003 #define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff 9004 #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 9005 #define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff 9006 #define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0 9007 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff 9008 #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 9009 #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 9010 #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 9011 #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff 9012 #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 9013 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff 9014 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 9015 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf 9016 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 9017 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 9018 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 9019 #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 9020 #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 9021 #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 9022 #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc 9023 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 9024 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 9025 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 9026 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 9027 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 9028 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 9029 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 9030 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 9031 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf 9032 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 9033 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 9034 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 9035 #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 9036 #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 9037 #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 9038 #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc 9039 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 9040 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 9041 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 9042 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 9043 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 9044 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 9045 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 9046 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 9047 #define RLC_GPR_REG1__DATA_MASK 0xffffffff 9048 #define RLC_GPR_REG1__DATA__SHIFT 0x0 9049 #define RLC_GPR_REG2__DATA_MASK 0xffffffff 9050 #define RLC_GPR_REG2__DATA__SHIFT 0x0 9051 #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1 9052 #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 9053 #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2 9054 #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 9055 #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4 9056 #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 9057 #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78 9058 #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 9059 #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80 9060 #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 9061 #define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000 9062 #define RLC_MGCG_CTRL__SPARE__SHIFT 0xf 9063 #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1 9064 #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 9065 #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2 9066 #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 9067 #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4 9068 #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 9069 #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8 9070 #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 9071 #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0 9072 #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 9073 #define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf 9074 #define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 9075 #define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 9076 #define RLC_SPM_VMID__RESERVED__SHIFT 0x4 9077 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 9078 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 9079 #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe 9080 #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 9081 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 9082 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 9083 #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe 9084 #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 9085 #define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff 9086 #define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 9087 #define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 9088 #define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 9089 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 9090 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf 9091 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 9092 #define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 9093 #define RLC_SPM_DEBUG__DATA_MASK 0xffffffff 9094 #define RLC_SPM_DEBUG__DATA__SHIFT 0x0 9095 #define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff 9096 #define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0 9097 #define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff 9098 #define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 9099 #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff 9100 #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 9101 #define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff 9102 #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 9103 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff 9104 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 9105 #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff 9106 #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 9107 #define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff 9108 #define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 9109 #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff 9110 #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 9111 #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff 9112 #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 9113 #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1 9114 #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 9115 #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2 9116 #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 9117 #define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc 9118 #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 9119 #define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff 9120 #define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0 9121 #define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 9122 #define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8 9123 #define RLC_SRM_DEBUG__DATA_MASK 0xffffffff 9124 #define RLC_SRM_DEBUG__DATA__SHIFT 0x0 9125 #define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff 9126 #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 9127 #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00 9128 #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa 9129 #define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff 9130 #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 9131 #define RLC_SRM_GPM_COMMAND__OP_MASK 0x1 9132 #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 9133 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2 9134 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 9135 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c 9136 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 9137 #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0 9138 #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 9139 #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000 9140 #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 9141 #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000 9142 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d 9143 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000 9144 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f 9145 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 9146 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 9147 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2 9148 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 9149 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc 9150 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 9151 #define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1 9152 #define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 9153 #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe 9154 #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 9155 #define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0 9156 #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 9157 #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000 9158 #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 9159 #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000 9160 #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c 9161 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000 9162 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f 9163 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 9164 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 9165 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2 9166 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 9167 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc 9168 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 9169 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff 9170 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 9171 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000 9172 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 9173 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff 9174 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 9175 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000 9176 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 9177 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff 9178 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 9179 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000 9180 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 9181 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff 9182 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 9183 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000 9184 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 9185 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff 9186 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 9187 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000 9188 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 9189 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff 9190 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 9191 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000 9192 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 9193 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff 9194 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 9195 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000 9196 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 9197 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff 9198 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 9199 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000 9200 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 9201 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff 9202 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 9203 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff 9204 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 9205 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff 9206 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 9207 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff 9208 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 9209 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff 9210 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 9211 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff 9212 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 9213 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff 9214 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 9215 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff 9216 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 9217 #define RLC_SRM_STAT__SRM_STATUS_MASK 0x1 9218 #define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0 9219 #define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe 9220 #define RLC_SRM_STAT__RESERVED__SHIFT 0x1 9221 #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1 9222 #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 9223 #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe 9224 #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 9225 #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff 9226 #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 9227 #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff 9228 #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 9229 #define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff 9230 #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 9231 #define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff 9232 #define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0 9233 #define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff 9234 #define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0 9235 #define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff 9236 #define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0 9237 #define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff 9238 #define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0 9239 #define RLC_SMU_COMMAND__CMD_MASK 0xffffffff 9240 #define RLC_SMU_COMMAND__CMD__SHIFT 0x0 9241 #define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff 9242 #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 9243 #define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00 9244 #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 9245 #define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000 9246 #define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 9247 #define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000 9248 #define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 9249 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff 9250 #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 9251 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 9252 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc 9253 #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 9254 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe 9255 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 9256 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 9257 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff 9258 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 9259 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff 9260 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 9261 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 9262 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 9263 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff 9264 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 9265 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff 9266 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 9267 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 9268 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 9269 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 9270 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb 9271 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 9272 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 9273 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 9274 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 9275 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 9276 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a 9277 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 9278 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f 9279 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff 9280 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 9281 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff 9282 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 9283 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9284 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9285 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9286 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9287 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9288 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9289 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9290 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9291 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9292 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9293 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9294 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9295 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9296 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9297 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9298 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9299 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9300 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9301 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9302 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9303 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9304 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9305 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9306 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9307 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9308 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9309 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9310 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9311 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9312 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9313 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9314 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9315 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9316 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9317 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9318 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9319 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9320 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9321 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9322 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9323 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9324 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9325 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9326 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9327 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9328 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9329 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9330 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9331 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9332 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9333 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9334 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9335 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9336 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9337 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9338 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9339 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9340 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9341 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9342 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9343 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9344 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9345 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9346 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9347 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9348 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9349 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9350 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9351 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9352 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9353 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9354 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9355 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff 9356 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 9357 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff 9358 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 9359 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff 9360 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 9361 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff 9362 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 9363 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9364 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9365 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9366 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9367 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9368 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9369 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9370 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9371 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9372 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9373 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9374 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9375 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff 9376 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 9377 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 9378 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 9379 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1 9380 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 9381 #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe 9382 #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 9383 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000 9384 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 9385 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf 9386 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 9387 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10 9388 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 9389 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20 9390 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 9391 #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0 9392 #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 9393 #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00 9394 #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 9395 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000 9396 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 9397 #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000 9398 #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 9399 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf 9400 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 9401 #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0 9402 #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 9403 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f 9404 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 9405 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80 9406 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 9407 #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300 9408 #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 9409 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00 9410 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa 9411 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff 9412 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 9413 #define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff 9414 #define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0 9415 #define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00 9416 #define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8 9417 #define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000 9418 #define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc 9419 #define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff 9420 #define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0 9421 #define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000 9422 #define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10 9423 #define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff 9424 #define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0 9425 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff 9426 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0 9427 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00 9428 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8 9429 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000 9430 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10 9431 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000 9432 #define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18 9433 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff 9434 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0 9435 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00 9436 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8 9437 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000 9438 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10 9439 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000 9440 #define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18 9441 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff 9442 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0 9443 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00 9444 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8 9445 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000 9446 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10 9447 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000 9448 #define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18 9449 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff 9450 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0 9451 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00 9452 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8 9453 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000 9454 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10 9455 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000 9456 #define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18 9457 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf 9458 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 9459 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 9460 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 9461 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 9462 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 9463 #define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf 9464 #define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0 9465 #define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0 9466 #define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4 9467 #define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700 9468 #define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8 9469 #define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800 9470 #define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb 9471 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff 9472 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 9473 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000 9474 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc 9475 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff 9476 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 9477 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff 9478 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 9479 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 9480 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 9481 #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff 9482 #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 9483 #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1 9484 #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 9485 #define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe 9486 #define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 9487 #define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1 9488 #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 9489 #define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe 9490 #define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 9491 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1 9492 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 9493 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe 9494 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 9495 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100 9496 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 9497 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00 9498 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 9499 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000 9500 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc 9501 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000 9502 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd 9503 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1 9504 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 9505 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe 9506 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 9507 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100 9508 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 9509 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00 9510 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 9511 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000 9512 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc 9513 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000 9514 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd 9515 #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff 9516 #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 9517 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff 9518 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 9519 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000 9520 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 9521 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000 9522 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f 9523 #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff 9524 #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 9525 #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff 9526 #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 9527 #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff 9528 #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 9529 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff 9530 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 9531 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff 9532 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 9533 #define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff 9534 #define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0 9535 #define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff 9536 #define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 9537 #define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff 9538 #define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 9539 #define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff 9540 #define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0 9541 #define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff 9542 #define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0 9543 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f 9544 #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 9545 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 9546 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 9547 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 9548 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa 9549 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 9550 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd 9551 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 9552 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 9553 #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 9554 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 9555 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000 9556 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 9557 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000 9558 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 9559 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000 9560 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 9561 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9562 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9563 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000 9564 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 9565 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000 9566 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 9567 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f 9568 #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 9569 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 9570 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 9571 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 9572 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa 9573 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 9574 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd 9575 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 9576 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 9577 #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 9578 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 9579 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000 9580 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 9581 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000 9582 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 9583 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000 9584 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 9585 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9586 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9587 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000 9588 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 9589 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000 9590 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 9591 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f 9592 #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 9593 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 9594 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 9595 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 9596 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa 9597 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 9598 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd 9599 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 9600 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 9601 #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 9602 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 9603 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000 9604 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 9605 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000 9606 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 9607 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000 9608 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 9609 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9610 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9611 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000 9612 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 9613 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000 9614 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 9615 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f 9616 #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 9617 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 9618 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 9619 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 9620 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa 9621 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 9622 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd 9623 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 9624 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 9625 #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 9626 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 9627 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000 9628 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 9629 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000 9630 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 9631 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000 9632 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 9633 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9634 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9635 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000 9636 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 9637 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000 9638 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 9639 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f 9640 #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 9641 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 9642 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 9643 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 9644 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa 9645 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 9646 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd 9647 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 9648 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 9649 #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 9650 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 9651 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000 9652 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 9653 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000 9654 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 9655 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000 9656 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 9657 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9658 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9659 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000 9660 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 9661 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000 9662 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 9663 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f 9664 #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 9665 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 9666 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 9667 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 9668 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa 9669 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 9670 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd 9671 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 9672 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 9673 #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 9674 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 9675 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000 9676 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 9677 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000 9678 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 9679 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000 9680 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 9681 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9682 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9683 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000 9684 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 9685 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000 9686 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 9687 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f 9688 #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 9689 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 9690 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 9691 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 9692 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa 9693 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 9694 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd 9695 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 9696 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 9697 #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 9698 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 9699 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000 9700 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 9701 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000 9702 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 9703 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000 9704 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 9705 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9706 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9707 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000 9708 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 9709 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000 9710 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 9711 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f 9712 #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 9713 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 9714 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 9715 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 9716 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa 9717 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 9718 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd 9719 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 9720 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 9721 #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 9722 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 9723 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000 9724 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 9725 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000 9726 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 9727 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000 9728 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 9729 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9730 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9731 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000 9732 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 9733 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000 9734 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 9735 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f 9736 #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 9737 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 9738 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 9739 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 9740 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa 9741 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 9742 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd 9743 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 9744 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 9745 #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 9746 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 9747 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000 9748 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 9749 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000 9750 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 9751 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000 9752 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 9753 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9754 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9755 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000 9756 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 9757 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000 9758 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 9759 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f 9760 #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 9761 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 9762 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 9763 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 9764 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa 9765 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 9766 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd 9767 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 9768 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 9769 #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 9770 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 9771 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000 9772 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 9773 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000 9774 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 9775 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000 9776 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 9777 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9778 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9779 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000 9780 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 9781 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000 9782 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 9783 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f 9784 #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 9785 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 9786 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 9787 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 9788 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa 9789 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 9790 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd 9791 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 9792 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 9793 #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 9794 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 9795 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000 9796 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 9797 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000 9798 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 9799 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000 9800 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 9801 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9802 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9803 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000 9804 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 9805 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000 9806 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 9807 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f 9808 #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 9809 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 9810 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 9811 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 9812 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa 9813 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 9814 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd 9815 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 9816 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 9817 #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 9818 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 9819 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000 9820 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 9821 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000 9822 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 9823 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000 9824 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 9825 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9826 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9827 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000 9828 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 9829 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000 9830 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 9831 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f 9832 #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 9833 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 9834 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 9835 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 9836 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa 9837 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 9838 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd 9839 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 9840 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 9841 #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 9842 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 9843 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000 9844 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 9845 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000 9846 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 9847 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000 9848 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 9849 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9850 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9851 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000 9852 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 9853 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000 9854 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 9855 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f 9856 #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 9857 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 9858 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 9859 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 9860 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa 9861 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 9862 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd 9863 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 9864 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 9865 #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 9866 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 9867 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000 9868 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 9869 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000 9870 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 9871 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000 9872 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 9873 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9874 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9875 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000 9876 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 9877 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000 9878 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 9879 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f 9880 #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 9881 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 9882 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 9883 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 9884 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa 9885 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 9886 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd 9887 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 9888 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 9889 #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 9890 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 9891 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000 9892 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 9893 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000 9894 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 9895 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000 9896 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 9897 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9898 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9899 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000 9900 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 9901 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000 9902 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 9903 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f 9904 #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 9905 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 9906 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 9907 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 9908 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa 9909 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 9910 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd 9911 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 9912 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 9913 #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 9914 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 9915 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000 9916 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 9917 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000 9918 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 9919 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000 9920 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 9921 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9922 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9923 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000 9924 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 9925 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000 9926 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 9927 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f 9928 #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 9929 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 9930 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 9931 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 9932 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa 9933 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 9934 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd 9935 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 9936 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 9937 #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 9938 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 9939 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000 9940 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 9941 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000 9942 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 9943 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000 9944 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 9945 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9946 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9947 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000 9948 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 9949 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000 9950 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 9951 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f 9952 #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 9953 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 9954 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 9955 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 9956 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa 9957 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 9958 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd 9959 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 9960 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 9961 #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 9962 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 9963 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000 9964 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 9965 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000 9966 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 9967 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000 9968 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 9969 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9970 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9971 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000 9972 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 9973 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000 9974 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 9975 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f 9976 #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 9977 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 9978 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 9979 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 9980 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa 9981 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 9982 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd 9983 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 9984 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 9985 #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 9986 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 9987 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000 9988 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 9989 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000 9990 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 9991 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000 9992 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 9993 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000 9994 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 9995 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000 9996 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 9997 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000 9998 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 9999 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f 10000 #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 10001 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 10002 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 10003 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 10004 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa 10005 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 10006 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd 10007 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 10008 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 10009 #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 10010 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 10011 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000 10012 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 10013 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000 10014 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 10015 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000 10016 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 10017 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000 10018 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 10019 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000 10020 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 10021 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000 10022 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 10023 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f 10024 #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 10025 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 10026 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 10027 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 10028 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa 10029 #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 10030 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 10031 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000 10032 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 10033 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000 10034 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 10035 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000 10036 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 10037 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000 10038 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 10039 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000 10040 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 10041 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f 10042 #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 10043 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 10044 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 10045 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 10046 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa 10047 #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 10048 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 10049 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000 10050 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 10051 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000 10052 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 10053 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000 10054 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 10055 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000 10056 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 10057 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000 10058 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 10059 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f 10060 #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 10061 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 10062 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 10063 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 10064 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa 10065 #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 10066 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 10067 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000 10068 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 10069 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000 10070 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 10071 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000 10072 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 10073 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000 10074 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 10075 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000 10076 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 10077 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f 10078 #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 10079 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 10080 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 10081 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 10082 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa 10083 #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 10084 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 10085 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000 10086 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 10087 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000 10088 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 10089 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000 10090 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 10091 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000 10092 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 10093 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000 10094 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 10095 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f 10096 #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 10097 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 10098 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 10099 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 10100 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa 10101 #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 10102 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 10103 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000 10104 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 10105 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000 10106 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 10107 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000 10108 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 10109 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000 10110 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 10111 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000 10112 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 10113 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f 10114 #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 10115 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 10116 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 10117 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 10118 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa 10119 #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 10120 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 10121 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000 10122 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 10123 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000 10124 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 10125 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000 10126 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 10127 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000 10128 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 10129 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000 10130 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 10131 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f 10132 #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 10133 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 10134 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 10135 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 10136 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa 10137 #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 10138 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 10139 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000 10140 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 10141 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000 10142 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 10143 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000 10144 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 10145 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000 10146 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 10147 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000 10148 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 10149 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f 10150 #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 10151 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 10152 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 10153 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 10154 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa 10155 #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 10156 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 10157 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000 10158 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 10159 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000 10160 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 10161 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 10162 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 10163 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000 10164 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 10165 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000 10166 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 10167 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f 10168 #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 10169 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 10170 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 10171 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 10172 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa 10173 #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 10174 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 10175 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000 10176 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 10177 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000 10178 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 10179 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000 10180 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 10181 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000 10182 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 10183 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000 10184 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 10185 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f 10186 #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 10187 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 10188 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 10189 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 10190 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa 10191 #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 10192 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 10193 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000 10194 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 10195 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000 10196 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 10197 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000 10198 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 10199 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000 10200 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 10201 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000 10202 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 10203 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f 10204 #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 10205 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 10206 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 10207 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 10208 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa 10209 #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 10210 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 10211 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000 10212 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 10213 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000 10214 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 10215 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000 10216 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 10217 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000 10218 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 10219 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000 10220 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 10221 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f 10222 #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 10223 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 10224 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 10225 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 10226 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa 10227 #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 10228 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 10229 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000 10230 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 10231 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000 10232 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 10233 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000 10234 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 10235 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000 10236 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 10237 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000 10238 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 10239 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e 10240 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 10241 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 10242 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 10243 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 10244 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 10245 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 10246 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 10247 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 10248 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 10249 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 10250 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 10251 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 10252 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 10253 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 10254 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 10255 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 10256 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 10257 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 10258 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 10259 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 10260 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 10261 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 10262 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 10263 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 10264 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa 10265 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 10266 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb 10267 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 10268 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc 10269 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 10270 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd 10271 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 10272 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe 10273 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 10274 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf 10275 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 10276 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 10277 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 10278 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 10279 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 10280 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 10281 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 10282 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 10283 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 10284 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 10285 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 10286 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 10287 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 10288 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 10289 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 10290 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 10291 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 10292 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 10293 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 10294 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 10295 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 10296 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa 10297 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 10298 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb 10299 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 10300 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc 10301 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 10302 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd 10303 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 10304 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe 10305 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 10306 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf 10307 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 10308 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 10309 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 10310 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 10311 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c 10312 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 10313 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 10314 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 10315 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 10316 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 10317 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 10318 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb 10319 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 10320 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe 10321 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f 10322 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 10323 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 10324 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 10325 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 10326 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe 10327 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 10328 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 10329 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 10330 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 10331 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 10332 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 10333 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 10334 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc 10335 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 10336 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 10337 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 10338 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 10339 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 10340 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 10341 #define SPI_TMPRING_SIZE__WAVES_MASK 0xfff 10342 #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 10343 #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 10344 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 10345 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf 10346 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 10347 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 10348 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 10349 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 10350 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 10351 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 10352 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc 10353 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf 10354 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 10355 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf 10356 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 10357 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 10358 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 10359 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 10360 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 10361 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 10362 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc 10363 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 10364 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 10365 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 10366 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 10367 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 10368 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 10369 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 10370 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c 10371 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 10372 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 10373 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 10374 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 10375 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 10376 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 10377 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 10378 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 10379 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 10380 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc 10381 #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 10382 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe 10383 #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 10384 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 10385 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 10386 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 10387 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff 10388 #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 10389 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 10390 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 10391 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff 10392 #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 10393 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 10394 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 10395 #define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 10396 #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 10397 #define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 10398 #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 10399 #define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 10400 #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 10401 #define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 10402 #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 10403 #define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 10404 #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 10405 #define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 10406 #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 10407 #define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 10408 #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 10409 #define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 10410 #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 10411 #define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 10412 #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 10413 #define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 10414 #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 10415 #define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 10416 #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 10417 #define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 10418 #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 10419 #define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 10420 #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 10421 #define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff 10422 #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 10423 #define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 10424 #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 10425 #define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 10426 #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 10427 #define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 10428 #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 10429 #define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff 10430 #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 10431 #define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 10432 #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 10433 #define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 10434 #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 10435 #define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 10436 #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 10437 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f 10438 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 10439 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80 10440 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 10441 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000 10442 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc 10443 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000 10444 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 10445 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000 10446 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 10447 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f 10448 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 10449 #define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80 10450 #define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7 10451 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000 10452 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc 10453 #define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000 10454 #define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11 10455 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000 10456 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 10457 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f 10458 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 10459 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f 10460 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 10461 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f 10462 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 10463 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f 10464 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 10465 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f 10466 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 10467 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f 10468 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 10469 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f 10470 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 10471 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f 10472 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 10473 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 10474 #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 10475 #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe 10476 #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 10477 #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 10478 #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 10479 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc 10480 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 10481 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 10482 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 10483 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 10484 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 10485 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 10486 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 10487 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 10488 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 10489 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 10490 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf 10491 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 10492 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 10493 #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff 10494 #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 10495 #define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 10496 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 10497 #define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff 10498 #define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 10499 #define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff 10500 #define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 10501 #define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff 10502 #define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 10503 #define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff 10504 #define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 10505 #define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff 10506 #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 10507 #define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff 10508 #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 10509 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 10510 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 10511 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 10512 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 10513 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 10514 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 10515 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 10516 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 10517 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 10518 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 10519 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 10520 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 10521 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf 10522 #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 10523 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 10524 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 10525 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 10526 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 10527 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 10528 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc 10529 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 10530 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf 10531 #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf 10532 #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 10533 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 10534 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 10535 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 10536 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 10537 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 10538 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc 10539 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 10540 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf 10541 #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf 10542 #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 10543 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 10544 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 10545 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 10546 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 10547 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 10548 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc 10549 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 10550 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf 10551 #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf 10552 #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 10553 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 10554 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 10555 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 10556 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 10557 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 10558 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc 10559 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 10560 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf 10561 #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf 10562 #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 10563 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 10564 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 10565 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 10566 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 10567 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 10568 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc 10569 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 10570 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf 10571 #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf 10572 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 10573 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 10574 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 10575 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 10576 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 10577 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 10578 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc 10579 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 10580 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf 10581 #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf 10582 #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 10583 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 10584 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 10585 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 10586 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 10587 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 10588 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc 10589 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 10590 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf 10591 #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf 10592 #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 10593 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 10594 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 10595 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 10596 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 10597 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 10598 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc 10599 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 10600 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf 10601 #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf 10602 #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 10603 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 10604 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 10605 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 10606 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 10607 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 10608 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc 10609 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 10610 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf 10611 #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf 10612 #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 10613 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 10614 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 10615 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 10616 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 10617 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 10618 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc 10619 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 10620 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf 10621 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf 10622 #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 10623 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 10624 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 10625 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 10626 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 10627 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 10628 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc 10629 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 10630 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf 10631 #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf 10632 #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 10633 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 10634 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 10635 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 10636 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 10637 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 10638 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc 10639 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 10640 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf 10641 #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf 10642 #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 10643 #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0 10644 #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 10645 #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00 10646 #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 10647 #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000 10648 #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc 10649 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000 10650 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf 10651 #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf 10652 #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 10653 #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0 10654 #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 10655 #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00 10656 #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 10657 #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000 10658 #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc 10659 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000 10660 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf 10661 #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf 10662 #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 10663 #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0 10664 #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 10665 #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00 10666 #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 10667 #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000 10668 #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc 10669 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000 10670 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf 10671 #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf 10672 #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 10673 #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0 10674 #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 10675 #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00 10676 #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 10677 #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000 10678 #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc 10679 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000 10680 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf 10681 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 10682 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 10683 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe 10684 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 10685 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 10686 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 10687 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 10688 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 10689 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 10690 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 10691 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe 10692 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 10693 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 10694 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 10695 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 10696 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 10697 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 10698 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 10699 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe 10700 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 10701 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 10702 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 10703 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 10704 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 10705 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 10706 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 10707 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe 10708 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 10709 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 10710 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 10711 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 10712 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 10713 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 10714 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 10715 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe 10716 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 10717 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 10718 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 10719 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 10720 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 10721 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 10722 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 10723 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe 10724 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 10725 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 10726 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 10727 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 10728 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 10729 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 10730 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 10731 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe 10732 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 10733 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 10734 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 10735 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 10736 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 10737 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 10738 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 10739 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe 10740 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 10741 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 10742 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 10743 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 10744 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 10745 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 10746 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 10747 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe 10748 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 10749 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 10750 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 10751 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 10752 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 10753 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 10754 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 10755 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe 10756 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 10757 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 10758 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 10759 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 10760 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 10761 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 10762 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 10763 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe 10764 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 10765 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 10766 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 10767 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 10768 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 10769 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 10770 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 10771 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe 10772 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 10773 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 10774 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 10775 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 10776 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 10777 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1 10778 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 10779 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe 10780 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 10781 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000 10782 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 10783 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000 10784 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 10785 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1 10786 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 10787 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe 10788 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 10789 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000 10790 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 10791 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000 10792 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 10793 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1 10794 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 10795 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe 10796 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 10797 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000 10798 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 10799 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000 10800 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 10801 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1 10802 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 10803 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe 10804 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 10805 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000 10806 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 10807 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000 10808 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 10809 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1 10810 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 10811 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2 10812 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 10813 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4 10814 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 10815 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000 10816 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e 10817 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000 10818 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f 10819 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 10820 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 10821 #define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3 10822 #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 10823 #define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc 10824 #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 10825 #define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30 10826 #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 10827 #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 10828 #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 10829 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff 10830 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 10831 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 10832 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 10833 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 10834 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 10835 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 10836 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 10837 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 10838 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a 10839 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 10840 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b 10841 #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 10842 #define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 10843 #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe 10844 #define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 10845 #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 10846 #define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 10847 #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 10848 #define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa 10849 #define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 10850 #define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 10851 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 10852 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 10853 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 10854 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 10855 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 10856 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 10857 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 10858 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 10859 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 10860 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 10861 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 10862 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 10863 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 10864 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 10865 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 10866 #define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 10867 #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 10868 #define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 10869 #define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 10870 #define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f 10871 #define SPI_DEBUG_READ__DATA_MASK 0xffffff 10872 #define SPI_DEBUG_READ__DATA__SHIFT 0x0 10873 #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1 10874 #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0 10875 #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2 10876 #define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1 10877 #define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4 10878 #define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2 10879 #define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8 10880 #define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 10881 #define SPI_EDC_CNT__SED_MASK 0xff 10882 #define SPI_EDC_CNT__SED__SHIFT 0x0 10883 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 10884 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 10885 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 10886 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 10887 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 10888 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 10889 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 10890 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 10891 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 10892 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 10893 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 10894 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 10895 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 10896 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 10897 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 10898 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 10899 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 10900 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 10901 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 10902 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 10903 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 10904 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 10905 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 10906 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 10907 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 10908 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 10909 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 10910 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 10911 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 10912 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 10913 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 10914 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 10915 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff 10916 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 10917 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 10918 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa 10919 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff 10920 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 10921 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 10922 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa 10923 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff 10924 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 10925 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff 10926 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 10927 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf 10928 #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 10929 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 10930 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 10931 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 10932 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 10933 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 10934 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc 10935 #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 10936 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 10937 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 10938 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 10939 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 10940 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 10941 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 10942 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c 10943 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 10944 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 10945 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 10946 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 10947 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 10948 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 10949 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 10950 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 10951 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 10952 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 10953 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 10954 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 10955 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 10956 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 10957 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 10958 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 10959 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 10960 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 10961 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 10962 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 10963 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 10964 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 10965 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 10966 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 10967 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf 10968 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 10969 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 10970 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 10971 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 10972 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 10973 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 10974 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 10975 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 10976 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 10977 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 10978 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 10979 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 10980 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa 10981 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 10982 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 10983 #define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 10984 #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 10985 #define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 10986 #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 10987 #define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 10988 #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 10989 #define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 10990 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 10991 #define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 10992 #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 10993 #define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 10994 #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 10995 #define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 10996 #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 10997 #define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 10998 #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 10999 #define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 11000 #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 11001 #define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 11002 #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 11003 #define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 11004 #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa 11005 #define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 11006 #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb 11007 #define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 11008 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc 11009 #define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 11010 #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd 11011 #define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 11012 #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe 11013 #define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 11014 #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf 11015 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 11016 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 11017 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 11018 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 11019 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 11020 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 11021 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 11022 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 11023 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 11024 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 11025 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 11026 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 11027 #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 11028 #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 11029 #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 11030 #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 11031 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf 11032 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 11033 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0 11034 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 11035 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf 11036 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 11037 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 11038 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 11039 #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 11040 #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc 11041 #define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 11042 #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 11043 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 11044 #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 11045 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 11046 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 11047 #define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 11048 #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 11049 #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 11050 #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 11051 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 11052 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 11053 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 11054 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 11055 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f 11056 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 11057 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 11058 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 11059 #define CGTS_RD_REG__READ_DATA_MASK 0x3fff 11060 #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 11061 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 11062 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 11063 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 11064 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 11065 #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f 11066 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 11067 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11068 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11069 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11070 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11071 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11072 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11073 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11074 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11075 #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 11076 #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 11077 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11078 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11079 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11080 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11081 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11082 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11083 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11084 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11085 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11086 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11087 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11088 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11089 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11090 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11091 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11092 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11093 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11094 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11095 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11096 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11097 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11098 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11099 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11100 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11101 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11102 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11103 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11104 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11105 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f 11106 #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 11107 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 11108 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11109 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11110 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11111 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11112 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11113 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11114 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11115 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 11116 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 11117 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 11118 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 11119 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 11120 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 11121 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 11122 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 11123 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 11124 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11125 #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f 11126 #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 11127 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11128 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11129 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11130 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11131 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11132 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11133 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11134 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11135 #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 11136 #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 11137 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11138 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11139 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11140 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11141 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11142 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11143 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11144 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11145 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f 11146 #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11147 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11148 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11149 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11150 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11151 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11152 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11153 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11154 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11155 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11156 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11157 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11158 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11159 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11160 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11161 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11162 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11163 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11164 #define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11165 #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f 11166 #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 11167 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11168 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11169 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11170 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11171 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11172 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11173 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11174 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11175 #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 11176 #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 11177 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11178 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11179 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11180 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11181 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11182 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11183 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11184 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11185 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11186 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11187 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11188 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11189 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11190 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11191 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11192 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11193 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11194 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11195 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11196 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11197 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11198 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11199 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11200 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11201 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11202 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11203 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11204 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11205 #define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f 11206 #define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 11207 #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11208 #define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11209 #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11210 #define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11211 #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11212 #define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11213 #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11214 #define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11215 #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f 11216 #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 11217 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11218 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11219 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11220 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11221 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11222 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11223 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11224 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11225 #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 11226 #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 11227 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11228 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11229 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11230 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11231 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11232 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11233 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11234 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11235 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f 11236 #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11237 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11238 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11239 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11240 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11241 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11242 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11243 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11244 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11245 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11246 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11247 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11248 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11249 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11250 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11251 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11252 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11253 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11254 #define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11255 #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f 11256 #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 11257 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11258 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11259 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11260 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11261 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11262 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11263 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11264 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11265 #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 11266 #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 11267 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11268 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11269 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11270 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11271 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11272 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11273 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11274 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11275 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11276 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11277 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11278 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11279 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11280 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11281 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11282 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11283 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11284 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11285 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11286 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11287 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11288 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11289 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11290 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11291 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11292 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11293 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11294 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11295 #define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f 11296 #define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 11297 #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11298 #define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11299 #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11300 #define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11301 #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11302 #define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11303 #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11304 #define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11305 #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f 11306 #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 11307 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11308 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11309 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11310 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11311 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11312 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11313 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11314 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11315 #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 11316 #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 11317 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11318 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11319 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11320 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11321 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11322 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11323 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11324 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11325 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f 11326 #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11327 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11328 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11329 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11330 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11331 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11332 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11333 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11334 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11335 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11336 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11337 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11338 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11339 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11340 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11341 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11342 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11343 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11344 #define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11345 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f 11346 #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 11347 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11348 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11349 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11350 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11351 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11352 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11353 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11354 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11355 #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 11356 #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 11357 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11358 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11359 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11360 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11361 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11362 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11363 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11364 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11365 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11366 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11367 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11368 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11369 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11370 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11371 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11372 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11373 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11374 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11375 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11376 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11377 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11378 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11379 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11380 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11381 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11382 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11383 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11384 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11385 #define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f 11386 #define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 11387 #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11388 #define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11389 #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11390 #define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11391 #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11392 #define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11393 #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11394 #define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11395 #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f 11396 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 11397 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11398 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11399 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11400 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11401 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11402 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11403 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11404 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11405 #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 11406 #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 11407 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11408 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11409 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11410 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11411 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11412 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11413 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11414 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11415 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f 11416 #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11417 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11418 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11419 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11420 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11421 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11422 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11423 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11424 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11425 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11426 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11427 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11428 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11429 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11430 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11431 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11432 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11433 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11434 #define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11435 #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f 11436 #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 11437 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11438 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11439 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11440 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11441 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11442 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11443 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11444 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11445 #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 11446 #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 11447 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11448 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11449 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11450 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11451 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11452 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11453 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11454 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11455 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11456 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11457 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11458 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11459 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11460 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11461 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11462 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11463 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11464 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11465 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11466 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11467 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11468 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11469 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11470 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11471 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11472 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11473 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11474 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11475 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f 11476 #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 11477 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 11478 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11479 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11480 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11481 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11482 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11483 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11484 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11485 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 11486 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 11487 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 11488 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 11489 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 11490 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 11491 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 11492 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 11493 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 11494 #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11495 #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f 11496 #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 11497 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11498 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11499 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11500 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11501 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11502 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11503 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11504 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11505 #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 11506 #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 11507 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11508 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11509 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11510 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11511 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11512 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11513 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11514 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11515 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f 11516 #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11517 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11518 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11519 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11520 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11521 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11522 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11523 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11524 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11525 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11526 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11527 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11528 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11529 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11530 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11531 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11532 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11533 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11534 #define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11535 #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f 11536 #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 11537 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11538 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11539 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11540 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11541 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11542 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11543 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11544 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11545 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 11546 #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 11547 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11548 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11549 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11550 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11551 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11552 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11553 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11554 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11555 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11556 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11557 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11558 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11559 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11560 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11561 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11562 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11563 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11564 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11565 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11566 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11567 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11568 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11569 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11570 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11571 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11572 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11573 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11574 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11575 #define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f 11576 #define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 11577 #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11578 #define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11579 #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11580 #define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11581 #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11582 #define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11583 #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11584 #define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11585 #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f 11586 #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 11587 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11588 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11589 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11590 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11591 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11592 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11593 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11594 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11595 #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 11596 #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 11597 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11598 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11599 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11600 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11601 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11602 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11603 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11604 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11605 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f 11606 #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11607 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11608 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11609 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11610 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11611 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11612 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11613 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11614 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11615 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11616 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11617 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11618 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11619 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11620 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11621 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11622 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11623 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11624 #define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11625 #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f 11626 #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 11627 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11628 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11629 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11630 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11631 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11632 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11633 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11634 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11635 #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 11636 #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 11637 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11638 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11639 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11640 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11641 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11642 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11643 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11644 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11645 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11646 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11647 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11648 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11649 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11650 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11651 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11652 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11653 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11654 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11655 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11656 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11657 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11658 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11659 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11660 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11661 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11662 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11663 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11664 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11665 #define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f 11666 #define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 11667 #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11668 #define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11669 #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11670 #define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11671 #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11672 #define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11673 #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11674 #define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11675 #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f 11676 #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 11677 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11678 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11679 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11680 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11681 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11682 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11683 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11684 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11685 #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 11686 #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 11687 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11688 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11689 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11690 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11691 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11692 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11693 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11694 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11695 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f 11696 #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11697 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11698 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11699 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11700 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11701 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11702 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11703 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11704 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11705 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11706 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11707 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11708 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11709 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11710 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11711 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11712 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11713 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11714 #define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11715 #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f 11716 #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 11717 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11718 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11719 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11720 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11721 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11722 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11723 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11724 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11725 #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 11726 #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 11727 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11728 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11729 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11730 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11731 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11732 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11733 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11734 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11735 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11736 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11737 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11738 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11739 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11740 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11741 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11742 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11743 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11744 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11745 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11746 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11747 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11748 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11749 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11750 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11751 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11752 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11753 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11754 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11755 #define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f 11756 #define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 11757 #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11758 #define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11759 #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11760 #define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11761 #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11762 #define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11763 #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11764 #define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11765 #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f 11766 #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 11767 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11768 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11769 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11770 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11771 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11772 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11773 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11774 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11775 #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 11776 #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 11777 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11778 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11779 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11780 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11781 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11782 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11783 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11784 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11785 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f 11786 #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11787 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11788 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11789 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11790 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11791 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11792 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11793 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11794 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11795 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11796 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11797 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11798 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11799 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11800 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11801 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11802 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11803 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11804 #define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11805 #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f 11806 #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 11807 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11808 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11809 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11810 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11811 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11812 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11813 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11814 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11815 #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 11816 #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 11817 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11818 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11819 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11820 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11821 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11822 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11823 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11824 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11825 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11826 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11827 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11828 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11829 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11830 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11831 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11832 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11833 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11834 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11835 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11836 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11837 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11838 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11839 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11840 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11841 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11842 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11843 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11844 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11845 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f 11846 #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 11847 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 11848 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11849 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11850 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11851 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11852 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11853 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11854 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11855 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 11856 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 11857 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 11858 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 11859 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 11860 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 11861 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 11862 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 11863 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 11864 #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11865 #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f 11866 #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 11867 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11868 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11869 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11870 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11871 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11872 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11873 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11874 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11875 #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 11876 #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 11877 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11878 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11879 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11880 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11881 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11882 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11883 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11884 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11885 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f 11886 #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11887 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11888 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11889 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11890 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11891 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11892 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11893 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11894 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11895 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11896 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11897 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11898 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11899 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11900 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11901 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11902 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11903 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11904 #define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11905 #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f 11906 #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 11907 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11908 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11909 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 11910 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 11911 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 11912 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 11913 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 11914 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 11915 #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 11916 #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 11917 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 11918 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 11919 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 11920 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 11921 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 11922 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 11923 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 11924 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11925 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 11926 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 11927 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 11928 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 11929 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 11930 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 11931 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 11932 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 11933 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 11934 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 11935 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 11936 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 11937 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 11938 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 11939 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 11940 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 11941 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 11942 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 11943 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 11944 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11945 #define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f 11946 #define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 11947 #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 11948 #define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 11949 #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 11950 #define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 11951 #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 11952 #define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 11953 #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 11954 #define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 11955 #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f 11956 #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 11957 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 11958 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 11959 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 11960 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 11961 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 11962 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 11963 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 11964 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 11965 #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 11966 #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 11967 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 11968 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 11969 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 11970 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 11971 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 11972 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 11973 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 11974 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11975 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f 11976 #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 11977 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 11978 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 11979 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 11980 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 11981 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 11982 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 11983 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 11984 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 11985 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 11986 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 11987 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 11988 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 11989 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 11990 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 11991 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 11992 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 11993 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 11994 #define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 11995 #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f 11996 #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 11997 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 11998 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 11999 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12000 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12001 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12002 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12003 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12004 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12005 #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 12006 #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 12007 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12008 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12009 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12010 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12011 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12012 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12013 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12014 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12015 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12016 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12017 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12018 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12019 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12020 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12021 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12022 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12023 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12024 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12025 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12026 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12027 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12028 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12029 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12030 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12031 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12032 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12033 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12034 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12035 #define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f 12036 #define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 12037 #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 12038 #define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12039 #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12040 #define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12041 #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12042 #define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12043 #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12044 #define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12045 #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f 12046 #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 12047 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12048 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12049 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12050 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12051 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12052 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12053 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12054 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12055 #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 12056 #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 12057 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12058 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12059 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12060 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12061 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12062 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12063 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12064 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12065 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f 12066 #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12067 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12068 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12069 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12070 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12071 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12072 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12073 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12074 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12075 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12076 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12077 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12078 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12079 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12080 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12081 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12082 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12083 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12084 #define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12085 #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f 12086 #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 12087 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 12088 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 12089 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12090 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12091 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12092 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12093 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12094 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12095 #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 12096 #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 12097 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12098 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12099 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12100 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12101 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12102 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12103 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12104 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12105 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12106 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12107 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12108 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12109 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12110 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12111 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12112 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12113 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12114 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12115 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12116 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12117 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12118 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12119 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12120 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12121 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12122 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12123 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12124 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12125 #define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f 12126 #define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 12127 #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 12128 #define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12129 #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12130 #define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12131 #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12132 #define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12133 #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12134 #define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12135 #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f 12136 #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 12137 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12138 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12139 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12140 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12141 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12142 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12143 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12144 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12145 #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 12146 #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 12147 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12148 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12149 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12150 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12151 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12152 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12153 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12154 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12155 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f 12156 #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12157 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12158 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12159 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12160 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12161 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12162 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12163 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12164 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12165 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12166 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12167 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12168 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12169 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12170 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12171 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12172 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12173 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12174 #define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12175 #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f 12176 #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 12177 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 12178 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 12179 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12180 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12181 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12182 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12183 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12184 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12185 #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 12186 #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 12187 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12188 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12189 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12190 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12191 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12192 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12193 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12194 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12195 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12196 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12197 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12198 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12199 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12200 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12201 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12202 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12203 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12204 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12205 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12206 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12207 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12208 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12209 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12210 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12211 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12212 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12213 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12214 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12215 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f 12216 #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 12217 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 12218 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12219 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12220 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12221 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12222 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12223 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12224 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12225 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 12226 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 12227 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 12228 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 12229 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 12230 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 12231 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 12232 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 12233 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 12234 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12235 #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f 12236 #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 12237 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12238 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12239 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12240 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12241 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12242 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12243 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12244 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12245 #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 12246 #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 12247 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12248 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12249 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12250 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12251 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12252 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12253 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12254 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12255 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f 12256 #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12257 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12258 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12259 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12260 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12261 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12262 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12263 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12264 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12265 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12266 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12267 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12268 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12269 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12270 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12271 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12272 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12273 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12274 #define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12275 #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f 12276 #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 12277 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 12278 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 12279 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12280 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12281 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12282 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12283 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12284 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12285 #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 12286 #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 12287 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12288 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12289 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12290 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12291 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12292 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12293 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12294 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12295 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12296 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12297 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12298 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12299 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12300 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12301 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12302 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12303 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12304 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12305 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12306 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12307 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12308 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12309 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12310 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12311 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12312 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12313 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12314 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12315 #define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f 12316 #define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 12317 #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 12318 #define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12319 #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12320 #define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12321 #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12322 #define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12323 #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12324 #define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12325 #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f 12326 #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 12327 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12328 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12329 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12330 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12331 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12332 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12333 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12334 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12335 #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 12336 #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 12337 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12338 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12339 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12340 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12341 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12342 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12343 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12344 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12345 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f 12346 #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12347 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12348 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12349 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12350 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12351 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12352 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12353 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12354 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12355 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12356 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12357 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12358 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12359 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12360 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12361 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12362 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12363 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12364 #define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12365 #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f 12366 #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 12367 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 12368 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 12369 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12370 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12371 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12372 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12373 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12374 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12375 #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 12376 #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 12377 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12378 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12379 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12380 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12381 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12382 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12383 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12384 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12385 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12386 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12387 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12388 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12389 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12390 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12391 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12392 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12393 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12394 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12395 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12396 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12397 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12398 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12399 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12400 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12401 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12402 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12403 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12404 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12405 #define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f 12406 #define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 12407 #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 12408 #define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12409 #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12410 #define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12411 #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12412 #define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12413 #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12414 #define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12415 #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f 12416 #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 12417 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12418 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12419 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12420 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12421 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12422 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12423 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12424 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12425 #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 12426 #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 12427 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12428 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12429 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12430 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12431 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12432 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12433 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12434 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12435 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f 12436 #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12437 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12438 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12439 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12440 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12441 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12442 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12443 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12444 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12445 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12446 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12447 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12448 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12449 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12450 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12451 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12452 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12453 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12454 #define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12455 #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f 12456 #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 12457 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 12458 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 12459 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 12460 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 12461 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 12462 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 12463 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 12464 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 12465 #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 12466 #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 12467 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 12468 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 12469 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 12470 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 12471 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 12472 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 12473 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 12474 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12475 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f 12476 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 12477 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 12478 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 12479 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 12480 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 12481 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 12482 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 12483 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 12484 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 12485 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 12486 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 12487 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 12488 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 12489 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 12490 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 12491 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 12492 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 12493 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 12494 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12495 #define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f 12496 #define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 12497 #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 12498 #define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 12499 #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 12500 #define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 12501 #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 12502 #define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 12503 #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 12504 #define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 12505 #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f 12506 #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 12507 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 12508 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 12509 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 12510 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 12511 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 12512 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 12513 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 12514 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 12515 #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 12516 #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 12517 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 12518 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 12519 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 12520 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 12521 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 12522 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 12523 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 12524 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12525 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f 12526 #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 12527 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 12528 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 12529 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 12530 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 12531 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 12532 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 12533 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 12534 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 12535 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 12536 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 12537 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 12538 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 12539 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 12540 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 12541 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 12542 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a 12543 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 12544 #define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b 12545 #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf 12546 #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 12547 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 12548 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 12549 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 12550 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 12551 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 12552 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 12553 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 12554 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a 12555 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 12556 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b 12557 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 12558 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c 12559 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 12560 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 12561 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 12562 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e 12563 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 12564 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 12565 #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf 12566 #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 12567 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 12568 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 12569 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 12570 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 12571 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 12572 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 12573 #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 12574 #define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 12575 #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 12576 #define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a 12577 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 12578 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 12579 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 12580 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 12581 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 12582 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 12583 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 12584 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 12585 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 12586 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 12587 #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf 12588 #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 12589 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 12590 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 12591 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 12592 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc 12593 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 12594 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 12595 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 12596 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 12597 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 12598 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a 12599 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 12600 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 12601 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 12602 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 12603 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 12604 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 12605 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 12606 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 12607 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 12608 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 12609 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf 12610 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 12611 #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 12612 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 12613 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff 12614 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 12615 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 12616 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f 12617 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff 12618 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 12619 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 12620 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f 12621 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff 12622 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 12623 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 12624 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f 12625 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff 12626 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 12627 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 12628 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f 12629 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff 12630 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 12631 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 12632 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f 12633 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff 12634 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 12635 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 12636 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f 12637 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff 12638 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 12639 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 12640 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f 12641 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff 12642 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 12643 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 12644 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f 12645 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff 12646 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 12647 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 12648 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f 12649 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff 12650 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 12651 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 12652 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f 12653 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff 12654 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 12655 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 12656 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f 12657 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff 12658 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 12659 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 12660 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f 12661 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff 12662 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 12663 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 12664 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f 12665 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff 12666 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 12667 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 12668 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f 12669 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff 12670 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 12671 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 12672 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f 12673 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff 12674 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 12675 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 12676 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f 12677 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff 12678 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 12679 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 12680 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f 12681 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff 12682 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 12683 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 12684 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f 12685 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff 12686 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 12687 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 12688 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f 12689 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff 12690 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 12691 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 12692 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f 12693 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff 12694 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 12695 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 12696 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f 12697 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff 12698 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 12699 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 12700 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f 12701 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff 12702 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 12703 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 12704 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f 12705 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff 12706 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 12707 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 12708 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f 12709 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff 12710 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 12711 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 12712 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f 12713 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff 12714 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 12715 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 12716 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f 12717 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff 12718 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 12719 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 12720 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f 12721 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff 12722 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 12723 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 12724 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f 12725 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff 12726 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 12727 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 12728 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f 12729 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff 12730 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 12731 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 12732 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f 12733 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff 12734 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 12735 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 12736 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f 12737 #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff 12738 #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 12739 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 12740 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f 12741 #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 12742 #define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 12743 #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 12744 #define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 12745 #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 12746 #define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 12747 #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 12748 #define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 12749 #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 12750 #define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 12751 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 12752 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 12753 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 12754 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 12755 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 12756 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 12757 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 12758 #define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 12759 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 12760 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 12761 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 12762 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa 12763 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 12764 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb 12765 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 12766 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc 12767 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 12768 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd 12769 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 12770 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe 12771 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 12772 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf 12773 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 12774 #define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 12775 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 12776 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 12777 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 12778 #define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 12779 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 12780 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 12781 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 12782 #define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 12783 #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 12784 #define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 12785 #define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000 12786 #define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16 12787 #define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 12788 #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 12789 #define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff 12790 #define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 12791 #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff 12792 #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 12793 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff 12794 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 12795 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff 12796 #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 12797 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 12798 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 12799 #define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 12800 #define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 12801 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff 12802 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 12803 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 12804 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 12805 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff 12806 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 12807 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 12808 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 12809 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff 12810 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 12811 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff 12812 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 12813 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff 12814 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 12815 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff 12816 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 12817 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff 12818 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 12819 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff 12820 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 12821 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff 12822 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 12823 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff 12824 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 12825 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff 12826 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 12827 #define BCI_DEBUG_READ__DATA_MASK 0xffffff 12828 #define BCI_DEBUG_READ__DATA__SHIFT 0x0 12829 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff 12830 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 12831 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff 12832 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 12833 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff 12834 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 12835 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff 12836 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 12837 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f 12838 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 12839 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 12840 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 12841 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff 12842 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 12843 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff 12844 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 12845 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff 12846 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 12847 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff 12848 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 12849 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f 12850 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 12851 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 12852 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 12853 #define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff 12854 #define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 12855 #define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff 12856 #define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 12857 #define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff 12858 #define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 12859 #define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff 12860 #define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 12861 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff 12862 #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 12863 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff 12864 #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 12865 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f 12866 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 12867 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 12868 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 12869 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 12870 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa 12871 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 12872 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc 12873 #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 12874 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 12875 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 12876 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 12877 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 12878 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 12879 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 12880 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 12881 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 12882 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 12883 #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 12884 #define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 12885 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 12886 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c 12887 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 12888 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 12889 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e 12890 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 12891 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 12892 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 12893 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 12894 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 12895 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 12896 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 12897 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 12898 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 12899 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff 12900 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 12901 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 12902 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 12903 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 12904 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 12905 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff 12906 #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 12907 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff 12908 #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 12909 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff 12910 #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 12911 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff 12912 #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 12913 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff 12914 #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 12915 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff 12916 #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 12917 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff 12918 #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 12919 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff 12920 #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 12921 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff 12922 #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 12923 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff 12924 #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 12925 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff 12926 #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 12927 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff 12928 #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 12929 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff 12930 #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 12931 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff 12932 #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 12933 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff 12934 #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 12935 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff 12936 #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 12937 #define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff 12938 #define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 12939 #define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff 12940 #define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 12941 #define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff 12942 #define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 12943 #define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff 12944 #define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 12945 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff 12946 #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 12947 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff 12948 #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 12949 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f 12950 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 12951 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 12952 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 12953 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 12954 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa 12955 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 12956 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc 12957 #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 12958 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 12959 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 12960 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 12961 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 12962 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 12963 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 12964 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 12965 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 12966 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 12967 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 12968 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a 12969 #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 12970 #define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b 12971 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 12972 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e 12973 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 12974 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 12975 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e 12976 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 12977 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 12978 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 12979 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 12980 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 12981 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 12982 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 12983 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 12984 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 12985 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 12986 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa 12987 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 12988 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb 12989 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 12990 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc 12991 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 12992 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd 12993 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000 12994 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 12995 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff 12996 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 12997 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 12998 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 12999 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 13000 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 13001 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f 13002 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 13003 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff 13004 #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 13005 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff 13006 #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 13007 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff 13008 #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 13009 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff 13010 #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 13011 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff 13012 #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 13013 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff 13014 #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 13015 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff 13016 #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 13017 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff 13018 #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 13019 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff 13020 #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 13021 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff 13022 #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 13023 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff 13024 #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 13025 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff 13026 #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 13027 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff 13028 #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 13029 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff 13030 #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 13031 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff 13032 #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 13033 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff 13034 #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 13035 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 13036 #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 13037 #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e 13038 #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 13039 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 13040 #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 13041 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 13042 #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 13043 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 13044 #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 13045 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 13046 #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 13047 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 13048 #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 13049 #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e 13050 #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 13051 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 13052 #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 13053 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 13054 #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 13055 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 13056 #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 13057 #define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff 13058 #define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 13059 #define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff 13060 #define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 13061 #define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff 13062 #define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 13063 #define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff 13064 #define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 13065 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff 13066 #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 13067 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff 13068 #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 13069 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f 13070 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 13071 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 13072 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 13073 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 13074 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa 13075 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 13076 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc 13077 #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 13078 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 13079 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 13080 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 13081 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 13082 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 13083 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 13084 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 13085 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 13086 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 13087 #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 13088 #define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 13089 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 13090 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c 13091 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 13092 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 13093 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e 13094 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 13095 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 13096 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 13097 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 13098 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 13099 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff 13100 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 13101 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 13102 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 13103 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 13104 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 13105 #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000 13106 #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a 13107 #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff 13108 #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 13109 #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff 13110 #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 13111 #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff 13112 #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 13113 #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff 13114 #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 13115 #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff 13116 #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 13117 #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff 13118 #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 13119 #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff 13120 #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 13121 #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff 13122 #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 13123 #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff 13124 #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 13125 #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff 13126 #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 13127 #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff 13128 #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 13129 #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff 13130 #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 13131 #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff 13132 #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 13133 #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff 13134 #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 13135 #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff 13136 #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 13137 #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff 13138 #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 13139 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 13140 #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 13141 #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e 13142 #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 13143 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 13144 #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 13145 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 13146 #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 13147 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 13148 #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 13149 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 13150 #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 13151 #define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff 13152 #define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 13153 #define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff 13154 #define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 13155 #define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff 13156 #define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 13157 #define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff 13158 #define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 13159 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff 13160 #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 13161 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff 13162 #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 13163 #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f 13164 #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 13165 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 13166 #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 13167 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 13168 #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa 13169 #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 13170 #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc 13171 #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 13172 #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 13173 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 13174 #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 13175 #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 13176 #define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 13177 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 13178 #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 13179 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 13180 #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 13181 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 13182 #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a 13183 #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 13184 #define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b 13185 #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 13186 #define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e 13187 #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 13188 #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 13189 #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e 13190 #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 13191 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 13192 #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 13193 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 13194 #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 13195 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 13196 #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 13197 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 13198 #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 13199 #define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff 13200 #define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 13201 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 13202 #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 13203 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 13204 #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 13205 #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000 13206 #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a 13207 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff 13208 #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 13209 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff 13210 #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 13211 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff 13212 #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 13213 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff 13214 #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 13215 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff 13216 #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 13217 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff 13218 #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 13219 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff 13220 #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 13221 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff 13222 #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 13223 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff 13224 #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 13225 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff 13226 #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 13227 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff 13228 #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 13229 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff 13230 #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 13231 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff 13232 #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 13233 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff 13234 #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 13235 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff 13236 #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 13237 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff 13238 #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 13239 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 13240 #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 13241 #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e 13242 #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 13243 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 13244 #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 13245 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 13246 #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 13247 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 13248 #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 13249 #define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff 13250 #define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 13251 #define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff 13252 #define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 13253 #define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff 13254 #define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 13255 #define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff 13256 #define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 13257 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff 13258 #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 13259 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff 13260 #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 13261 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f 13262 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 13263 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 13264 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 13265 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 13266 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa 13267 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 13268 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc 13269 #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 13270 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 13271 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 13272 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 13273 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 13274 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 13275 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 13276 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 13277 #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 13278 #define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 13279 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 13280 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b 13281 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 13282 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 13283 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e 13284 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 13285 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 13286 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 13287 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 13288 #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 13289 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 13290 #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 13291 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 13292 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 13293 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f 13294 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 13295 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 13296 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 13297 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00 13298 #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa 13299 #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff 13300 #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 13301 #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff 13302 #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 13303 #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff 13304 #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 13305 #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff 13306 #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 13307 #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff 13308 #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 13309 #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff 13310 #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 13311 #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff 13312 #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 13313 #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff 13314 #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 13315 #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff 13316 #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 13317 #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff 13318 #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 13319 #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff 13320 #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 13321 #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff 13322 #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 13323 #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff 13324 #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 13325 #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff 13326 #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 13327 #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff 13328 #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 13329 #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff 13330 #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 13331 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 13332 #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 13333 #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e 13334 #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 13335 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 13336 #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 13337 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 13338 #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 13339 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 13340 #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 13341 #define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff 13342 #define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 13343 #define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff 13344 #define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 13345 #define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff 13346 #define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 13347 #define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff 13348 #define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 13349 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff 13350 #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 13351 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff 13352 #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 13353 #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f 13354 #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 13355 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 13356 #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 13357 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 13358 #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa 13359 #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 13360 #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc 13361 #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 13362 #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 13363 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 13364 #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 13365 #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 13366 #define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 13367 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 13368 #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 13369 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 13370 #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 13371 #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 13372 #define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a 13373 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 13374 #define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d 13375 #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 13376 #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 13377 #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e 13378 #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 13379 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 13380 #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 13381 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 13382 #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 13383 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 13384 #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 13385 #define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff 13386 #define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 13387 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 13388 #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 13389 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 13390 #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 13391 #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000 13392 #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a 13393 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff 13394 #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 13395 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff 13396 #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 13397 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff 13398 #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 13399 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff 13400 #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 13401 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff 13402 #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 13403 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff 13404 #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 13405 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff 13406 #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 13407 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff 13408 #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 13409 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff 13410 #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 13411 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff 13412 #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 13413 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff 13414 #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 13415 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff 13416 #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 13417 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff 13418 #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 13419 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff 13420 #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 13421 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff 13422 #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 13423 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff 13424 #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 13425 #define SQ_CONFIG__UNUSED_MASK 0xff 13426 #define SQ_CONFIG__UNUSED__SHIFT 0x0 13427 #define SQ_CONFIG__DEBUG_EN_MASK 0x100 13428 #define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 13429 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200 13430 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 13431 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400 13432 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa 13433 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 13434 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc 13435 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 13436 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd 13437 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 13438 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe 13439 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 13440 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf 13441 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000 13442 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 13443 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000 13444 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 13445 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000 13446 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 13447 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000 13448 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 13449 #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000 13450 #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 13451 #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 13452 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 13453 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc 13454 #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 13455 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 13456 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 13457 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 13458 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 13459 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 13460 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 13461 #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 13462 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 13463 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 13464 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 13465 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 13466 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa 13467 #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 13468 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb 13469 #define SQC_CONFIG__EVICT_LRU_MASK 0x3000 13470 #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc 13471 #define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000 13472 #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe 13473 #define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000 13474 #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf 13475 #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000 13476 #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 13477 #define SQC_CACHES__TARGET_INST_MASK 0x1 13478 #define SQC_CACHES__TARGET_INST__SHIFT 0x0 13479 #define SQC_CACHES__TARGET_DATA_MASK 0x2 13480 #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 13481 #define SQC_CACHES__INVALIDATE_MASK 0x4 13482 #define SQC_CACHES__INVALIDATE__SHIFT 0x2 13483 #define SQC_CACHES__WRITEBACK_MASK 0x8 13484 #define SQC_CACHES__WRITEBACK__SHIFT 0x3 13485 #define SQC_CACHES__VOL_MASK 0x10 13486 #define SQC_CACHES__VOL__SHIFT 0x4 13487 #define SQC_CACHES__COMPLETE_MASK 0x10000 13488 #define SQC_CACHES__COMPLETE__SHIFT 0x10 13489 #define SQC_WRITEBACK__DWB_MASK 0x1 13490 #define SQC_WRITEBACK__DWB__SHIFT 0x0 13491 #define SQC_WRITEBACK__DIRTY_MASK 0x2 13492 #define SQC_WRITEBACK__DIRTY__SHIFT 0x1 13493 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3 13494 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0 13495 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4 13496 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2 13497 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18 13498 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3 13499 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20 13500 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5 13501 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0 13502 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6 13503 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100 13504 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8 13505 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600 13506 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9 13507 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800 13508 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb 13509 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000 13510 #define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc 13511 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000 13512 #define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe 13513 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000 13514 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf 13515 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000 13516 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11 13517 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000 13518 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12 13519 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000 13520 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14 13521 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000 13522 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15 13523 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000 13524 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17 13525 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000 13526 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18 13527 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000 13528 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a 13529 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000 13530 #define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b 13531 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000 13532 #define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d 13533 #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f 13534 #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 13535 #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 13536 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 13537 #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 13538 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa 13539 #define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f 13540 #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 13541 #define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 13542 #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 13543 #define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 13544 #define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c 13545 #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 13546 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 13547 #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 13548 #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e 13549 #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 13550 #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f 13551 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf 13552 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 13553 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 13554 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 13555 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 13556 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 13557 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 13558 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 13559 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 13560 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 13561 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2 13562 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 13563 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4 13564 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 13565 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8 13566 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 13567 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100 13568 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 13569 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200 13570 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 13571 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400 13572 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa 13573 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000 13574 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 13575 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000 13576 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 13577 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000 13578 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 13579 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000 13580 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 13581 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000 13582 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 13583 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000 13584 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 13585 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000 13586 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 13587 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000 13588 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 13589 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000 13590 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a 13591 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 13592 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 13593 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 13594 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 13595 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 13596 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 13597 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 13598 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 13599 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 13600 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 13601 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 13602 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 13603 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff 13604 #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 13605 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 13606 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 13607 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 13608 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 13609 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 13610 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 13611 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 13612 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 13613 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 13614 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 13615 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 13616 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 13617 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 13618 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 13619 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 13620 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 13621 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 13622 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 13623 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 13624 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd 13625 #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff 13626 #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 13627 #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 13628 #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 13629 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 13630 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 13631 #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 13632 #define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 13633 #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 13634 #define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 13635 #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 13636 #define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 13637 #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 13638 #define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c 13639 #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 13640 #define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 13641 #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 13642 #define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 13643 #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 13644 #define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 13645 #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 13646 #define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c 13647 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 13648 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 13649 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 13650 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 13651 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 13652 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 13653 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 13654 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 13655 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff 13656 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 13657 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff 13658 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 13659 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff 13660 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 13661 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff 13662 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 13663 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff 13664 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 13665 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff 13666 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 13667 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff 13668 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 13669 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff 13670 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 13671 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff 13672 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 13673 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff 13674 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 13675 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff 13676 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 13677 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff 13678 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 13679 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 13680 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 13681 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 13682 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 13683 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 13684 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 13685 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 13686 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 13687 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff 13688 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 13689 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff 13690 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 13691 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff 13692 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 13693 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff 13694 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 13695 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff 13696 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 13697 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff 13698 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 13699 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff 13700 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 13701 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff 13702 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 13703 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff 13704 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 13705 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff 13706 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 13707 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff 13708 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 13709 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff 13710 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 13711 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff 13712 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 13713 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 13714 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc 13715 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13716 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13717 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 13718 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 13719 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 13720 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 13721 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 13722 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 13723 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff 13724 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 13725 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 13726 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc 13727 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13728 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13729 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 13730 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 13731 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 13732 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 13733 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 13734 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 13735 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff 13736 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 13737 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 13738 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc 13739 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13740 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13741 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 13742 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 13743 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 13744 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 13745 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 13746 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 13747 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff 13748 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 13749 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 13750 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc 13751 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13752 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13753 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 13754 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 13755 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 13756 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 13757 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 13758 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 13759 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff 13760 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 13761 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 13762 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc 13763 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13764 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13765 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 13766 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 13767 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 13768 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 13769 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 13770 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c 13771 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff 13772 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 13773 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 13774 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc 13775 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13776 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13777 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 13778 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 13779 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 13780 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 13781 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 13782 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c 13783 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff 13784 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 13785 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 13786 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc 13787 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13788 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13789 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 13790 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 13791 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 13792 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 13793 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 13794 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c 13795 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff 13796 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 13797 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 13798 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc 13799 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13800 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13801 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 13802 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 13803 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 13804 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 13805 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 13806 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c 13807 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff 13808 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 13809 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 13810 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc 13811 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13812 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13813 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 13814 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 13815 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 13816 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 13817 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 13818 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c 13819 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff 13820 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 13821 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 13822 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc 13823 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13824 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13825 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 13826 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 13827 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 13828 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 13829 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 13830 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c 13831 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff 13832 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 13833 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 13834 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc 13835 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13836 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13837 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 13838 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 13839 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 13840 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 13841 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 13842 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c 13843 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff 13844 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 13845 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 13846 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc 13847 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13848 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13849 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 13850 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 13851 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 13852 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 13853 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 13854 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c 13855 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff 13856 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 13857 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 13858 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc 13859 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13860 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13861 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 13862 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 13863 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 13864 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 13865 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 13866 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c 13867 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff 13868 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 13869 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 13870 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc 13871 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13872 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13873 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 13874 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 13875 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 13876 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 13877 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 13878 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c 13879 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff 13880 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 13881 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 13882 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc 13883 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13884 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13885 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 13886 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 13887 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 13888 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 13889 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 13890 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c 13891 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff 13892 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 13893 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 13894 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc 13895 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 13896 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 13897 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 13898 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 13899 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 13900 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 13901 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 13902 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c 13903 #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf 13904 #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 13905 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 13906 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13907 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 13908 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 13909 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 13910 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 13911 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 13912 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 13913 #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf 13914 #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 13915 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 13916 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13917 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000 13918 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c 13919 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 13920 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 13921 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 13922 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 13923 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 13924 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 13925 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 13926 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 13927 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 13928 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 13929 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 13930 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 13931 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 13932 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 13933 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff 13934 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 13935 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 13936 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 13937 #define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff 13938 #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 13939 #define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 13940 #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 13941 #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 13942 #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e 13943 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff 13944 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 13945 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 13946 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 13947 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 13948 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 13949 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 13950 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f 13951 #define SQ_TIME_HI__TIME_MASK 0xffffffff 13952 #define SQ_TIME_HI__TIME__SHIFT 0x0 13953 #define SQ_TIME_LO__TIME_MASK 0xffffffff 13954 #define SQ_TIME_LO__TIME__SHIFT 0x0 13955 #define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff 13956 #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 13957 #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf 13958 #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 13959 #define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff 13960 #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 13961 #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f 13962 #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 13963 #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 13964 #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 13965 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 13966 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 13967 #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 13968 #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 13969 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 13970 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc 13971 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 13972 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe 13973 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 13974 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf 13975 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff 13976 #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 13977 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff 13978 #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 13979 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff 13980 #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 13981 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff 13982 #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 13983 #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 13984 #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 13985 #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 13986 #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 13987 #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 13988 #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 13989 #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 13990 #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 13991 #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 13992 #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc 13993 #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 13994 #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf 13995 #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 13996 #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 13997 #define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 13998 #define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 13999 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 14000 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 14001 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 14002 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 14003 #define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 14004 #define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a 14005 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 14006 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b 14007 #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 14008 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 14009 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 14010 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e 14011 #define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 14012 #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f 14013 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 14014 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f 14015 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff 14016 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 14017 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 14018 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 14019 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 14020 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 14021 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff 14022 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 14023 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff 14024 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 14025 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 14026 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 14027 #define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff 14028 #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 14029 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 14030 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e 14031 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff 14032 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 14033 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 14034 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 14035 #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 14036 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 14037 #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 14038 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e 14039 #define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 14040 #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f 14041 #define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff 14042 #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 14043 #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 14044 #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 14045 #define SQ_LB_CTR_CTRL__START_MASK 0x1 14046 #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 14047 #define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 14048 #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 14049 #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 14050 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 14051 #define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff 14052 #define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 14053 #define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff 14054 #define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 14055 #define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff 14056 #define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 14057 #define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff 14058 #define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 14059 #define SQC_EDC_CNT__INST_SEC_MASK 0xff 14060 #define SQC_EDC_CNT__INST_SEC__SHIFT 0x0 14061 #define SQC_EDC_CNT__INST_DED_MASK 0xff00 14062 #define SQC_EDC_CNT__INST_DED__SHIFT 0x8 14063 #define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000 14064 #define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10 14065 #define SQC_EDC_CNT__DATA_DED_MASK 0xff000000 14066 #define SQC_EDC_CNT__DATA_DED__SHIFT 0x18 14067 #define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff 14068 #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 14069 #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00 14070 #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 14071 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 14072 #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 14073 #define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff 14074 #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 14075 #define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00 14076 #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 14077 #define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000 14078 #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 14079 #define SQ_EDC_INFO__WAVE_ID_MASK 0xf 14080 #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 14081 #define SQ_EDC_INFO__SIMD_ID_MASK 0x30 14082 #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 14083 #define SQ_EDC_INFO__SOURCE_MASK 0x1c0 14084 #define SQ_EDC_INFO__SOURCE__SHIFT 0x6 14085 #define SQ_EDC_INFO__VM_ID_MASK 0x1e00 14086 #define SQ_EDC_INFO__VM_ID__SHIFT 0x9 14087 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff 14088 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 14089 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff 14090 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 14091 #define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 14092 #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 14093 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 14094 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e 14095 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 14096 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f 14097 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff 14098 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 14099 #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 14100 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 14101 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 14102 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 14103 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 14104 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 14105 #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 14106 #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 14107 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 14108 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc 14109 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 14110 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf 14111 #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 14112 #define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 14113 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 14114 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 14115 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 14116 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 14117 #define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 14118 #define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 14119 #define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 14120 #define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 14121 #define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 14122 #define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a 14123 #define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 14124 #define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b 14125 #define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 14126 #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e 14127 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff 14128 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 14129 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff 14130 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 14131 #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 14132 #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 14133 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 14134 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 14135 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 14136 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a 14137 #define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 14138 #define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e 14139 #define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff 14140 #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 14141 #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 14142 #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe 14143 #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 14144 #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c 14145 #define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 14146 #define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f 14147 #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 14148 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 14149 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 14150 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 14151 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 14152 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 14153 #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 14154 #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 14155 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 14156 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc 14157 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 14158 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 14159 #define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 14160 #define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 14161 #define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 14162 #define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 14163 #define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 14164 #define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a 14165 #define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 14166 #define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b 14167 #define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 14168 #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c 14169 #define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff 14170 #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 14171 #define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 14172 #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd 14173 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff 14174 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 14175 #define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 14176 #define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd 14177 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff 14178 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 14179 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 14180 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc 14181 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 14182 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 14183 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000 14184 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 14185 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000 14186 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 14187 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000 14188 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 14189 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000 14190 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 14191 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000 14192 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c 14193 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff 14194 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 14195 #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 14196 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 14197 #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 14198 #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 14199 #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 14200 #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 14201 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 14202 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 14203 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 14204 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc 14205 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 14206 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf 14207 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 14208 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 14209 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 14210 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 14211 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 14212 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 14213 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 14214 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 14215 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 14216 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b 14217 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 14218 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c 14219 #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 14220 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 14221 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000 14222 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f 14223 #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff 14224 #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 14225 #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 14226 #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc 14227 #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 14228 #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 14229 #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 14230 #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c 14231 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff 14232 #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 14233 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 14234 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe 14235 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 14236 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 14237 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 14238 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 14239 #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 14240 #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 14241 #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 14242 #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a 14243 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 14244 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c 14245 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 14246 #define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d 14247 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 14248 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e 14249 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000 14250 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f 14251 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff 14252 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 14253 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 14254 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e 14255 #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff 14256 #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 14257 #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff 14258 #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 14259 #define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff 14260 #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 14261 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000 14262 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc 14263 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000 14264 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd 14265 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000 14266 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe 14267 #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000 14268 #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf 14269 #define SQ_IND_INDEX__WAVE_ID_MASK 0xf 14270 #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 14271 #define SQ_IND_INDEX__SIMD_ID_MASK 0x30 14272 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 14273 #define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 14274 #define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 14275 #define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 14276 #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc 14277 #define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 14278 #define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd 14279 #define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 14280 #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe 14281 #define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 14282 #define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf 14283 #define SQ_IND_INDEX__INDEX_MASK 0xffff0000 14284 #define SQ_IND_INDEX__INDEX__SHIFT 0x10 14285 #define SQ_CMD__CMD_MASK 0x7 14286 #define SQ_CMD__CMD__SHIFT 0x0 14287 #define SQ_CMD__MODE_MASK 0x70 14288 #define SQ_CMD__MODE__SHIFT 0x4 14289 #define SQ_CMD__CHECK_VMID_MASK 0x80 14290 #define SQ_CMD__CHECK_VMID__SHIFT 0x7 14291 #define SQ_CMD__DATA_MASK 0x700 14292 #define SQ_CMD__DATA__SHIFT 0x8 14293 #define SQ_CMD__WAVE_ID_MASK 0xf0000 14294 #define SQ_CMD__WAVE_ID__SHIFT 0x10 14295 #define SQ_CMD__SIMD_ID_MASK 0x300000 14296 #define SQ_CMD__SIMD_ID__SHIFT 0x14 14297 #define SQ_CMD__QUEUE_ID_MASK 0x7000000 14298 #define SQ_CMD__QUEUE_ID__SHIFT 0x18 14299 #define SQ_CMD__VM_ID_MASK 0xf0000000 14300 #define SQ_CMD__VM_ID__SHIFT 0x1c 14301 #define SQ_IND_DATA__DATA_MASK 0xffffffff 14302 #define SQ_IND_DATA__DATA__SHIFT 0x0 14303 #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff 14304 #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 14305 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff 14306 #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 14307 #define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf 14308 #define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 14309 #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 14310 #define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 14311 #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff 14312 #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 14313 #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff 14314 #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 14315 #define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff 14316 #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 14317 #define SQ_WAVE_PC_HI__PC_HI_MASK 0xff 14318 #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 14319 #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 14320 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 14321 #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 14322 #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 14323 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 14324 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 14325 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 14326 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 14327 #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 14328 #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 14329 #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 14330 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa 14331 #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000 14332 #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 14333 #define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000 14334 #define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14 14335 #define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000 14336 #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 14337 #define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000 14338 #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a 14339 #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000 14340 #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b 14341 #define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000 14342 #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d 14343 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000 14344 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e 14345 #define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1 14346 #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 14347 #define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2 14348 #define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 14349 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4 14350 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 14351 #define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0 14352 #define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 14353 #define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00 14354 #define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8 14355 #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff 14356 #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 14357 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff 14358 #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 14359 #define SQ_WAVE_STATUS__SCC_MASK 0x1 14360 #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 14361 #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 14362 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 14363 #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18 14364 #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 14365 #define SQ_WAVE_STATUS__PRIV_MASK 0x20 14366 #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 14367 #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 14368 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 14369 #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 14370 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 14371 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 14372 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 14373 #define SQ_WAVE_STATUS__EXECZ_MASK 0x200 14374 #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 14375 #define SQ_WAVE_STATUS__VCCZ_MASK 0x400 14376 #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa 14377 #define SQ_WAVE_STATUS__IN_TG_MASK 0x800 14378 #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb 14379 #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 14380 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc 14381 #define SQ_WAVE_STATUS__HALT_MASK 0x2000 14382 #define SQ_WAVE_STATUS__HALT__SHIFT 0xd 14383 #define SQ_WAVE_STATUS__TRAP_MASK 0x4000 14384 #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe 14385 #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 14386 #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf 14387 #define SQ_WAVE_STATUS__VALID_MASK 0x10000 14388 #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 14389 #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 14390 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 14391 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 14392 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 14393 #define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 14394 #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 14395 #define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 14396 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 14397 #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 14398 #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 14399 #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000 14400 #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 14401 #define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 14402 #define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 14403 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 14404 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b 14405 #define SQ_WAVE_MODE__FP_ROUND_MASK 0xf 14406 #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 14407 #define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 14408 #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 14409 #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 14410 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 14411 #define SQ_WAVE_MODE__IEEE_MASK 0x200 14412 #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 14413 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 14414 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa 14415 #define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 14416 #define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb 14417 #define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 14418 #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc 14419 #define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000 14420 #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b 14421 #define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 14422 #define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c 14423 #define SQ_WAVE_MODE__CSP_MASK 0xe0000000 14424 #define SQ_WAVE_MODE__CSP__SHIFT 0x1d 14425 #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff 14426 #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 14427 #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400 14428 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa 14429 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 14430 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 14431 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 14432 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 14433 #define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf 14434 #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 14435 #define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 14436 #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 14437 #define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 14438 #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 14439 #define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 14440 #define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 14441 #define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 14442 #define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc 14443 #define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 14444 #define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd 14445 #define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 14446 #define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 14447 #define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 14448 #define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 14449 #define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 14450 #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 14451 #define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 14452 #define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b 14453 #define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 14454 #define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e 14455 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f 14456 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 14457 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 14458 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 14459 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 14460 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 14461 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 14462 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 14463 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff 14464 #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 14465 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 14466 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc 14467 #define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf 14468 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 14469 #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 14470 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 14471 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 14472 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 14473 #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 14474 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc 14475 #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000 14476 #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf 14477 #define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000 14478 #define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 14479 #define SQ_WAVE_M0__M0_MASK 0xffffffff 14480 #define SQ_WAVE_M0__M0__SHIFT 0x0 14481 #define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff 14482 #define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 14483 #define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff 14484 #define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 14485 #define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff 14486 #define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 14487 #define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff 14488 #define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 14489 #define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff 14490 #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 14491 #define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff 14492 #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 14493 #define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff 14494 #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 14495 #define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff 14496 #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 14497 #define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff 14498 #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 14499 #define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff 14500 #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 14501 #define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff 14502 #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 14503 #define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff 14504 #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 14505 #define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff 14506 #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 14507 #define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff 14508 #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 14509 #define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff 14510 #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 14511 #define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff 14512 #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 14513 #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 14514 #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 14515 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 14516 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 14517 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 14518 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 14519 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 14520 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 14521 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff 14522 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 14523 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 14524 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 14525 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 14526 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 14527 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 14528 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 14529 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf 14530 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 14531 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0 14532 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 14533 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 14534 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 14535 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 14536 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 14537 #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff 14538 #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 14539 #define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff 14540 #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 14541 #define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 14542 #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 14543 #define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff 14544 #define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 14545 #define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff 14546 #define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 14547 #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3 14548 #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 14549 #define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4 14550 #define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2 14551 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18 14552 #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 14553 #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0 14554 #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5 14555 #define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700 14556 #define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8 14557 #define SH_MEM_CONFIG__APE1_ATC_MASK 0x800 14558 #define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb 14559 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf 14560 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 14561 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 14562 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 14563 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf 14564 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 14565 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 14566 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 14567 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 14568 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 14569 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 14570 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 14571 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800 14572 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb 14573 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf 14574 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14575 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 14576 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 14577 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 14578 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 14579 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 14580 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 14581 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 14582 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 14583 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff 14584 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 14585 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf 14586 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14587 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 14588 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 14589 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 14590 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 14591 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 14592 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 14593 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 14594 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa 14595 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 14596 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe 14597 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 14598 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 14599 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff 14600 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 14601 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf 14602 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14603 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 14604 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 14605 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff 14606 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 14607 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf 14608 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 14609 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 14610 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 14611 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 14612 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 14613 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 14614 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 14615 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 14616 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa 14617 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 14618 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe 14619 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf 14620 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 14621 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 14622 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 14623 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 14624 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc 14625 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 14626 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd 14627 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf 14628 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 14629 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 14630 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 14631 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 14632 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 14633 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 14634 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 14635 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 14636 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa 14637 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 14638 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe 14639 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 14640 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 14641 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 14642 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 14643 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 14644 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 14645 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 14646 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 14647 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf 14648 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14649 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 14650 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 14651 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 14652 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 14653 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 14654 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 14655 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 14656 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 14657 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 14658 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa 14659 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 14660 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe 14661 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 14662 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf 14663 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 14664 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 14665 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff 14666 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 14667 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf 14668 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14669 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 14670 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 14671 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 14672 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 14673 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 14674 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 14675 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 14676 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 14677 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 14678 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 14679 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff 14680 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 14681 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf 14682 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 14683 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 14684 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 14685 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 14686 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 14687 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 14688 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 14689 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 14690 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa 14691 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf 14692 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 14693 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 14694 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 14695 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 14696 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 14697 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 14698 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 14699 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 14700 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa 14701 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 14702 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc 14703 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 14704 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe 14705 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 14706 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 14707 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 14708 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 14709 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 14710 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 14711 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 14712 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 14713 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 14714 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 14715 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 14716 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a 14717 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf 14718 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 14719 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 14720 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 14721 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 14722 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 14723 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 14724 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 14725 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 14726 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa 14727 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 14728 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc 14729 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 14730 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 14731 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f 14732 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 14733 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 14734 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 14735 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 14736 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 14737 #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff 14738 #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 14739 #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff 14740 #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 14741 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000 14742 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a 14743 #define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000 14744 #define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b 14745 #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000 14746 #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c 14747 #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000 14748 #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f 14749 #define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff 14750 #define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0 14751 #define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000 14752 #define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12 14753 #define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000 14754 #define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13 14755 #define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000 14756 #define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14 14757 #define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000 14758 #define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15 14759 #define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000 14760 #define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17 14761 #define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000 14762 #define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19 14763 #define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000 14764 #define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a 14765 #define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000 14766 #define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b 14767 #define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 14768 #define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 14769 #define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 14770 #define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 14771 #define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff 14772 #define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0 14773 #define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000 14774 #define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10 14775 #define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 14776 #define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 14777 #define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 14778 #define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a 14779 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 14780 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 14781 #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 14782 #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 14783 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 14784 #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 14785 #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 14786 #define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 14787 #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 14788 #define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 14789 #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 14790 #define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 14791 #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 14792 #define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 14793 #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 14794 #define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 14795 #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 14796 #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 14797 #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 14798 #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a 14799 #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff 14800 #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 14801 #define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 14802 #define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 14803 #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 14804 #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 14805 #define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 14806 #define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa 14807 #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 14808 #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe 14809 #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 14810 #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 14811 #define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 14812 #define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 14813 #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 14814 #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 14815 #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 14816 #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a 14817 #define SQ_SOP2__SSRC0_MASK 0xff 14818 #define SQ_SOP2__SSRC0__SHIFT 0x0 14819 #define SQ_SOP2__SSRC1_MASK 0xff00 14820 #define SQ_SOP2__SSRC1__SHIFT 0x8 14821 #define SQ_SOP2__SDST_MASK 0x7f0000 14822 #define SQ_SOP2__SDST__SHIFT 0x10 14823 #define SQ_SOP2__OP_MASK 0x3f800000 14824 #define SQ_SOP2__OP__SHIFT 0x17 14825 #define SQ_SOP2__ENCODING_MASK 0xc0000000 14826 #define SQ_SOP2__ENCODING__SHIFT 0x1e 14827 #define SQ_VOP1__SRC0_MASK 0x1ff 14828 #define SQ_VOP1__SRC0__SHIFT 0x0 14829 #define SQ_VOP1__OP_MASK 0x1fe00 14830 #define SQ_VOP1__OP__SHIFT 0x9 14831 #define SQ_VOP1__VDST_MASK 0x1fe0000 14832 #define SQ_VOP1__VDST__SHIFT 0x11 14833 #define SQ_VOP1__ENCODING_MASK 0xfe000000 14834 #define SQ_VOP1__ENCODING__SHIFT 0x19 14835 #define SQ_MTBUF_1__VADDR_MASK 0xff 14836 #define SQ_MTBUF_1__VADDR__SHIFT 0x0 14837 #define SQ_MTBUF_1__VDATA_MASK 0xff00 14838 #define SQ_MTBUF_1__VDATA__SHIFT 0x8 14839 #define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 14840 #define SQ_MTBUF_1__SRSRC__SHIFT 0x10 14841 #define SQ_MTBUF_1__SLC_MASK 0x400000 14842 #define SQ_MTBUF_1__SLC__SHIFT 0x16 14843 #define SQ_MTBUF_1__TFE_MASK 0x800000 14844 #define SQ_MTBUF_1__TFE__SHIFT 0x17 14845 #define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 14846 #define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 14847 #define SQ_EXP_1__VSRC0_MASK 0xff 14848 #define SQ_EXP_1__VSRC0__SHIFT 0x0 14849 #define SQ_EXP_1__VSRC1_MASK 0xff00 14850 #define SQ_EXP_1__VSRC1__SHIFT 0x8 14851 #define SQ_EXP_1__VSRC2_MASK 0xff0000 14852 #define SQ_EXP_1__VSRC2__SHIFT 0x10 14853 #define SQ_EXP_1__VSRC3_MASK 0xff000000 14854 #define SQ_EXP_1__VSRC3__SHIFT 0x18 14855 #define SQ_MUBUF_1__VADDR_MASK 0xff 14856 #define SQ_MUBUF_1__VADDR__SHIFT 0x0 14857 #define SQ_MUBUF_1__VDATA_MASK 0xff00 14858 #define SQ_MUBUF_1__VDATA__SHIFT 0x8 14859 #define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 14860 #define SQ_MUBUF_1__SRSRC__SHIFT 0x10 14861 #define SQ_MUBUF_1__TFE_MASK 0x800000 14862 #define SQ_MUBUF_1__TFE__SHIFT 0x17 14863 #define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 14864 #define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 14865 #define SQ_SMEM_1__OFFSET_MASK 0xfffff 14866 #define SQ_SMEM_1__OFFSET__SHIFT 0x0 14867 #define SQ_INST__ENCODING_MASK 0xffffffff 14868 #define SQ_INST__ENCODING__SHIFT 0x0 14869 #define SQ_EXP_0__EN_MASK 0xf 14870 #define SQ_EXP_0__EN__SHIFT 0x0 14871 #define SQ_EXP_0__TGT_MASK 0x3f0 14872 #define SQ_EXP_0__TGT__SHIFT 0x4 14873 #define SQ_EXP_0__COMPR_MASK 0x400 14874 #define SQ_EXP_0__COMPR__SHIFT 0xa 14875 #define SQ_EXP_0__DONE_MASK 0x800 14876 #define SQ_EXP_0__DONE__SHIFT 0xb 14877 #define SQ_EXP_0__VM_MASK 0x1000 14878 #define SQ_EXP_0__VM__SHIFT 0xc 14879 #define SQ_EXP_0__ENCODING_MASK 0xfc000000 14880 #define SQ_EXP_0__ENCODING__SHIFT 0x1a 14881 #define SQ_MUBUF_0__OFFSET_MASK 0xfff 14882 #define SQ_MUBUF_0__OFFSET__SHIFT 0x0 14883 #define SQ_MUBUF_0__OFFEN_MASK 0x1000 14884 #define SQ_MUBUF_0__OFFEN__SHIFT 0xc 14885 #define SQ_MUBUF_0__IDXEN_MASK 0x2000 14886 #define SQ_MUBUF_0__IDXEN__SHIFT 0xd 14887 #define SQ_MUBUF_0__GLC_MASK 0x4000 14888 #define SQ_MUBUF_0__GLC__SHIFT 0xe 14889 #define SQ_MUBUF_0__LDS_MASK 0x10000 14890 #define SQ_MUBUF_0__LDS__SHIFT 0x10 14891 #define SQ_MUBUF_0__SLC_MASK 0x20000 14892 #define SQ_MUBUF_0__SLC__SHIFT 0x11 14893 #define SQ_MUBUF_0__OP_MASK 0x1fc0000 14894 #define SQ_MUBUF_0__OP__SHIFT 0x12 14895 #define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 14896 #define SQ_MUBUF_0__ENCODING__SHIFT 0x1a 14897 #define SQ_VOP_SDWA__SRC0_MASK 0xff 14898 #define SQ_VOP_SDWA__SRC0__SHIFT 0x0 14899 #define SQ_VOP_SDWA__DST_SEL_MASK 0x700 14900 #define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 14901 #define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800 14902 #define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb 14903 #define SQ_VOP_SDWA__CLAMP_MASK 0x2000 14904 #define SQ_VOP_SDWA__CLAMP__SHIFT 0xd 14905 #define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000 14906 #define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 14907 #define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000 14908 #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 14909 #define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000 14910 #define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 14911 #define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000 14912 #define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 14913 #define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000 14914 #define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 14915 #define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000 14916 #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b 14917 #define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000 14918 #define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c 14919 #define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000 14920 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d 14921 #define SQ_VOP3_0__VDST_MASK 0xff 14922 #define SQ_VOP3_0__VDST__SHIFT 0x0 14923 #define SQ_VOP3_0__ABS_MASK 0x700 14924 #define SQ_VOP3_0__ABS__SHIFT 0x8 14925 #define SQ_VOP3_0__CLAMP_MASK 0x8000 14926 #define SQ_VOP3_0__CLAMP__SHIFT 0xf 14927 #define SQ_VOP3_0__OP_MASK 0x3ff0000 14928 #define SQ_VOP3_0__OP__SHIFT 0x10 14929 #define SQ_VOP3_0__ENCODING_MASK 0xfc000000 14930 #define SQ_VOP3_0__ENCODING__SHIFT 0x1a 14931 #define SQ_VOP2__SRC0_MASK 0x1ff 14932 #define SQ_VOP2__SRC0__SHIFT 0x0 14933 #define SQ_VOP2__VSRC1_MASK 0x1fe00 14934 #define SQ_VOP2__VSRC1__SHIFT 0x9 14935 #define SQ_VOP2__VDST_MASK 0x1fe0000 14936 #define SQ_VOP2__VDST__SHIFT 0x11 14937 #define SQ_VOP2__OP_MASK 0x7e000000 14938 #define SQ_VOP2__OP__SHIFT 0x19 14939 #define SQ_VOP2__ENCODING_MASK 0x80000000 14940 #define SQ_VOP2__ENCODING__SHIFT 0x1f 14941 #define SQ_MTBUF_0__OFFSET_MASK 0xfff 14942 #define SQ_MTBUF_0__OFFSET__SHIFT 0x0 14943 #define SQ_MTBUF_0__OFFEN_MASK 0x1000 14944 #define SQ_MTBUF_0__OFFEN__SHIFT 0xc 14945 #define SQ_MTBUF_0__IDXEN_MASK 0x2000 14946 #define SQ_MTBUF_0__IDXEN__SHIFT 0xd 14947 #define SQ_MTBUF_0__GLC_MASK 0x4000 14948 #define SQ_MTBUF_0__GLC__SHIFT 0xe 14949 #define SQ_MTBUF_0__OP_MASK 0x78000 14950 #define SQ_MTBUF_0__OP__SHIFT 0xf 14951 #define SQ_MTBUF_0__DFMT_MASK 0x780000 14952 #define SQ_MTBUF_0__DFMT__SHIFT 0x13 14953 #define SQ_MTBUF_0__NFMT_MASK 0x3800000 14954 #define SQ_MTBUF_0__NFMT__SHIFT 0x17 14955 #define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 14956 #define SQ_MTBUF_0__ENCODING__SHIFT 0x1a 14957 #define SQ_SOPP__SIMM16_MASK 0xffff 14958 #define SQ_SOPP__SIMM16__SHIFT 0x0 14959 #define SQ_SOPP__OP_MASK 0x7f0000 14960 #define SQ_SOPP__OP__SHIFT 0x10 14961 #define SQ_SOPP__ENCODING_MASK 0xff800000 14962 #define SQ_SOPP__ENCODING__SHIFT 0x17 14963 #define SQ_FLAT_0__GLC_MASK 0x10000 14964 #define SQ_FLAT_0__GLC__SHIFT 0x10 14965 #define SQ_FLAT_0__SLC_MASK 0x20000 14966 #define SQ_FLAT_0__SLC__SHIFT 0x11 14967 #define SQ_FLAT_0__OP_MASK 0x1fc0000 14968 #define SQ_FLAT_0__OP__SHIFT 0x12 14969 #define SQ_FLAT_0__ENCODING_MASK 0xfc000000 14970 #define SQ_FLAT_0__ENCODING__SHIFT 0x1a 14971 #define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff 14972 #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 14973 #define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 14974 #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 14975 #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000 14976 #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf 14977 #define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000 14978 #define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 14979 #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 14980 #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a 14981 #define SQ_MIMG_1__VADDR_MASK 0xff 14982 #define SQ_MIMG_1__VADDR__SHIFT 0x0 14983 #define SQ_MIMG_1__VDATA_MASK 0xff00 14984 #define SQ_MIMG_1__VDATA__SHIFT 0x8 14985 #define SQ_MIMG_1__SRSRC_MASK 0x1f0000 14986 #define SQ_MIMG_1__SRSRC__SHIFT 0x10 14987 #define SQ_MIMG_1__SSAMP_MASK 0x3e00000 14988 #define SQ_MIMG_1__SSAMP__SHIFT 0x15 14989 #define SQ_MIMG_1__D16_MASK 0x80000000 14990 #define SQ_MIMG_1__D16__SHIFT 0x1f 14991 #define SQ_SOP1__SSRC0_MASK 0xff 14992 #define SQ_SOP1__SSRC0__SHIFT 0x0 14993 #define SQ_SOP1__OP_MASK 0xff00 14994 #define SQ_SOP1__OP__SHIFT 0x8 14995 #define SQ_SOP1__SDST_MASK 0x7f0000 14996 #define SQ_SOP1__SDST__SHIFT 0x10 14997 #define SQ_SOP1__ENCODING_MASK 0xff800000 14998 #define SQ_SOP1__ENCODING__SHIFT 0x17 14999 #define SQ_SOPC__SSRC0_MASK 0xff 15000 #define SQ_SOPC__SSRC0__SHIFT 0x0 15001 #define SQ_SOPC__SSRC1_MASK 0xff00 15002 #define SQ_SOPC__SSRC1__SHIFT 0x8 15003 #define SQ_SOPC__OP_MASK 0x7f0000 15004 #define SQ_SOPC__OP__SHIFT 0x10 15005 #define SQ_SOPC__ENCODING_MASK 0xff800000 15006 #define SQ_SOPC__ENCODING__SHIFT 0x17 15007 #define SQ_FLAT_1__ADDR_MASK 0xff 15008 #define SQ_FLAT_1__ADDR__SHIFT 0x0 15009 #define SQ_FLAT_1__DATA_MASK 0xff00 15010 #define SQ_FLAT_1__DATA__SHIFT 0x8 15011 #define SQ_FLAT_1__TFE_MASK 0x800000 15012 #define SQ_FLAT_1__TFE__SHIFT 0x17 15013 #define SQ_FLAT_1__VDST_MASK 0xff000000 15014 #define SQ_FLAT_1__VDST__SHIFT 0x18 15015 #define SQ_DS_1__ADDR_MASK 0xff 15016 #define SQ_DS_1__ADDR__SHIFT 0x0 15017 #define SQ_DS_1__DATA0_MASK 0xff00 15018 #define SQ_DS_1__DATA0__SHIFT 0x8 15019 #define SQ_DS_1__DATA1_MASK 0xff0000 15020 #define SQ_DS_1__DATA1__SHIFT 0x10 15021 #define SQ_DS_1__VDST_MASK 0xff000000 15022 #define SQ_DS_1__VDST__SHIFT 0x18 15023 #define SQ_VOP3_1__SRC0_MASK 0x1ff 15024 #define SQ_VOP3_1__SRC0__SHIFT 0x0 15025 #define SQ_VOP3_1__SRC1_MASK 0x3fe00 15026 #define SQ_VOP3_1__SRC1__SHIFT 0x9 15027 #define SQ_VOP3_1__SRC2_MASK 0x7fc0000 15028 #define SQ_VOP3_1__SRC2__SHIFT 0x12 15029 #define SQ_VOP3_1__OMOD_MASK 0x18000000 15030 #define SQ_VOP3_1__OMOD__SHIFT 0x1b 15031 #define SQ_VOP3_1__NEG_MASK 0xe0000000 15032 #define SQ_VOP3_1__NEG__SHIFT 0x1d 15033 #define SQ_SMEM_0__SBASE_MASK 0x3f 15034 #define SQ_SMEM_0__SBASE__SHIFT 0x0 15035 #define SQ_SMEM_0__SDATA_MASK 0x1fc0 15036 #define SQ_SMEM_0__SDATA__SHIFT 0x6 15037 #define SQ_SMEM_0__GLC_MASK 0x10000 15038 #define SQ_SMEM_0__GLC__SHIFT 0x10 15039 #define SQ_SMEM_0__IMM_MASK 0x20000 15040 #define SQ_SMEM_0__IMM__SHIFT 0x11 15041 #define SQ_SMEM_0__OP_MASK 0x3fc0000 15042 #define SQ_SMEM_0__OP__SHIFT 0x12 15043 #define SQ_SMEM_0__ENCODING_MASK 0xfc000000 15044 #define SQ_SMEM_0__ENCODING__SHIFT 0x1a 15045 #define SQ_MIMG_0__DMASK_MASK 0xf00 15046 #define SQ_MIMG_0__DMASK__SHIFT 0x8 15047 #define SQ_MIMG_0__UNORM_MASK 0x1000 15048 #define SQ_MIMG_0__UNORM__SHIFT 0xc 15049 #define SQ_MIMG_0__GLC_MASK 0x2000 15050 #define SQ_MIMG_0__GLC__SHIFT 0xd 15051 #define SQ_MIMG_0__DA_MASK 0x4000 15052 #define SQ_MIMG_0__DA__SHIFT 0xe 15053 #define SQ_MIMG_0__R128_MASK 0x8000 15054 #define SQ_MIMG_0__R128__SHIFT 0xf 15055 #define SQ_MIMG_0__TFE_MASK 0x10000 15056 #define SQ_MIMG_0__TFE__SHIFT 0x10 15057 #define SQ_MIMG_0__LWE_MASK 0x20000 15058 #define SQ_MIMG_0__LWE__SHIFT 0x11 15059 #define SQ_MIMG_0__OP_MASK 0x1fc0000 15060 #define SQ_MIMG_0__OP__SHIFT 0x12 15061 #define SQ_MIMG_0__SLC_MASK 0x2000000 15062 #define SQ_MIMG_0__SLC__SHIFT 0x19 15063 #define SQ_MIMG_0__ENCODING_MASK 0xfc000000 15064 #define SQ_MIMG_0__ENCODING__SHIFT 0x1a 15065 #define SQ_SOPK__SIMM16_MASK 0xffff 15066 #define SQ_SOPK__SIMM16__SHIFT 0x0 15067 #define SQ_SOPK__SDST_MASK 0x7f0000 15068 #define SQ_SOPK__SDST__SHIFT 0x10 15069 #define SQ_SOPK__OP_MASK 0xf800000 15070 #define SQ_SOPK__OP__SHIFT 0x17 15071 #define SQ_SOPK__ENCODING_MASK 0xf0000000 15072 #define SQ_SOPK__ENCODING__SHIFT 0x1c 15073 #define SQ_DS_0__OFFSET0_MASK 0xff 15074 #define SQ_DS_0__OFFSET0__SHIFT 0x0 15075 #define SQ_DS_0__OFFSET1_MASK 0xff00 15076 #define SQ_DS_0__OFFSET1__SHIFT 0x8 15077 #define SQ_DS_0__GDS_MASK 0x10000 15078 #define SQ_DS_0__GDS__SHIFT 0x10 15079 #define SQ_DS_0__OP_MASK 0x1fe0000 15080 #define SQ_DS_0__OP__SHIFT 0x11 15081 #define SQ_DS_0__ENCODING_MASK 0xfc000000 15082 #define SQ_DS_0__ENCODING__SHIFT 0x1a 15083 #define SQ_VOP_DPP__SRC0_MASK 0xff 15084 #define SQ_VOP_DPP__SRC0__SHIFT 0x0 15085 #define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00 15086 #define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 15087 #define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000 15088 #define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 15089 #define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000 15090 #define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 15091 #define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000 15092 #define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 15093 #define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000 15094 #define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 15095 #define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000 15096 #define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 15097 #define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000 15098 #define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 15099 #define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000 15100 #define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c 15101 #define SQ_VOPC__SRC0_MASK 0x1ff 15102 #define SQ_VOPC__SRC0__SHIFT 0x0 15103 #define SQ_VOPC__VSRC1_MASK 0x1fe00 15104 #define SQ_VOPC__VSRC1__SHIFT 0x9 15105 #define SQ_VOPC__OP_MASK 0x1fe0000 15106 #define SQ_VOPC__OP__SHIFT 0x11 15107 #define SQ_VOPC__ENCODING_MASK 0xfe000000 15108 #define SQ_VOPC__ENCODING__SHIFT 0x19 15109 #define SQ_VINTRP__VSRC_MASK 0xff 15110 #define SQ_VINTRP__VSRC__SHIFT 0x0 15111 #define SQ_VINTRP__ATTRCHAN_MASK 0x300 15112 #define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 15113 #define SQ_VINTRP__ATTR_MASK 0xfc00 15114 #define SQ_VINTRP__ATTR__SHIFT 0xa 15115 #define SQ_VINTRP__OP_MASK 0x30000 15116 #define SQ_VINTRP__OP__SHIFT 0x10 15117 #define SQ_VINTRP__VDST_MASK 0x3fc0000 15118 #define SQ_VINTRP__VDST__SHIFT 0x12 15119 #define SQ_VINTRP__ENCODING_MASK 0xfc000000 15120 #define SQ_VINTRP__ENCODING__SHIFT 0x1a 15121 #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf 15122 #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 15123 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 15124 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 15125 #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 15126 #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc 15127 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 15128 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 15129 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 15130 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 15131 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 15132 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a 15133 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 15134 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b 15135 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 15136 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c 15137 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 15138 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 15139 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 15140 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 15141 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 15142 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 15143 #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf 15144 #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 15145 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 15146 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 15147 #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 15148 #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc 15149 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000 15150 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 15151 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 15152 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 15153 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 15154 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a 15155 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 15156 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b 15157 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 15158 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c 15159 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 15160 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 15161 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 15162 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e 15163 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 15164 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f 15165 #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf 15166 #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 15167 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 15168 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 15169 #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 15170 #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc 15171 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000 15172 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 15173 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 15174 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 15175 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 15176 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a 15177 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 15178 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b 15179 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 15180 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c 15181 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 15182 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 15183 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 15184 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e 15185 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 15186 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f 15187 #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf 15188 #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 15189 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 15190 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 15191 #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 15192 #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc 15193 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000 15194 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 15195 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 15196 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 15197 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 15198 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a 15199 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 15200 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b 15201 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 15202 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c 15203 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 15204 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 15205 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 15206 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e 15207 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 15208 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f 15209 #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf 15210 #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 15211 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 15212 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 15213 #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 15214 #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc 15215 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000 15216 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18 15217 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 15218 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 15219 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 15220 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a 15221 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 15222 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b 15223 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 15224 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c 15225 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 15226 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 15227 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 15228 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e 15229 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 15230 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f 15231 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 15232 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 15233 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 15234 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 15235 #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 15236 #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 15237 #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 15238 #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 15239 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 15240 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 15241 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 15242 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 15243 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 15244 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 15245 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 15246 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 15247 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 15248 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 15249 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 15250 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 15251 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 15252 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa 15253 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 15254 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb 15255 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 15256 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc 15257 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 15258 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd 15259 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 15260 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe 15261 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 15262 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf 15263 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 15264 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 15265 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 15266 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 15267 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 15268 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 15269 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 15270 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 15271 #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 15272 #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 15273 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 15274 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 15275 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 15276 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 15277 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 15278 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 15279 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 15280 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 15281 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 15282 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 15283 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 15284 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a 15285 #define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 15286 #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b 15287 #define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 15288 #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c 15289 #define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 15290 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d 15291 #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 15292 #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e 15293 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 15294 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f 15295 #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 15296 #define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 15297 #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 15298 #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 15299 #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 15300 #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 15301 #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 15302 #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 15303 #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 15304 #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 15305 #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 15306 #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 15307 #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 15308 #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 15309 #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 15310 #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 15311 #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 15312 #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 15313 #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 15314 #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 15315 #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 15316 #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa 15317 #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 15318 #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb 15319 #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 15320 #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc 15321 #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 15322 #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd 15323 #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 15324 #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe 15325 #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 15326 #define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf 15327 #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 15328 #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 15329 #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 15330 #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 15331 #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 15332 #define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 15333 #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 15334 #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 15335 #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 15336 #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 15337 #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 15338 #define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 15339 #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 15340 #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 15341 #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 15342 #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 15343 #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 15344 #define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 15345 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 15346 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 15347 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 15348 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a 15349 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 15350 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b 15351 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 15352 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c 15353 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 15354 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d 15355 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 15356 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e 15357 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 15358 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f 15359 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 15360 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 15361 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 15362 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 15363 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 15364 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 15365 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 15366 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 15367 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 15368 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 15369 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 15370 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 15371 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 15372 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 15373 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 15374 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 15375 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 15376 #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 15377 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 15378 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 15379 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 15380 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa 15381 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 15382 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb 15383 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 15384 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc 15385 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 15386 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd 15387 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 15388 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe 15389 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 15390 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf 15391 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 15392 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 15393 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 15394 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 15395 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 15396 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 15397 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 15398 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 15399 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 15400 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 15401 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 15402 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 15403 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 15404 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 15405 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 15406 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 15407 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 15408 #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 15409 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 15410 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 15411 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 15412 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a 15413 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 15414 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b 15415 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 15416 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c 15417 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 15418 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d 15419 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 15420 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e 15421 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 15422 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f 15423 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 15424 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 15425 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 15426 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 15427 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 15428 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 15429 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 15430 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 15431 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 15432 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 15433 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 15434 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 15435 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 15436 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 15437 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 15438 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 15439 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 15440 #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 15441 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 15442 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 15443 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 15444 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa 15445 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 15446 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb 15447 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 15448 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc 15449 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 15450 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd 15451 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 15452 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe 15453 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 15454 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf 15455 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 15456 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 15457 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 15458 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 15459 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 15460 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 15461 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 15462 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 15463 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 15464 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 15465 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 15466 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 15467 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 15468 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 15469 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 15470 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 15471 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 15472 #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 15473 #define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 15474 #define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 15475 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f 15476 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 15477 #define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80 15478 #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7 15479 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 15480 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 15481 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 15482 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 15483 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 15484 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 15485 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 15486 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 15487 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 15488 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 15489 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 15490 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 15491 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 15492 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 15493 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 15494 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 15495 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 15496 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 15497 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 15498 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 15499 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 15500 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 15501 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 15502 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 15503 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 15504 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 15505 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 15506 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 15507 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 15508 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 15509 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 15510 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 15511 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15512 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15513 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15514 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15515 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15516 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15517 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15518 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15519 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 15520 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 15521 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 15522 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 15523 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 15524 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 15525 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 15526 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 15527 #define TCC_CTRL__CACHE_SIZE_MASK 0x3 15528 #define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 15529 #define TCC_CTRL__RATE_MASK 0xc 15530 #define TCC_CTRL__RATE__SHIFT 0x2 15531 #define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 15532 #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 15533 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 15534 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 15535 #define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 15536 #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc 15537 #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 15538 #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 15539 #define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 15540 #define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 15541 #define TCC_CTRL__MDC_SIZE_MASK 0x3000000 15542 #define TCC_CTRL__MDC_SIZE__SHIFT 0x18 15543 #define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000 15544 #define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a 15545 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000 15546 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c 15547 #define TCC_EDC_CNT__SEC_COUNT_MASK 0xff 15548 #define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0 15549 #define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000 15550 #define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10 15551 #define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 15552 #define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 15553 #define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 15554 #define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 15555 #define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2 15556 #define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 15557 #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 15558 #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 15559 #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 15560 #define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 15561 #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 15562 #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 15563 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 15564 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 15565 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 15566 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 15567 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 15568 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 15569 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 15570 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 15571 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 15572 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 15573 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 15574 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 15575 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 15576 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15577 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 15578 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 15579 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 15580 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 15581 #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf 15582 #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 15583 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 15584 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 15585 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 15586 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 15587 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 15588 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 15589 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 15590 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 15591 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 15592 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 15593 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 15594 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 15595 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 15596 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 15597 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 15598 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 15599 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 15600 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 15601 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 15602 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 15603 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 15604 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 15605 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 15606 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 15607 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 15608 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 15609 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 15610 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 15611 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 15612 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 15613 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 15614 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 15615 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 15616 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 15617 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 15618 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 15619 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 15620 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 15621 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 15622 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 15623 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 15624 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 15625 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 15626 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 15627 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 15628 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 15629 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 15630 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 15631 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 15632 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 15633 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 15634 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 15635 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 15636 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 15637 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 15638 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 15639 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 15640 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 15641 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 15642 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 15643 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 15644 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 15645 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 15646 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 15647 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 15648 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 15649 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15650 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15651 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15652 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15653 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 15654 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 15655 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 15656 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 15657 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15658 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15659 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15660 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15661 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 15662 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 15663 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 15664 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 15665 #define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf 15666 #define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 15667 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 15668 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 15669 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 15670 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 15671 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 15672 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 15673 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 15674 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 15675 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 15676 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 15677 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 15678 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 15679 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 15680 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 15681 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 15682 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 15683 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 15684 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 15685 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 15686 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 15687 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 15688 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 15689 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 15690 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 15691 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 15692 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 15693 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 15694 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 15695 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 15696 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 15697 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 15698 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 15699 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 15700 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 15701 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 15702 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 15703 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 15704 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 15705 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 15706 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 15707 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 15708 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 15709 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 15710 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 15711 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 15712 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 15713 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 15714 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 15715 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15716 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15717 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15718 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15719 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 15720 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 15721 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 15722 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 15723 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15724 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15725 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15726 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15727 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 15728 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 15729 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 15730 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 15731 #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff 15732 #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 15733 #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff 15734 #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 15735 #define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 15736 #define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 15737 #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 15738 #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 15739 #define TD_CNTL__PAD_STALL_EN_MASK 0x100 15740 #define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 15741 #define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 15742 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 15743 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 15744 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb 15745 #define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 15746 #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf 15747 #define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 15748 #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 15749 #define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 15750 #define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 15751 #define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 15752 #define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 15753 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 15754 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 15755 #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000 15756 #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 15757 #define TD_STATUS__BUSY_MASK 0x80000000 15758 #define TD_STATUS__BUSY__SHIFT 0x1f 15759 #define TD_DEBUG_INDEX__INDEX_MASK 0x1f 15760 #define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 15761 #define TD_DEBUG_DATA__DATA_MASK 0xffffffff 15762 #define TD_DEBUG_DATA__DATA__SHIFT 0x0 15763 #define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1 15764 #define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0 15765 #define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2 15766 #define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1 15767 #define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4 15768 #define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2 15769 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 15770 #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 15771 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 15772 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 15773 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 15774 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 15775 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 15776 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 15777 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 15778 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 15779 #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 15780 #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 15781 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 15782 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 15783 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 15784 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 15785 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 15786 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 15787 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 15788 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 15789 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff 15790 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 15791 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 15792 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 15793 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 15794 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 15795 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 15796 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 15797 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15798 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15799 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15800 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15801 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15802 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15803 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15804 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15805 #define TD_SCRATCH__SCRATCH_MASK 0xffffffff 15806 #define TD_SCRATCH__SCRATCH__SHIFT 0x0 15807 #define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 15808 #define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd 15809 #define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 15810 #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 15811 #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 15812 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 15813 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 15814 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 15815 #define TA_CNTL_AUX__RESERVED_MASK 0xe 15816 #define TA_CNTL_AUX__RESERVED__SHIFT 0x1 15817 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 15818 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 15819 #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000 15820 #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 15821 #define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000 15822 #define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 15823 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000 15824 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 15825 #define TA_RESERVED_010C__Unused_MASK 0xffffffff 15826 #define TA_RESERVED_010C__Unused__SHIFT 0x0 15827 #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff 15828 #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 15829 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff 15830 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 15831 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 15832 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc 15833 #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 15834 #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd 15835 #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 15836 #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe 15837 #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 15838 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 15839 #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 15840 #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 15841 #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 15842 #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 15843 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 15844 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 15845 #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 15846 #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 15847 #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 15848 #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 15849 #define TA_STATUS__IN_BUSY_MASK 0x1000000 15850 #define TA_STATUS__IN_BUSY__SHIFT 0x18 15851 #define TA_STATUS__FG_BUSY_MASK 0x2000000 15852 #define TA_STATUS__FG_BUSY__SHIFT 0x19 15853 #define TA_STATUS__LA_BUSY_MASK 0x4000000 15854 #define TA_STATUS__LA_BUSY__SHIFT 0x1a 15855 #define TA_STATUS__FL_BUSY_MASK 0x8000000 15856 #define TA_STATUS__FL_BUSY__SHIFT 0x1b 15857 #define TA_STATUS__TA_BUSY_MASK 0x10000000 15858 #define TA_STATUS__TA_BUSY__SHIFT 0x1c 15859 #define TA_STATUS__FA_BUSY_MASK 0x20000000 15860 #define TA_STATUS__FA_BUSY__SHIFT 0x1d 15861 #define TA_STATUS__AL_BUSY_MASK 0x40000000 15862 #define TA_STATUS__AL_BUSY__SHIFT 0x1e 15863 #define TA_STATUS__BUSY_MASK 0x80000000 15864 #define TA_STATUS__BUSY__SHIFT 0x1f 15865 #define TA_DEBUG_INDEX__INDEX_MASK 0x1f 15866 #define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 15867 #define TA_DEBUG_DATA__DATA_MASK 0xffffffff 15868 #define TA_DEBUG_DATA__DATA__SHIFT 0x0 15869 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 15870 #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 15871 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 15872 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 15873 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 15874 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 15875 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 15876 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 15877 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 15878 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 15879 #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 15880 #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 15881 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 15882 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 15883 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 15884 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 15885 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 15886 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 15887 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 15888 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 15889 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff 15890 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 15891 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 15892 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 15893 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 15894 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 15895 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 15896 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 15897 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 15898 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 15899 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 15900 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 15901 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 15902 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 15903 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 15904 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 15905 #define TA_SCRATCH__SCRATCH_MASK 0xffffffff 15906 #define TA_SCRATCH__SCRATCH__SHIFT 0x0 15907 #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff 15908 #define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 15909 #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 15910 #define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 15911 #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 15912 #define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 15913 #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 15914 #define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 15915 #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 15916 #define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 15917 #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 15918 #define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 15919 #define TCP_INVALIDATE__START_MASK 0x1 15920 #define TCP_INVALIDATE__START__SHIFT 0x0 15921 #define TCP_STATUS__TCP_BUSY_MASK 0x1 15922 #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 15923 #define TCP_STATUS__INPUT_BUSY_MASK 0x2 15924 #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 15925 #define TCP_STATUS__ADRS_BUSY_MASK 0x4 15926 #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 15927 #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8 15928 #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 15929 #define TCP_STATUS__CNTRL_BUSY_MASK 0x10 15930 #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 15931 #define TCP_STATUS__LFIFO_BUSY_MASK 0x20 15932 #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 15933 #define TCP_STATUS__READ_BUSY_MASK 0x40 15934 #define TCP_STATUS__READ_BUSY__SHIFT 0x6 15935 #define TCP_STATUS__FORMAT_BUSY_MASK 0x80 15936 #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 15937 #define TCP_CNTL__FORCE_HIT_MASK 0x1 15938 #define TCP_CNTL__FORCE_HIT__SHIFT 0x0 15939 #define TCP_CNTL__FORCE_MISS_MASK 0x2 15940 #define TCP_CNTL__FORCE_MISS__SHIFT 0x1 15941 #define TCP_CNTL__L1_SIZE_MASK 0xc 15942 #define TCP_CNTL__L1_SIZE__SHIFT 0x2 15943 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 15944 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 15945 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 15946 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 15947 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 15948 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf 15949 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 15950 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 15951 #define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 15952 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c 15953 #define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 15954 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 15955 #define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf 15956 #define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 15957 #define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 15958 #define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 15959 #define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 15960 #define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 15961 #define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 15962 #define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc 15963 #define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 15964 #define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 15965 #define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 15966 #define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 15967 #define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 15968 #define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 15969 #define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 15970 #define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c 15971 #define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf 15972 #define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 15973 #define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 15974 #define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 15975 #define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 15976 #define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 15977 #define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 15978 #define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc 15979 #define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 15980 #define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 15981 #define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 15982 #define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 15983 #define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 15984 #define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 15985 #define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 15986 #define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c 15987 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf 15988 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 15989 #define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 15990 #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 15991 #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 15992 #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 15993 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 15994 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 15995 #define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff 15996 #define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 15997 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 15998 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 15999 #define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 16000 #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 16001 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 16002 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 16003 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 16004 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 16005 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 16006 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 16007 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 16008 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 16009 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 16010 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 16011 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 16012 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 16013 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 16014 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 16015 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 16016 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 16017 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 16018 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 16019 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 16020 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 16021 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 16022 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 16023 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 16024 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 16025 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 16026 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 16027 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 16028 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 16029 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 16030 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 16031 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 16032 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 16033 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 16034 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 16035 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 16036 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 16037 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff 16038 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 16039 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 16040 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 16041 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 16042 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 16043 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff 16044 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 16045 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 16046 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 16047 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 16048 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 16049 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 16050 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 16051 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 16052 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 16053 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 16054 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 16055 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 16056 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 16057 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 16058 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 16059 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 16060 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 16061 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 16062 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 16063 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 16064 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 16065 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 16066 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 16067 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 16068 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 16069 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 16070 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 16071 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 16072 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 16073 #define TCP_EDC_CNT__SEC_COUNT_MASK 0xff 16074 #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 16075 #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00 16076 #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 16077 #define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000 16078 #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 16079 #define TCP_EDC_CNT__UNUSED_MASK 0xff000000 16080 #define TCP_EDC_CNT__UNUSED__SHIFT 0x18 16081 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 16082 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 16083 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc 16084 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 16085 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 16086 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 16087 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 16088 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 16089 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 16090 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 16091 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 16092 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa 16093 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 16094 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc 16095 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 16096 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe 16097 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 16098 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 16099 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 16100 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 16101 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 16102 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 16103 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 16104 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 16105 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 16106 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 16107 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 16108 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 16109 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 16110 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 16111 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 16112 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 16113 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 16114 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 16115 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc 16116 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 16117 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 16118 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 16119 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 16120 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 16121 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 16122 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 16123 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 16124 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa 16125 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 16126 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc 16127 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 16128 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe 16129 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 16130 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 16131 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 16132 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 16133 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 16134 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 16135 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 16136 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 16137 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 16138 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 16139 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 16140 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 16141 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 16142 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 16143 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 16144 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 16145 #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 16146 #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 16147 #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 16148 #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 16149 #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 16150 #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 16151 #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 16152 #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 16153 #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 16154 #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 16155 #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 16156 #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 16157 #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 16158 #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 16159 #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 16160 #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 16161 #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 16162 #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 16163 #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 16164 #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 16165 #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 16166 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa 16167 #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 16168 #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb 16169 #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 16170 #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc 16171 #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 16172 #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd 16173 #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 16174 #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe 16175 #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 16176 #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf 16177 #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 16178 #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 16179 #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 16180 #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 16181 #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 16182 #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 16183 #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 16184 #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 16185 #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 16186 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 16187 #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 16188 #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 16189 #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 16190 #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 16191 #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 16192 #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 16193 #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 16194 #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 16195 #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 16196 #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 16197 #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 16198 #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a 16199 #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 16200 #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b 16201 #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 16202 #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c 16203 #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 16204 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 16205 #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 16206 #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e 16207 #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 16208 #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f 16209 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 16210 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 16211 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc 16212 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 16213 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 16214 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 16215 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 16216 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 16217 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 16218 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 16219 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 16220 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa 16221 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 16222 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc 16223 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 16224 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe 16225 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 16226 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 16227 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 16228 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 16229 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 16230 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 16231 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 16232 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 16233 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 16234 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 16235 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 16236 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 16237 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 16238 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 16239 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 16240 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 16241 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 16242 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 16243 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc 16244 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 16245 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 16246 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 16247 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 16248 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 16249 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 16250 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 16251 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 16252 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa 16253 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 16254 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc 16255 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 16256 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe 16257 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 16258 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 16259 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 16260 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 16261 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 16262 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 16263 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 16264 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 16265 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 16266 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 16267 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 16268 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 16269 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 16270 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 16271 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 16272 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 16273 #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 16274 #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 16275 #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc 16276 #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 16277 #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 16278 #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 16279 #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 16280 #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 16281 #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 16282 #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 16283 #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 16284 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa 16285 #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 16286 #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc 16287 #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 16288 #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe 16289 #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 16290 #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 16291 #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 16292 #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 16293 #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 16294 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 16295 #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 16296 #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 16297 #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 16298 #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 16299 #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 16300 #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a 16301 #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 16302 #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c 16303 #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 16304 #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e 16305 #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 16306 #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 16307 #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc 16308 #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 16309 #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 16310 #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 16311 #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 16312 #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 16313 #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 16314 #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 16315 #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 16316 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa 16317 #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 16318 #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc 16319 #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 16320 #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe 16321 #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 16322 #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 16323 #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 16324 #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 16325 #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 16326 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 16327 #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 16328 #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 16329 #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 16330 #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 16331 #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 16332 #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a 16333 #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 16334 #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c 16335 #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 16336 #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e 16337 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 16338 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 16339 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc 16340 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 16341 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 16342 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 16343 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 16344 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 16345 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 16346 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 16347 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 16348 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa 16349 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 16350 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc 16351 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 16352 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe 16353 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 16354 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 16355 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 16356 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 16357 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 16358 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 16359 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 16360 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 16361 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 16362 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 16363 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 16364 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a 16365 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 16366 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c 16367 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 16368 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e 16369 #define TC_CFG_L1_VOLATILE__VOL_MASK 0xf 16370 #define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 16371 #define TC_CFG_L2_VOLATILE__VOL_MASK 0xf 16372 #define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 16373 #define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff 16374 #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 16375 #define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff 16376 #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 16377 #define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff 16378 #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 16379 #define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff 16380 #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 16381 #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 16382 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 16383 #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 16384 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 16385 #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 16386 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 16387 #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 16388 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 16389 #define TCP_WATCH0_CNTL__MASK_MASK 0xffffff 16390 #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 16391 #define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 16392 #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 16393 #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 16394 #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 16395 #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 16396 #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f 16397 #define TCP_WATCH1_CNTL__MASK_MASK 0xffffff 16398 #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 16399 #define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 16400 #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 16401 #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 16402 #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 16403 #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 16404 #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f 16405 #define TCP_WATCH2_CNTL__MASK_MASK 0xffffff 16406 #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 16407 #define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 16408 #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 16409 #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 16410 #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 16411 #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 16412 #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f 16413 #define TCP_WATCH3_CNTL__MASK_MASK 0xffffff 16414 #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 16415 #define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 16416 #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 16417 #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 16418 #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 16419 #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 16420 #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f 16421 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000 16422 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 16423 #define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000 16424 #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a 16425 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000 16426 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b 16427 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 16428 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 16429 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 16430 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 16431 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff 16432 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 16433 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1 16434 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 16435 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2 16436 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 16437 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4 16438 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 16439 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 16440 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 16441 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 16442 #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 16443 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18 16444 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 16445 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20 16446 #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 16447 #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff 16448 #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 16449 #define TD_CGTT_CTRL__ON_DELAY_MASK 0xf 16450 #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 16451 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 16452 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16453 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 16454 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 16455 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 16456 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 16457 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 16458 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 16459 #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 16460 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 16461 #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 16462 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 16463 #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 16464 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16465 #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 16466 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 16467 #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 16468 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 16469 #define TA_CGTT_CTRL__ON_DELAY_MASK 0xf 16470 #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 16471 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 16472 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16473 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 16474 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 16475 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 16476 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 16477 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 16478 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 16479 #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 16480 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 16481 #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 16482 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 16483 #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 16484 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16485 #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 16486 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 16487 #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 16488 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 16489 #define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf 16490 #define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 16491 #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 16492 #define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16493 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 16494 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 16495 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 16496 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 16497 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 16498 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 16499 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 16500 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 16501 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 16502 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 16503 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 16504 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16505 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 16506 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 16507 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 16508 #define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 16509 #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf 16510 #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 16511 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 16512 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16513 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 16514 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 16515 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 16516 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 16517 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 16518 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 16519 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 16520 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 16521 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 16522 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 16523 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 16524 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16525 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 16526 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 16527 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 16528 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 16529 #define TCI_STATUS__TCI_BUSY_MASK 0x1 16530 #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 16531 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff 16532 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 16533 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 16534 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 16535 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 16536 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 16537 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 16538 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 16539 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe 16540 #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 16541 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 16542 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 16543 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 16544 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 16545 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 16546 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 16547 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 16548 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 16549 #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 16550 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 16551 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 16552 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 16553 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 16554 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 16555 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 16556 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 16557 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 16558 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 16559 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 16560 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 16561 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 16562 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 16563 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80 16564 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 16565 #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100 16566 #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 16567 #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200 16568 #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 16569 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400 16570 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa 16571 #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800 16572 #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb 16573 #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000 16574 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc 16575 #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000 16576 #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd 16577 #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000 16578 #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe 16579 #define GDS_ENHANCE2__MISC_MASK 0xffff 16580 #define GDS_ENHANCE2__MISC__SHIFT 0x0 16581 #define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 16582 #define GDS_ENHANCE2__UNUSED__SHIFT 0x10 16583 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 16584 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 16585 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 16586 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 16587 #define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 16588 #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 16589 #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 16590 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 16591 #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 16592 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 16593 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 16594 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa 16595 #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 16596 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc 16597 #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 16598 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 16599 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 16600 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 16601 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 16602 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 16603 #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 16604 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 16605 #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 16606 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 16607 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 16608 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 16609 #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 16610 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 16611 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 16612 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 16613 #define GDS_EDC_CNT__DED_MASK 0xff 16614 #define GDS_EDC_CNT__DED__SHIFT 0x0 16615 #define GDS_EDC_CNT__SED_MASK 0xff00 16616 #define GDS_EDC_CNT__SED__SHIFT 0x8 16617 #define GDS_EDC_CNT__SEC_MASK 0xff0000 16618 #define GDS_EDC_CNT__SEC__SHIFT 0x10 16619 #define GDS_EDC_GRBM_CNT__DED_MASK 0xff 16620 #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 16621 #define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000 16622 #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10 16623 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 16624 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 16625 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 16626 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 16627 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4 16628 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 16629 #define GDS_EDC_OA_DED__UNUSED0_MASK 0x8 16630 #define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3 16631 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10 16632 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 16633 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20 16634 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 16635 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40 16636 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 16637 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80 16638 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 16639 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100 16640 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 16641 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200 16642 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 16643 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400 16644 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa 16645 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800 16646 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb 16647 #define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000 16648 #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc 16649 #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f 16650 #define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 16651 #define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 16652 #define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 16653 #define GDS_DEBUG_DATA__DATA_MASK 0xffffffff 16654 #define GDS_DEBUG_DATA__DATA__SHIFT 0x0 16655 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1 16656 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0 16657 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2 16658 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1 16659 #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4 16660 #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 16661 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8 16662 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3 16663 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10 16664 #define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4 16665 #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20 16666 #define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5 16667 #define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0 16668 #define GDS_DSM_CNTL__UNUSED__SHIFT 0x6 16669 #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf 16670 #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 16671 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 16672 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16673 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 16674 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 16675 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 16676 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 16677 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 16678 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 16679 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 16680 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 16681 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 16682 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 16683 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 16684 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 16685 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 16686 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 16687 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 16688 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 16689 #define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff 16690 #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 16691 #define GDS_RD_DATA__READ_DATA_MASK 0xffffffff 16692 #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 16693 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff 16694 #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 16695 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff 16696 #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 16697 #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff 16698 #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 16699 #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff 16700 #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 16701 #define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff 16702 #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 16703 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff 16704 #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 16705 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff 16706 #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 16707 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff 16708 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 16709 #define GDS_ATOM_CNTL__AINC_MASK 0x3f 16710 #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 16711 #define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 16712 #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 16713 #define GDS_ATOM_CNTL__DMODE_MASK 0x300 16714 #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 16715 #define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00 16716 #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa 16717 #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 16718 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 16719 #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe 16720 #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 16721 #define GDS_ATOM_BASE__BASE_MASK 0xffff 16722 #define GDS_ATOM_BASE__BASE__SHIFT 0x0 16723 #define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 16724 #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 16725 #define GDS_ATOM_SIZE__SIZE_MASK 0xffff 16726 #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 16727 #define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 16728 #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 16729 #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff 16730 #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 16731 #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 16732 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 16733 #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff 16734 #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 16735 #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 16736 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 16737 #define GDS_ATOM_DST__DST_MASK 0xffffffff 16738 #define GDS_ATOM_DST__DST__SHIFT 0x0 16739 #define GDS_ATOM_OP__OP_MASK 0xff 16740 #define GDS_ATOM_OP__OP__SHIFT 0x0 16741 #define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 16742 #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 16743 #define GDS_ATOM_SRC0__DATA_MASK 0xffffffff 16744 #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 16745 #define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff 16746 #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 16747 #define GDS_ATOM_SRC1__DATA_MASK 0xffffffff 16748 #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 16749 #define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff 16750 #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 16751 #define GDS_ATOM_READ0__DATA_MASK 0xffffffff 16752 #define GDS_ATOM_READ0__DATA__SHIFT 0x0 16753 #define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff 16754 #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 16755 #define GDS_ATOM_READ1__DATA_MASK 0xffffffff 16756 #define GDS_ATOM_READ1__DATA__SHIFT 0x0 16757 #define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff 16758 #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 16759 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f 16760 #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 16761 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 16762 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 16763 #define GDS_GWS_RESOURCE__FLAG_MASK 0x1 16764 #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 16765 #define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe 16766 #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 16767 #define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 16768 #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd 16769 #define GDS_GWS_RESOURCE__DED_MASK 0x4000 16770 #define GDS_GWS_RESOURCE__DED__SHIFT 0xe 16771 #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 16772 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf 16773 #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000 16774 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 16775 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000 16776 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b 16777 #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000 16778 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c 16779 #define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000 16780 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d 16781 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff 16782 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 16783 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 16784 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 16785 #define GDS_OA_CNTL__INDEX_MASK 0xf 16786 #define GDS_OA_CNTL__INDEX__SHIFT 0x0 16787 #define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 16788 #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 16789 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff 16790 #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 16791 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff 16792 #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 16793 #define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000 16794 #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 16795 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000 16796 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 16797 #define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000 16798 #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 16799 #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 16800 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e 16801 #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 16802 #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f 16803 #define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff 16804 #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 16805 #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 16806 #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f 16807 #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff 16808 #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 16809 #define GDS_DEBUG_REG0__spare1_MASK 0x3f 16810 #define GDS_DEBUG_REG0__spare1__SHIFT 0x0 16811 #define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 16812 #define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 16813 #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 16814 #define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 16815 #define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 16816 #define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc 16817 #define GDS_DEBUG_REG0__cstate_MASK 0x1e000 16818 #define GDS_DEBUG_REG0__cstate__SHIFT 0xd 16819 #define GDS_DEBUG_REG0__buff_write_MASK 0x20000 16820 #define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 16821 #define GDS_DEBUG_REG0__flush_request_MASK 0x40000 16822 #define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 16823 #define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 16824 #define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 16825 #define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 16826 #define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 16827 #define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 16828 #define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 16829 #define GDS_DEBUG_REG0__spare_MASK 0xffc00000 16830 #define GDS_DEBUG_REG0__spare__SHIFT 0x16 16831 #define GDS_DEBUG_REG1__tag_hit_MASK 0x1 16832 #define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 16833 #define GDS_DEBUG_REG1__tag_miss_MASK 0x2 16834 #define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 16835 #define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc 16836 #define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 16837 #define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 16838 #define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 16839 #define GDS_DEBUG_REG1__data_ready_MASK 0x40000 16840 #define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 16841 #define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 16842 #define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 16843 #define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 16844 #define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 16845 #define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 16846 #define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 16847 #define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 16848 #define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 16849 #define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 16850 #define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 16851 #define GDS_DEBUG_REG1__spare_MASK 0xff000000 16852 #define GDS_DEBUG_REG1__spare__SHIFT 0x18 16853 #define GDS_DEBUG_REG2__ds_full_MASK 0x1 16854 #define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 16855 #define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 16856 #define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 16857 #define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 16858 #define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 16859 #define GDS_DEBUG_REG2__cmd_write_MASK 0x8 16860 #define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 16861 #define GDS_DEBUG_REG2__app_sel_MASK 0xf0 16862 #define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 16863 #define GDS_DEBUG_REG2__req_MASK 0x7fff00 16864 #define GDS_DEBUG_REG2__req__SHIFT 0x8 16865 #define GDS_DEBUG_REG2__spare_MASK 0xff800000 16866 #define GDS_DEBUG_REG2__spare__SHIFT 0x17 16867 #define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff 16868 #define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 16869 #define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 16870 #define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb 16871 #define GDS_DEBUG_REG3__spare_MASK 0xffff8000 16872 #define GDS_DEBUG_REG3__spare__SHIFT 0xf 16873 #define GDS_DEBUG_REG4__gws_busy_MASK 0x1 16874 #define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 16875 #define GDS_DEBUG_REG4__gws_req_MASK 0x2 16876 #define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 16877 #define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 16878 #define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 16879 #define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 16880 #define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 16881 #define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 16882 #define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 16883 #define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 16884 #define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa 16885 #define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 16886 #define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb 16887 #define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 16888 #define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc 16889 #define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 16890 #define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd 16891 #define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 16892 #define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe 16893 #define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 16894 #define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf 16895 #define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 16896 #define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 16897 #define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 16898 #define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 16899 #define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 16900 #define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 16901 #define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 16902 #define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 16903 #define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 16904 #define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 16905 #define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 16906 #define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 16907 #define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 16908 #define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 16909 #define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 16910 #define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 16911 #define GDS_DEBUG_REG4__spare_MASK 0xff000000 16912 #define GDS_DEBUG_REG4__spare__SHIFT 0x18 16913 #define GDS_DEBUG_REG5__write_dis_MASK 0x1 16914 #define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 16915 #define GDS_DEBUG_REG5__dec_error_MASK 0x2 16916 #define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 16917 #define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 16918 #define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 16919 #define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 16920 #define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 16921 #define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 16922 #define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 16923 #define GDS_DEBUG_REG5__spare_MASK 0xe0 16924 #define GDS_DEBUG_REG5__spare__SHIFT 0x5 16925 #define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 16926 #define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 16927 #define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 16928 #define GDS_DEBUG_REG5__spare1__SHIFT 0x16 16929 #define GDS_DEBUG_REG6__oa_busy_MASK 0x1 16930 #define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 16931 #define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e 16932 #define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 16933 #define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 16934 #define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 16935 #define GDS_DEBUG_REG6__spare_MASK 0xffe00000 16936 #define GDS_DEBUG_REG6__spare__SHIFT 0x15 16937 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 16938 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 16939 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 16940 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 16941 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 16942 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 16943 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 16944 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 16945 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 16946 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 16947 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 16948 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 16949 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 16950 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 16951 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 16952 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 16953 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 16954 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 16955 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff 16956 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 16957 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 16958 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 16959 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 16960 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 16961 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 16962 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 16963 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 16964 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 16965 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 16966 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 16967 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 16968 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 16969 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 16970 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 16971 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 16972 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 16973 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 16974 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 16975 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 16976 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 16977 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff 16978 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 16979 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 16980 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 16981 #define GDS_VMID0_BASE__BASE_MASK 0xffff 16982 #define GDS_VMID0_BASE__BASE__SHIFT 0x0 16983 #define GDS_VMID1_BASE__BASE_MASK 0xffff 16984 #define GDS_VMID1_BASE__BASE__SHIFT 0x0 16985 #define GDS_VMID2_BASE__BASE_MASK 0xffff 16986 #define GDS_VMID2_BASE__BASE__SHIFT 0x0 16987 #define GDS_VMID3_BASE__BASE_MASK 0xffff 16988 #define GDS_VMID3_BASE__BASE__SHIFT 0x0 16989 #define GDS_VMID4_BASE__BASE_MASK 0xffff 16990 #define GDS_VMID4_BASE__BASE__SHIFT 0x0 16991 #define GDS_VMID5_BASE__BASE_MASK 0xffff 16992 #define GDS_VMID5_BASE__BASE__SHIFT 0x0 16993 #define GDS_VMID6_BASE__BASE_MASK 0xffff 16994 #define GDS_VMID6_BASE__BASE__SHIFT 0x0 16995 #define GDS_VMID7_BASE__BASE_MASK 0xffff 16996 #define GDS_VMID7_BASE__BASE__SHIFT 0x0 16997 #define GDS_VMID8_BASE__BASE_MASK 0xffff 16998 #define GDS_VMID8_BASE__BASE__SHIFT 0x0 16999 #define GDS_VMID9_BASE__BASE_MASK 0xffff 17000 #define GDS_VMID9_BASE__BASE__SHIFT 0x0 17001 #define GDS_VMID10_BASE__BASE_MASK 0xffff 17002 #define GDS_VMID10_BASE__BASE__SHIFT 0x0 17003 #define GDS_VMID11_BASE__BASE_MASK 0xffff 17004 #define GDS_VMID11_BASE__BASE__SHIFT 0x0 17005 #define GDS_VMID12_BASE__BASE_MASK 0xffff 17006 #define GDS_VMID12_BASE__BASE__SHIFT 0x0 17007 #define GDS_VMID13_BASE__BASE_MASK 0xffff 17008 #define GDS_VMID13_BASE__BASE__SHIFT 0x0 17009 #define GDS_VMID14_BASE__BASE_MASK 0xffff 17010 #define GDS_VMID14_BASE__BASE__SHIFT 0x0 17011 #define GDS_VMID15_BASE__BASE_MASK 0xffff 17012 #define GDS_VMID15_BASE__BASE__SHIFT 0x0 17013 #define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff 17014 #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 17015 #define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff 17016 #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 17017 #define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff 17018 #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 17019 #define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff 17020 #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 17021 #define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff 17022 #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 17023 #define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff 17024 #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 17025 #define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff 17026 #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 17027 #define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff 17028 #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 17029 #define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff 17030 #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 17031 #define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff 17032 #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 17033 #define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff 17034 #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 17035 #define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff 17036 #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 17037 #define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff 17038 #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 17039 #define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff 17040 #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 17041 #define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff 17042 #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 17043 #define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff 17044 #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 17045 #define GDS_GWS_VMID0__BASE_MASK 0x3f 17046 #define GDS_GWS_VMID0__BASE__SHIFT 0x0 17047 #define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 17048 #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 17049 #define GDS_GWS_VMID1__BASE_MASK 0x3f 17050 #define GDS_GWS_VMID1__BASE__SHIFT 0x0 17051 #define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 17052 #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 17053 #define GDS_GWS_VMID2__BASE_MASK 0x3f 17054 #define GDS_GWS_VMID2__BASE__SHIFT 0x0 17055 #define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 17056 #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 17057 #define GDS_GWS_VMID3__BASE_MASK 0x3f 17058 #define GDS_GWS_VMID3__BASE__SHIFT 0x0 17059 #define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 17060 #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 17061 #define GDS_GWS_VMID4__BASE_MASK 0x3f 17062 #define GDS_GWS_VMID4__BASE__SHIFT 0x0 17063 #define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 17064 #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 17065 #define GDS_GWS_VMID5__BASE_MASK 0x3f 17066 #define GDS_GWS_VMID5__BASE__SHIFT 0x0 17067 #define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 17068 #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 17069 #define GDS_GWS_VMID6__BASE_MASK 0x3f 17070 #define GDS_GWS_VMID6__BASE__SHIFT 0x0 17071 #define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 17072 #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 17073 #define GDS_GWS_VMID7__BASE_MASK 0x3f 17074 #define GDS_GWS_VMID7__BASE__SHIFT 0x0 17075 #define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 17076 #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 17077 #define GDS_GWS_VMID8__BASE_MASK 0x3f 17078 #define GDS_GWS_VMID8__BASE__SHIFT 0x0 17079 #define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 17080 #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 17081 #define GDS_GWS_VMID9__BASE_MASK 0x3f 17082 #define GDS_GWS_VMID9__BASE__SHIFT 0x0 17083 #define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 17084 #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 17085 #define GDS_GWS_VMID10__BASE_MASK 0x3f 17086 #define GDS_GWS_VMID10__BASE__SHIFT 0x0 17087 #define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 17088 #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 17089 #define GDS_GWS_VMID11__BASE_MASK 0x3f 17090 #define GDS_GWS_VMID11__BASE__SHIFT 0x0 17091 #define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 17092 #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 17093 #define GDS_GWS_VMID12__BASE_MASK 0x3f 17094 #define GDS_GWS_VMID12__BASE__SHIFT 0x0 17095 #define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 17096 #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 17097 #define GDS_GWS_VMID13__BASE_MASK 0x3f 17098 #define GDS_GWS_VMID13__BASE__SHIFT 0x0 17099 #define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 17100 #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 17101 #define GDS_GWS_VMID14__BASE_MASK 0x3f 17102 #define GDS_GWS_VMID14__BASE__SHIFT 0x0 17103 #define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 17104 #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 17105 #define GDS_GWS_VMID15__BASE_MASK 0x3f 17106 #define GDS_GWS_VMID15__BASE__SHIFT 0x0 17107 #define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 17108 #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 17109 #define GDS_OA_VMID0__MASK_MASK 0xffff 17110 #define GDS_OA_VMID0__MASK__SHIFT 0x0 17111 #define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 17112 #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 17113 #define GDS_OA_VMID1__MASK_MASK 0xffff 17114 #define GDS_OA_VMID1__MASK__SHIFT 0x0 17115 #define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 17116 #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 17117 #define GDS_OA_VMID2__MASK_MASK 0xffff 17118 #define GDS_OA_VMID2__MASK__SHIFT 0x0 17119 #define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 17120 #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 17121 #define GDS_OA_VMID3__MASK_MASK 0xffff 17122 #define GDS_OA_VMID3__MASK__SHIFT 0x0 17123 #define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 17124 #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 17125 #define GDS_OA_VMID4__MASK_MASK 0xffff 17126 #define GDS_OA_VMID4__MASK__SHIFT 0x0 17127 #define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 17128 #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 17129 #define GDS_OA_VMID5__MASK_MASK 0xffff 17130 #define GDS_OA_VMID5__MASK__SHIFT 0x0 17131 #define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 17132 #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 17133 #define GDS_OA_VMID6__MASK_MASK 0xffff 17134 #define GDS_OA_VMID6__MASK__SHIFT 0x0 17135 #define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 17136 #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 17137 #define GDS_OA_VMID7__MASK_MASK 0xffff 17138 #define GDS_OA_VMID7__MASK__SHIFT 0x0 17139 #define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 17140 #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 17141 #define GDS_OA_VMID8__MASK_MASK 0xffff 17142 #define GDS_OA_VMID8__MASK__SHIFT 0x0 17143 #define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 17144 #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 17145 #define GDS_OA_VMID9__MASK_MASK 0xffff 17146 #define GDS_OA_VMID9__MASK__SHIFT 0x0 17147 #define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 17148 #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 17149 #define GDS_OA_VMID10__MASK_MASK 0xffff 17150 #define GDS_OA_VMID10__MASK__SHIFT 0x0 17151 #define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 17152 #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 17153 #define GDS_OA_VMID11__MASK_MASK 0xffff 17154 #define GDS_OA_VMID11__MASK__SHIFT 0x0 17155 #define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 17156 #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 17157 #define GDS_OA_VMID12__MASK_MASK 0xffff 17158 #define GDS_OA_VMID12__MASK__SHIFT 0x0 17159 #define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 17160 #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 17161 #define GDS_OA_VMID13__MASK_MASK 0xffff 17162 #define GDS_OA_VMID13__MASK__SHIFT 0x0 17163 #define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 17164 #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 17165 #define GDS_OA_VMID14__MASK_MASK 0xffff 17166 #define GDS_OA_VMID14__MASK__SHIFT 0x0 17167 #define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 17168 #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 17169 #define GDS_OA_VMID15__MASK_MASK 0xffff 17170 #define GDS_OA_VMID15__MASK__SHIFT 0x0 17171 #define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 17172 #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 17173 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 17174 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 17175 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 17176 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 17177 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 17178 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 17179 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 17180 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 17181 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 17182 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 17183 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 17184 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 17185 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 17186 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 17187 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 17188 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 17189 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 17190 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 17191 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 17192 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 17193 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 17194 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa 17195 #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 17196 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb 17197 #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 17198 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc 17199 #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 17200 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd 17201 #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 17202 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe 17203 #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 17204 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf 17205 #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 17206 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 17207 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 17208 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 17209 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 17210 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 17211 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 17212 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 17213 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 17214 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 17215 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 17216 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 17217 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 17218 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 17219 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 17220 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 17221 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 17222 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 17223 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 17224 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 17225 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 17226 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a 17227 #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 17228 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b 17229 #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 17230 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c 17231 #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 17232 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 17233 #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 17234 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e 17235 #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 17236 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f 17237 #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 17238 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 17239 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 17240 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 17241 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 17242 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 17243 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 17244 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 17245 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 17246 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 17247 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 17248 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 17249 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 17250 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 17251 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 17252 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 17253 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 17254 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 17255 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 17256 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 17257 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 17258 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa 17259 #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 17260 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb 17261 #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 17262 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc 17263 #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 17264 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd 17265 #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 17266 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe 17267 #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 17268 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf 17269 #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 17270 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 17271 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 17272 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 17273 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 17274 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 17275 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 17276 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 17277 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 17278 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 17279 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 17280 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 17281 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 17282 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 17283 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 17284 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 17285 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 17286 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 17287 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 17288 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 17289 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 17290 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a 17291 #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 17292 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b 17293 #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 17294 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c 17295 #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 17296 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 17297 #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 17298 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e 17299 #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 17300 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f 17301 #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 17302 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 17303 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 17304 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 17305 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 17306 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 17307 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 17308 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 17309 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 17310 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 17311 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 17312 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 17313 #define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 17314 #define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 17315 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 17316 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 17317 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 17318 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 17319 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 17320 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 17321 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 17322 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 17323 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 17324 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 17325 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 17326 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 17327 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 17328 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa 17329 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 17330 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb 17331 #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 17332 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc 17333 #define GDS_OA_RESET__RESET_MASK 0x1 17334 #define GDS_OA_RESET__RESET__SHIFT 0x0 17335 #define GDS_OA_RESET__PIPE_ID_MASK 0xff00 17336 #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 17337 #define GDS_ENHANCE__MISC_MASK 0xffff 17338 #define GDS_ENHANCE__MISC__SHIFT 0x0 17339 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 17340 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 17341 #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 17342 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 17343 #define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 17344 #define GDS_ENHANCE__UNUSED__SHIFT 0x12 17345 #define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff 17346 #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 17347 #define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 17348 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 17349 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 17350 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc 17351 #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000 17352 #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 17353 #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000 17354 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 17355 #define GDS_CS_CTXSW_STATUS__R_MASK 0x1 17356 #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 17357 #define GDS_CS_CTXSW_STATUS__W_MASK 0x2 17358 #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 17359 #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc 17360 #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 17361 #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff 17362 #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 17363 #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000 17364 #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 17365 #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff 17366 #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 17367 #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000 17368 #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 17369 #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff 17370 #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 17371 #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000 17372 #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 17373 #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff 17374 #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 17375 #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000 17376 #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 17377 #define GDS_GFX_CTXSW_STATUS__R_MASK 0x1 17378 #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 17379 #define GDS_GFX_CTXSW_STATUS__W_MASK 0x2 17380 #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 17381 #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc 17382 #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 17383 #define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff 17384 #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 17385 #define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000 17386 #define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 17387 #define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff 17388 #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 17389 #define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000 17390 #define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 17391 #define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff 17392 #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 17393 #define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000 17394 #define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 17395 #define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff 17396 #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 17397 #define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000 17398 #define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 17399 #define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff 17400 #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 17401 #define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000 17402 #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 17403 #define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff 17404 #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 17405 #define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000 17406 #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 17407 #define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff 17408 #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 17409 #define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000 17410 #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 17411 #define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff 17412 #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 17413 #define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000 17414 #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 17415 #define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff 17416 #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 17417 #define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000 17418 #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 17419 #define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff 17420 #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 17421 #define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000 17422 #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 17423 #define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff 17424 #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 17425 #define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000 17426 #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 17427 #define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff 17428 #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 17429 #define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000 17430 #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 17431 #define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff 17432 #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 17433 #define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000 17434 #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 17435 #define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff 17436 #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 17437 #define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000 17438 #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 17439 #define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff 17440 #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 17441 #define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000 17442 #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 17443 #define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff 17444 #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 17445 #define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000 17446 #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 17447 #define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff 17448 #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 17449 #define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000 17450 #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 17451 #define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff 17452 #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 17453 #define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000 17454 #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 17455 #define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff 17456 #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 17457 #define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000 17458 #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 17459 #define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff 17460 #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 17461 #define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000 17462 #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 17463 #define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff 17464 #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 17465 #define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000 17466 #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 17467 #define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff 17468 #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 17469 #define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000 17470 #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 17471 #define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff 17472 #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 17473 #define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000 17474 #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 17475 #define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff 17476 #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 17477 #define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000 17478 #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 17479 #define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff 17480 #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 17481 #define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000 17482 #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 17483 #define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff 17484 #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 17485 #define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000 17486 #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 17487 #define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff 17488 #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 17489 #define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000 17490 #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 17491 #define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff 17492 #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 17493 #define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000 17494 #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 17495 #define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff 17496 #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 17497 #define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000 17498 #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 17499 #define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff 17500 #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 17501 #define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000 17502 #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 17503 #define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff 17504 #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 17505 #define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000 17506 #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 17507 #define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff 17508 #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 17509 #define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000 17510 #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 17511 #define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff 17512 #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 17513 #define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000 17514 #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 17515 #define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff 17516 #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 17517 #define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000 17518 #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 17519 #define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff 17520 #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 17521 #define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000 17522 #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 17523 #define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff 17524 #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 17525 #define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000 17526 #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 17527 #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 17528 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 17529 #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 17530 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 17531 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 17532 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 17533 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc 17534 #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 17535 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 17536 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 17537 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 17538 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 17539 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 17540 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 17541 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f 17542 #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 17543 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 17544 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 17545 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 17546 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b 17547 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff 17548 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 17549 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff 17550 #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 17551 #define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff 17552 #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 17553 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 17554 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 17555 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc 17556 #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 17557 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 17558 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 17559 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40 17560 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 17561 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 17562 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 17563 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 17564 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa 17565 #define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800 17566 #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb 17567 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff 17568 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 17569 #define IA_ENHANCE__MISC_MASK 0xffffffff 17570 #define IA_ENHANCE__MISC__SHIFT 0x0 17571 #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff 17572 #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 17573 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff 17574 #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 17575 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f 17576 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 17577 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff 17578 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 17579 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 17580 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 17581 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 17582 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 17583 #define VGT_IMMED_DATA__DATA_MASK 0xffffffff 17584 #define VGT_IMMED_DATA__DATA__SHIFT 0x0 17585 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 17586 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 17587 #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff 17588 #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 17589 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff 17590 #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 17591 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f 17592 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 17593 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 17594 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 17595 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 17596 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 17597 #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff 17598 #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 17599 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 17600 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 17601 #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 17602 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 17603 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff 17604 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 17605 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff 17606 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 17607 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff 17608 #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 17609 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff 17610 #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 17611 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff 17612 #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 17613 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff 17614 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 17615 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f 17616 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 17617 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff 17618 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 17619 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 17620 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 17621 #define VGT_ENHANCE__MISC_MASK 0xffffffff 17622 #define VGT_ENHANCE__MISC__SHIFT 0x0 17623 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 17624 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 17625 #define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 17626 #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 17627 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff 17628 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 17629 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff 17630 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 17631 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff 17632 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 17633 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f 17634 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 17635 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 17636 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe 17637 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 17638 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf 17639 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 17640 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 17641 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf 17642 #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 17643 #define VGT_GROUP_DECR__DECR_MASK 0xf 17644 #define VGT_GROUP_DECR__DECR__SHIFT 0x0 17645 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 17646 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 17647 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 17648 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 17649 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 17650 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 17651 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 17652 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 17653 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 17654 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 17655 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 17656 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 17657 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 17658 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 17659 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 17660 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 17661 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 17662 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 17663 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 17664 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 17665 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 17666 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 17667 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 17668 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 17669 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf 17670 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 17671 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 17672 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 17673 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 17674 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 17675 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 17676 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc 17677 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 17678 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 17679 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 17680 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 17681 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 17682 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 17683 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 17684 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c 17685 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf 17686 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 17687 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 17688 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 17689 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 17690 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 17691 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 17692 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc 17693 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 17694 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 17695 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 17696 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 17697 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 17698 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 17699 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 17700 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c 17701 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff 17702 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 17703 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff 17704 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 17705 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f 17706 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 17707 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f 17708 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 17709 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 17710 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 17711 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 17712 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 17713 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 17714 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 17715 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 17716 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 17717 #define VGT_GS_MODE__MODE_MASK 0x7 17718 #define VGT_GS_MODE__MODE__SHIFT 0x0 17719 #define VGT_GS_MODE__RESERVED_0_MASK 0x8 17720 #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 17721 #define VGT_GS_MODE__CUT_MODE_MASK 0x30 17722 #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 17723 #define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 17724 #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 17725 #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 17726 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb 17727 #define VGT_GS_MODE__RESERVED_2_MASK 0x1000 17728 #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc 17729 #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 17730 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd 17731 #define VGT_GS_MODE__RESERVED_3_MASK 0x4000 17732 #define VGT_GS_MODE__RESERVED_3__SHIFT 0xe 17733 #define VGT_GS_MODE__RESERVED_4_MASK 0x8000 17734 #define VGT_GS_MODE__RESERVED_4__SHIFT 0xf 17735 #define VGT_GS_MODE__RESERVED_5_MASK 0x10000 17736 #define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 17737 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 17738 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 17739 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 17740 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 17741 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 17742 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 17743 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 17744 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 17745 #define VGT_GS_MODE__ONCHIP_MASK 0x600000 17746 #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 17747 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff 17748 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 17749 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 17750 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb 17751 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f 17752 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 17753 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 17754 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 17755 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 17756 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 17757 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 17758 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 17759 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 17760 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f 17761 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 17762 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 17763 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10 17764 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 17765 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 17766 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 17767 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 17768 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 17769 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 17770 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 17771 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 17772 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb 17773 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 17774 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc 17775 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 17776 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd 17777 #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 17778 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 17779 #define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 17780 #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 17781 #define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 17782 #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 17783 #define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 17784 #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 17785 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff 17786 #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 17787 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 17788 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 17789 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 17790 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb 17791 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 17792 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe 17793 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 17794 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 17795 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f 17796 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 17797 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 17798 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 17799 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 17800 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 17801 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000 17802 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 17803 #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff 17804 #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 17805 #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff 17806 #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 17807 #define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf 17808 #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 17809 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f 17810 #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 17811 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 17812 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 17813 #define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 17814 #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 17815 #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 17816 #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 17817 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 17818 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 17819 #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 17820 #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 17821 #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 17822 #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 17823 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 17824 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 17825 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 17826 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 17827 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 17828 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 17829 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 17830 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 17831 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 17832 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 17833 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 17834 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 17835 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 17836 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f 17837 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff 17838 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 17839 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff 17840 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 17841 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff 17842 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 17843 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff 17844 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 17845 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff 17846 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 17847 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff 17848 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 17849 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff 17850 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 17851 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff 17852 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 17853 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff 17854 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 17855 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff 17856 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 17857 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff 17858 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 17859 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff 17860 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 17861 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf 17862 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 17863 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 17864 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 17865 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 17866 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 17867 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 17868 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc 17869 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff 17870 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 17871 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff 17872 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 17873 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff 17874 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 17875 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff 17876 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 17877 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff 17878 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 17879 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff 17880 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 17881 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff 17882 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 17883 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff 17884 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 17885 #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 17886 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 17887 #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 17888 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 17889 #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 17890 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 17891 #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 17892 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 17893 #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 17894 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 17895 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 17896 #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 17897 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200 17898 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 17899 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400 17900 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa 17901 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800 17902 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb 17903 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000 17904 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc 17905 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff 17906 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 17907 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff 17908 #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 17909 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 17910 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 17911 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 17912 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe 17913 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 17914 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 17915 #define VGT_TF_PARAM__TYPE_MASK 0x3 17916 #define VGT_TF_PARAM__TYPE__SHIFT 0x0 17917 #define VGT_TF_PARAM__PARTITIONING_MASK 0x1c 17918 #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 17919 #define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 17920 #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 17921 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 17922 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 17923 #define VGT_TF_PARAM__DEPRECATED_MASK 0x200 17924 #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 17925 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 17926 #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa 17927 #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 17928 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe 17929 #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000 17930 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf 17931 #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000 17932 #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 17933 #define VGT_TF_PARAM__MTYPE_MASK 0x180000 17934 #define VGT_TF_PARAM__MTYPE__SHIFT 0x13 17935 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff 17936 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 17937 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00 17938 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 17939 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 17940 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 17941 #define VGT_TF_RING_SIZE__SIZE_MASK 0xffff 17942 #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 17943 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 17944 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 17945 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e 17946 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 17947 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 17948 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 17949 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff 17950 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 17951 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 17952 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 17953 #define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff 17954 #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 17955 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 17956 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 17957 #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc 17958 #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 17959 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff 17960 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 17961 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 17962 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 17963 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 17964 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 17965 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 17966 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 17967 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 17968 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 17969 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 17970 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 17971 #define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000 17972 #define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c 17973 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff 17974 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 17975 #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff 17976 #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 17977 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff 17978 #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 17979 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff 17980 #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 17981 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff 17982 #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 17983 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff 17984 #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 17985 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff 17986 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 17987 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff 17988 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 17989 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff 17990 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 17991 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff 17992 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 17993 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff 17994 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 17995 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff 17996 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 17997 #define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 17998 #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 17999 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 18000 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 18001 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 18002 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 18003 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 18004 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 18005 #define WD_ENHANCE__MISC_MASK 0xffffffff 18006 #define WD_ENHANCE__MISC__SHIFT 0x0 18007 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff 18008 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 18009 #define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 18010 #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd 18011 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 18012 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 18013 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1 18014 #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 18015 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf 18016 #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 18017 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 18018 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 18019 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 18020 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 18021 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 18022 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 18023 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 18024 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 18025 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 18026 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 18027 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 18028 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 18029 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 18030 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 18031 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 18032 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 18033 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 18034 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 18035 #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf 18036 #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 18037 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 18038 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 18039 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 18040 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 18041 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 18042 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 18043 #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 18044 #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 18045 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 18046 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 18047 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 18048 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 18049 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 18050 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 18051 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 18052 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 18053 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 18054 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 18055 #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf 18056 #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 18057 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 18058 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 18059 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 18060 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 18061 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 18062 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 18063 #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 18064 #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a 18065 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 18066 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 18067 #define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000 18068 #define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c 18069 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 18070 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 18071 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 18072 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e 18073 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 18074 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 18075 #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f 18076 #define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 18077 #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 18078 #define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 18079 #define VGT_DEBUG_DATA__DATA_MASK 0xffffffff 18080 #define VGT_DEBUG_DATA__DATA__SHIFT 0x0 18081 #define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f 18082 #define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 18083 #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 18084 #define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 18085 #define IA_DEBUG_DATA__DATA_MASK 0xffffffff 18086 #define IA_DEBUG_DATA__DATA__SHIFT 0x0 18087 #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 18088 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 18089 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 18090 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 18091 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 18092 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 18093 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 18094 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 18095 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 18096 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 18097 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 18098 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 18099 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 18100 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 18101 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 18102 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 18103 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 18104 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 18105 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 18106 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 18107 #define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f 18108 #define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 18109 #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 18110 #define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 18111 #define WD_DEBUG_DATA__DATA_MASK 0xffffffff 18112 #define WD_DEBUG_DATA__DATA__SHIFT 0x0 18113 #define WD_QOS__DRAW_STALL_MASK 0x1 18114 #define WD_QOS__DRAW_STALL__SHIFT 0x0 18115 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 18116 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 18117 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 18118 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 18119 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 18120 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 18121 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 18122 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 18123 #define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 18124 #define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 18125 #define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 18126 #define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 18127 #define WD_DEBUG_REG0__wd_busy_MASK 0x4 18128 #define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 18129 #define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 18130 #define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 18131 #define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 18132 #define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 18133 #define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 18134 #define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 18135 #define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 18136 #define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 18137 #define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 18138 #define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 18139 #define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 18140 #define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 18141 #define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 18142 #define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 18143 #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 18144 #define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa 18145 #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 18146 #define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb 18147 #define WD_DEBUG_REG0__SPARE2_MASK 0x1000 18148 #define WD_DEBUG_REG0__SPARE2__SHIFT 0xc 18149 #define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 18150 #define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd 18151 #define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 18152 #define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe 18153 #define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 18154 #define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf 18155 #define WD_DEBUG_REG0__SPARE3_MASK 0x10000 18156 #define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 18157 #define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 18158 #define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 18159 #define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 18160 #define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 18161 #define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 18162 #define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 18163 #define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 18164 #define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 18165 #define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 18166 #define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 18167 #define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 18168 #define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 18169 #define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 18170 #define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 18171 #define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 18172 #define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 18173 #define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 18174 #define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 18175 #define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 18176 #define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a 18177 #define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 18178 #define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b 18179 #define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 18180 #define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c 18181 #define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 18182 #define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d 18183 #define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 18184 #define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e 18185 #define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 18186 #define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f 18187 #define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 18188 #define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 18189 #define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 18190 #define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 18191 #define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 18192 #define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 18193 #define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 18194 #define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 18195 #define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 18196 #define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 18197 #define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 18198 #define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 18199 #define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 18200 #define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 18201 #define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 18202 #define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 18203 #define WD_DEBUG_REG1__SPARE0_MASK 0x100 18204 #define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 18205 #define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 18206 #define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 18207 #define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 18208 #define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa 18209 #define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 18210 #define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb 18211 #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 18212 #define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc 18213 #define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 18214 #define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 18215 #define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 18216 #define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 18217 #define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 18218 #define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a 18219 #define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 18220 #define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b 18221 #define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 18222 #define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c 18223 #define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 18224 #define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d 18225 #define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 18226 #define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e 18227 #define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 18228 #define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f 18229 #define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 18230 #define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 18231 #define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 18232 #define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 18233 #define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 18234 #define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 18235 #define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 18236 #define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 18237 #define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 18238 #define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 18239 #define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 18240 #define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 18241 #define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 18242 #define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 18243 #define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 18244 #define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 18245 #define WD_DEBUG_REG2__SPARE0_MASK 0x100 18246 #define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 18247 #define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 18248 #define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 18249 #define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 18250 #define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa 18251 #define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 18252 #define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb 18253 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 18254 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc 18255 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 18256 #define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 18257 #define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 18258 #define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 18259 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 18260 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a 18261 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 18262 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b 18263 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 18264 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c 18265 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 18266 #define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d 18267 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 18268 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e 18269 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 18270 #define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f 18271 #define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 18272 #define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 18273 #define WD_DEBUG_REG3__SPARE0_MASK 0x2 18274 #define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 18275 #define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 18276 #define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 18277 #define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 18278 #define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 18279 #define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 18280 #define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 18281 #define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 18282 #define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 18283 #define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 18284 #define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 18285 #define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 18286 #define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 18287 #define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 18288 #define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 18289 #define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 18290 #define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa 18291 #define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 18292 #define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb 18293 #define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 18294 #define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc 18295 #define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 18296 #define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd 18297 #define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 18298 #define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe 18299 #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 18300 #define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf 18301 #define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 18302 #define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 18303 #define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 18304 #define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 18305 #define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 18306 #define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 18307 #define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 18308 #define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 18309 #define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 18310 #define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 18311 #define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 18312 #define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 18313 #define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 18314 #define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 18315 #define WD_DEBUG_REG3__SPARE1_MASK 0x800000 18316 #define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 18317 #define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 18318 #define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 18319 #define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 18320 #define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 18321 #define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 18322 #define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a 18323 #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 18324 #define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b 18325 #define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 18326 #define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c 18327 #define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 18328 #define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d 18329 #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 18330 #define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e 18331 #define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 18332 #define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f 18333 #define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 18334 #define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 18335 #define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 18336 #define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 18337 #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 18338 #define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 18339 #define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 18340 #define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 18341 #define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 18342 #define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 18343 #define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 18344 #define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 18345 #define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 18346 #define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 18347 #define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 18348 #define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 18349 #define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 18350 #define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 18351 #define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 18352 #define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 18353 #define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 18354 #define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa 18355 #define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 18356 #define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb 18357 #define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 18358 #define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc 18359 #define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 18360 #define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd 18361 #define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 18362 #define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe 18363 #define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 18364 #define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 18365 #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 18366 #define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 18367 #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 18368 #define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 18369 #define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 18370 #define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 18371 #define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 18372 #define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 18373 #define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 18374 #define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 18375 #define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 18376 #define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 18377 #define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 18378 #define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 18379 #define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 18380 #define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a 18381 #define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 18382 #define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b 18383 #define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 18384 #define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c 18385 #define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 18386 #define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d 18387 #define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 18388 #define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e 18389 #define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 18390 #define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f 18391 #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 18392 #define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 18393 #define WD_DEBUG_REG5__SPARE0_MASK 0x2 18394 #define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 18395 #define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 18396 #define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 18397 #define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 18398 #define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 18399 #define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 18400 #define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 18401 #define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 18402 #define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 18403 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 18404 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 18405 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 18406 #define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 18407 #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 18408 #define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 18409 #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 18410 #define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa 18411 #define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 18412 #define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb 18413 #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 18414 #define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc 18415 #define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 18416 #define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd 18417 #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 18418 #define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe 18419 #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 18420 #define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf 18421 #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 18422 #define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 18423 #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 18424 #define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 18425 #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 18426 #define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 18427 #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 18428 #define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 18429 #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 18430 #define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 18431 #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 18432 #define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 18433 #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 18434 #define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 18435 #define WD_DEBUG_REG5__SPARE1_MASK 0x800000 18436 #define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 18437 #define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 18438 #define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 18439 #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 18440 #define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 18441 #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 18442 #define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a 18443 #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 18444 #define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b 18445 #define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 18446 #define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c 18447 #define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 18448 #define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d 18449 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 18450 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e 18451 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 18452 #define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f 18453 #define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff 18454 #define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0 18455 #define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1 18456 #define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0 18457 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2 18458 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1 18459 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4 18460 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2 18461 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8 18462 #define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3 18463 #define WD_DEBUG_REG7__SPARE0_MASK 0xf0 18464 #define WD_DEBUG_REG7__SPARE0__SHIFT 0x4 18465 #define WD_DEBUG_REG7__SPARE1_MASK 0xf00 18466 #define WD_DEBUG_REG7__SPARE1__SHIFT 0x8 18467 #define WD_DEBUG_REG7__SPARE2_MASK 0xf000 18468 #define WD_DEBUG_REG7__SPARE2__SHIFT 0xc 18469 #define WD_DEBUG_REG7__SPARE3_MASK 0xf0000 18470 #define WD_DEBUG_REG7__SPARE3__SHIFT 0x10 18471 #define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000 18472 #define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14 18473 #define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000 18474 #define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15 18475 #define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000 18476 #define WD_DEBUG_REG7__SPARE4__SHIFT 0x16 18477 #define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000 18478 #define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c 18479 #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000 18480 #define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d 18481 #define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000 18482 #define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e 18483 #define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000 18484 #define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f 18485 #define WD_DEBUG_REG8__pipe0_dr_MASK 0x1 18486 #define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0 18487 #define WD_DEBUG_REG8__pipe1_dr_MASK 0x2 18488 #define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1 18489 #define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4 18490 #define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2 18491 #define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8 18492 #define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3 18493 #define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10 18494 #define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4 18495 #define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20 18496 #define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5 18497 #define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40 18498 #define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6 18499 #define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80 18500 #define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7 18501 #define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100 18502 #define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8 18503 #define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200 18504 #define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9 18505 #define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400 18506 #define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa 18507 #define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800 18508 #define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb 18509 #define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000 18510 #define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc 18511 #define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000 18512 #define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12 18513 #define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000 18514 #define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13 18515 #define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000 18516 #define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14 18517 #define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000 18518 #define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b 18519 #define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000 18520 #define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c 18521 #define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000 18522 #define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d 18523 #define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000 18524 #define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e 18525 #define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000 18526 #define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f 18527 #define WD_DEBUG_REG9__pipe0_dr_MASK 0x1 18528 #define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0 18529 #define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2 18530 #define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1 18531 #define WD_DEBUG_REG9__pipe2_dr_MASK 0x4 18532 #define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2 18533 #define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8 18534 #define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3 18535 #define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10 18536 #define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4 18537 #define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20 18538 #define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5 18539 #define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40 18540 #define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6 18541 #define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80 18542 #define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7 18543 #define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100 18544 #define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8 18545 #define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200 18546 #define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9 18547 #define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400 18548 #define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa 18549 #define WD_DEBUG_REG9__SPARE0_MASK 0xf800 18550 #define WD_DEBUG_REG9__SPARE0__SHIFT 0xb 18551 #define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000 18552 #define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10 18553 #define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000 18554 #define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13 18555 #define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000 18556 #define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14 18557 #define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000 18558 #define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18 18559 #define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000 18560 #define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19 18561 #define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000 18562 #define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a 18563 #define WD_DEBUG_REG9__SPARE1_MASK 0x8000000 18564 #define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b 18565 #define WD_DEBUG_REG9__SPARE2_MASK 0x30000000 18566 #define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c 18567 #define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000 18568 #define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e 18569 #define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000 18570 #define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f 18571 #define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1 18572 #define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0 18573 #define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2 18574 #define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1 18575 #define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4 18576 #define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2 18577 #define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8 18578 #define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3 18579 #define WD_DEBUG_REG10__pipe0_dr_MASK 0x10 18580 #define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4 18581 #define WD_DEBUG_REG10__pipe1_dr_MASK 0x20 18582 #define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5 18583 #define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40 18584 #define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6 18585 #define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80 18586 #define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7 18587 #define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100 18588 #define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8 18589 #define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200 18590 #define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9 18591 #define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400 18592 #define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa 18593 #define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800 18594 #define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb 18595 #define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000 18596 #define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc 18597 #define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000 18598 #define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd 18599 #define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000 18600 #define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe 18601 #define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000 18602 #define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf 18603 #define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000 18604 #define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10 18605 #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000 18606 #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18 18607 #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000 18608 #define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19 18609 #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000 18610 #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a 18611 #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000 18612 #define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b 18613 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000 18614 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c 18615 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000 18616 #define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d 18617 #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000 18618 #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e 18619 #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000 18620 #define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f 18621 #define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 18622 #define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 18623 #define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 18624 #define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 18625 #define IA_DEBUG_REG0__ia_busy_MASK 0x4 18626 #define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 18627 #define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 18628 #define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 18629 #define IA_DEBUG_REG0__SPARE0_MASK 0x10 18630 #define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 18631 #define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 18632 #define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 18633 #define IA_DEBUG_REG0__dma_busy_MASK 0x40 18634 #define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 18635 #define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 18636 #define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 18637 #define IA_DEBUG_REG0__grp_busy_MASK 0x100 18638 #define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 18639 #define IA_DEBUG_REG0__SPARE1_MASK 0x200 18640 #define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 18641 #define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 18642 #define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa 18643 #define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 18644 #define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb 18645 #define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 18646 #define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc 18647 #define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 18648 #define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd 18649 #define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 18650 #define IA_DEBUG_REG0__SPARE2__SHIFT 0xe 18651 #define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 18652 #define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 18653 #define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 18654 #define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 18655 #define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 18656 #define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a 18657 #define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 18658 #define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b 18659 #define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 18660 #define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c 18661 #define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 18662 #define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 18663 #define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 18664 #define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e 18665 #define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 18666 #define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f 18667 #define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 18668 #define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 18669 #define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 18670 #define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 18671 #define IA_DEBUG_REG1__start_new_packet_MASK 0x4 18672 #define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 18673 #define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 18674 #define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 18675 #define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 18676 #define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 18677 #define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 18678 #define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 18679 #define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 18680 #define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 18681 #define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 18682 #define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 18683 #define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 18684 #define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 18685 #define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 18686 #define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa 18687 #define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 18688 #define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb 18689 #define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 18690 #define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc 18691 #define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 18692 #define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd 18693 #define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 18694 #define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe 18695 #define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 18696 #define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf 18697 #define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 18698 #define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 18699 #define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 18700 #define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 18701 #define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 18702 #define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 18703 #define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 18704 #define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 18705 #define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 18706 #define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 18707 #define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 18708 #define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 18709 #define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 18710 #define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 18711 #define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 18712 #define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 18713 #define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 18714 #define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 18715 #define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 18716 #define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 18717 #define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 18718 #define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a 18719 #define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 18720 #define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b 18721 #define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 18722 #define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c 18723 #define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 18724 #define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d 18725 #define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 18726 #define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e 18727 #define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 18728 #define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f 18729 #define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 18730 #define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 18731 #define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 18732 #define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 18733 #define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 18734 #define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 18735 #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 18736 #define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 18737 #define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 18738 #define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 18739 #define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 18740 #define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 18741 #define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 18742 #define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 18743 #define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 18744 #define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 18745 #define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 18746 #define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 18747 #define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 18748 #define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa 18749 #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 18750 #define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb 18751 #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 18752 #define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc 18753 #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 18754 #define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd 18755 #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 18756 #define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe 18757 #define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 18758 #define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf 18759 #define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 18760 #define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 18761 #define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 18762 #define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 18763 #define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 18764 #define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 18765 #define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 18766 #define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 18767 #define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 18768 #define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 18769 #define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 18770 #define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 18771 #define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 18772 #define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 18773 #define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 18774 #define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 18775 #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 18776 #define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 18777 #define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 18778 #define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 18779 #define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 18780 #define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a 18781 #define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 18782 #define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b 18783 #define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 18784 #define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c 18785 #define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 18786 #define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d 18787 #define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 18788 #define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e 18789 #define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 18790 #define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f 18791 #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 18792 #define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 18793 #define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 18794 #define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 18795 #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 18796 #define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 18797 #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 18798 #define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 18799 #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 18800 #define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 18801 #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 18802 #define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 18803 #define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 18804 #define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 18805 #define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 18806 #define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 18807 #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 18808 #define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 18809 #define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 18810 #define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 18811 #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 18812 #define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa 18813 #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 18814 #define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb 18815 #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 18816 #define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc 18817 #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 18818 #define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd 18819 #define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 18820 #define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe 18821 #define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 18822 #define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf 18823 #define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 18824 #define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 18825 #define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 18826 #define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 18827 #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 18828 #define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 18829 #define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 18830 #define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 18831 #define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 18832 #define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 18833 #define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 18834 #define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 18835 #define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 18836 #define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 18837 #define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 18838 #define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 18839 #define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 18840 #define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 18841 #define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 18842 #define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a 18843 #define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 18844 #define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b 18845 #define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 18846 #define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c 18847 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 18848 #define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d 18849 #define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 18850 #define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e 18851 #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 18852 #define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f 18853 #define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 18854 #define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 18855 #define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 18856 #define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 18857 #define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 18858 #define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 18859 #define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 18860 #define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 18861 #define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 18862 #define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 18863 #define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 18864 #define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 18865 #define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 18866 #define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 18867 #define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 18868 #define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 18869 #define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 18870 #define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 18871 #define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 18872 #define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 18873 #define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 18874 #define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa 18875 #define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 18876 #define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb 18877 #define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 18878 #define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc 18879 #define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 18880 #define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd 18881 #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 18882 #define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe 18883 #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 18884 #define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf 18885 #define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 18886 #define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 18887 #define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 18888 #define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 18889 #define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 18890 #define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 18891 #define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 18892 #define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 18893 #define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 18894 #define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 18895 #define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 18896 #define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 18897 #define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 18898 #define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a 18899 #define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 18900 #define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c 18901 #define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 18902 #define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d 18903 #define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 18904 #define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e 18905 #define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 18906 #define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f 18907 #define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff 18908 #define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 18909 #define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 18910 #define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 18911 #define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 18912 #define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e 18913 #define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 18914 #define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f 18915 #define IA_DEBUG_REG6__current_shift_q_MASK 0xf 18916 #define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 18917 #define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 18918 #define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 18919 #define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 18920 #define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 18921 #define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 18922 #define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd 18923 #define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 18924 #define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe 18925 #define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 18926 #define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf 18927 #define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 18928 #define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 18929 #define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 18930 #define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 18931 #define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 18932 #define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 18933 #define IA_DEBUG_REG6__extract_group_MASK 0x800000 18934 #define IA_DEBUG_REG6__extract_group__SHIFT 0x17 18935 #define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 18936 #define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 18937 #define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf 18938 #define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 18939 #define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 18940 #define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 18941 #define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 18942 #define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 18943 #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 18944 #define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc 18945 #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 18946 #define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 18947 #define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 18948 #define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 18949 #define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 18950 #define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 18951 #define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 18952 #define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 18953 #define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 18954 #define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 18955 #define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 18956 #define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a 18957 #define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 18958 #define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b 18959 #define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 18960 #define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c 18961 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 18962 #define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d 18963 #define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 18964 #define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e 18965 #define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 18966 #define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f 18967 #define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f 18968 #define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 18969 #define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 18970 #define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 18971 #define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 18972 #define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 18973 #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 18974 #define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 18975 #define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 18976 #define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 18977 #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 18978 #define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 18979 #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 18980 #define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa 18981 #define IA_DEBUG_REG8__grp_continued_MASK 0x800 18982 #define IA_DEBUG_REG8__grp_continued__SHIFT 0xb 18983 #define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 18984 #define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc 18985 #define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 18986 #define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf 18987 #define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 18988 #define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 18989 #define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 18990 #define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 18991 #define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 18992 #define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 18993 #define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 18994 #define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a 18995 #define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 18996 #define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b 18997 #define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 18998 #define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c 18999 #define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 19000 #define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 19001 #define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 19002 #define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 19003 #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 19004 #define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 19005 #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 19006 #define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 19007 #define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 19008 #define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 19009 #define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 19010 #define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 19011 #define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 19012 #define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 19013 #define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 19014 #define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 19015 #define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 19016 #define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 19017 #define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 19018 #define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 19019 #define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 19020 #define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa 19021 #define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 19022 #define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb 19023 #define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 19024 #define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc 19025 #define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 19026 #define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd 19027 #define IA_DEBUG_REG9__SPARE0_MASK 0x4000 19028 #define IA_DEBUG_REG9__SPARE0__SHIFT 0xe 19029 #define IA_DEBUG_REG9__SPARE1_MASK 0x8000 19030 #define IA_DEBUG_REG9__SPARE1__SHIFT 0xf 19031 #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 19032 #define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 19033 #define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 19034 #define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 19035 #define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 19036 #define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 19037 #define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 19038 #define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 19039 #define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 19040 #define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 19041 #define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 19042 #define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 19043 #define VGT_DEBUG_REG0__SPARE9_MASK 0x2 19044 #define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 19045 #define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 19046 #define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 19047 #define VGT_DEBUG_REG0__SPARE8_MASK 0x8 19048 #define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 19049 #define VGT_DEBUG_REG0__SPARE7_MASK 0x10 19050 #define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 19051 #define VGT_DEBUG_REG0__SPARE6_MASK 0x20 19052 #define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 19053 #define VGT_DEBUG_REG0__SPARE5_MASK 0x40 19054 #define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 19055 #define VGT_DEBUG_REG0__SPARE4_MASK 0x80 19056 #define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 19057 #define VGT_DEBUG_REG0__pi_busy_MASK 0x100 19058 #define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 19059 #define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 19060 #define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 19061 #define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 19062 #define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa 19063 #define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 19064 #define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb 19065 #define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 19066 #define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc 19067 #define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 19068 #define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd 19069 #define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 19070 #define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe 19071 #define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 19072 #define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf 19073 #define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 19074 #define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 19075 #define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 19076 #define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 19077 #define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 19078 #define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 19079 #define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 19080 #define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 19081 #define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 19082 #define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 19083 #define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 19084 #define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 19085 #define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 19086 #define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 19087 #define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 19088 #define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 19089 #define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 19090 #define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 19091 #define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 19092 #define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 19093 #define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 19094 #define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a 19095 #define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 19096 #define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b 19097 #define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 19098 #define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c 19099 #define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 19100 #define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d 19101 #define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 19102 #define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e 19103 #define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 19104 #define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f 19105 #define VGT_DEBUG_REG1__SPARE9_MASK 0x1 19106 #define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 19107 #define VGT_DEBUG_REG1__SPARE8_MASK 0x2 19108 #define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 19109 #define VGT_DEBUG_REG1__SPARE7_MASK 0x4 19110 #define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 19111 #define VGT_DEBUG_REG1__SPARE6_MASK 0x8 19112 #define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 19113 #define VGT_DEBUG_REG1__SPARE5_MASK 0x10 19114 #define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 19115 #define VGT_DEBUG_REG1__SPARE4_MASK 0x20 19116 #define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 19117 #define VGT_DEBUG_REG1__SPARE3_MASK 0x40 19118 #define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 19119 #define VGT_DEBUG_REG1__SPARE2_MASK 0x80 19120 #define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 19121 #define VGT_DEBUG_REG1__SPARE1_MASK 0x100 19122 #define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 19123 #define VGT_DEBUG_REG1__SPARE0_MASK 0x200 19124 #define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 19125 #define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 19126 #define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa 19127 #define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 19128 #define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb 19129 #define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 19130 #define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc 19131 #define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 19132 #define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd 19133 #define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 19134 #define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe 19135 #define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 19136 #define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf 19137 #define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 19138 #define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 19139 #define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 19140 #define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 19141 #define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 19142 #define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 19143 #define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 19144 #define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 19145 #define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 19146 #define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 19147 #define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 19148 #define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 19149 #define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 19150 #define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 19151 #define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 19152 #define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 19153 #define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 19154 #define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 19155 #define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 19156 #define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 19157 #define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 19158 #define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a 19159 #define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 19160 #define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b 19161 #define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 19162 #define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c 19163 #define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 19164 #define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d 19165 #define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 19166 #define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e 19167 #define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 19168 #define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f 19169 #define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 19170 #define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 19171 #define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 19172 #define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 19173 #define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 19174 #define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 19175 #define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 19176 #define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 19177 #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 19178 #define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 19179 #define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 19180 #define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 19181 #define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 19182 #define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 19183 #define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 19184 #define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 19185 #define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 19186 #define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 19187 #define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 19188 #define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 19189 #define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 19190 #define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa 19191 #define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 19192 #define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb 19193 #define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 19194 #define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc 19195 #define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 19196 #define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd 19197 #define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 19198 #define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe 19199 #define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 19200 #define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf 19201 #define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 19202 #define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 19203 #define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 19204 #define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 19205 #define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 19206 #define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 19207 #define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 19208 #define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 19209 #define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 19210 #define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 19211 #define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 19212 #define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 19213 #define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 19214 #define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 19215 #define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 19216 #define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 19217 #define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 19218 #define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 19219 #define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 19220 #define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 19221 #define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 19222 #define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a 19223 #define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 19224 #define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b 19225 #define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 19226 #define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c 19227 #define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 19228 #define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d 19229 #define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff 19230 #define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 19231 #define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 19232 #define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc 19233 #define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 19234 #define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 19235 #define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 19236 #define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a 19237 #define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff 19238 #define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 19239 #define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 19240 #define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 19241 #define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 19242 #define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 19243 #define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 19244 #define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d 19245 #define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 19246 #define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e 19247 #define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 19248 #define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f 19249 #define VGT_DEBUG_REG5__SPARE4_MASK 0x7 19250 #define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 19251 #define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 19252 #define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 19253 #define VGT_DEBUG_REG5__SPARE3_MASK 0x700 19254 #define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 19255 #define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 19256 #define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb 19257 #define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 19258 #define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 19259 #define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 19260 #define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 19261 #define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 19262 #define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 19263 #define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 19264 #define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b 19265 #define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff 19266 #define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 19267 #define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 19268 #define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 19269 #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 19270 #define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 19271 #define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 19272 #define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 19273 #define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 19274 #define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 19275 #define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 19276 #define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 19277 #define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 19278 #define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 19279 #define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 19280 #define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 19281 #define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 19282 #define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 19283 #define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 19284 #define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 19285 #define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 19286 #define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 19287 #define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 19288 #define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 19289 #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 19290 #define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 19291 #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 19292 #define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 19293 #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 19294 #define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 19295 #define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 19296 #define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 19297 #define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 19298 #define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 19299 #define VGT_DEBUG_REG8__valid_r2_MASK 0x100 19300 #define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 19301 #define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 19302 #define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 19303 #define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 19304 #define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa 19305 #define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 19306 #define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb 19307 #define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 19308 #define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc 19309 #define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 19310 #define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd 19311 #define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 19312 #define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe 19313 #define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 19314 #define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf 19315 #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 19316 #define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 19317 #define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 19318 #define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 19319 #define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 19320 #define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 19321 #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 19322 #define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 19323 #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 19324 #define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 19325 #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 19326 #define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 19327 #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 19328 #define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 19329 #define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 19330 #define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 19331 #define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 19332 #define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 19333 #define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 19334 #define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 19335 #define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 19336 #define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a 19337 #define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 19338 #define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b 19339 #define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 19340 #define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c 19341 #define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 19342 #define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d 19343 #define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 19344 #define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e 19345 #define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 19346 #define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f 19347 #define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 19348 #define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 19349 #define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 19350 #define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 19351 #define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 19352 #define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 19353 #define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 19354 #define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 19355 #define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 19356 #define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 19357 #define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 19358 #define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 19359 #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 19360 #define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 19361 #define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 19362 #define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 19363 #define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 19364 #define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 19365 #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 19366 #define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa 19367 #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 19368 #define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb 19369 #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 19370 #define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 19371 #define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 19372 #define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 19373 #define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 19374 #define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 19375 #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 19376 #define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 19377 #define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 19378 #define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 19379 #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 19380 #define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 19381 #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 19382 #define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a 19383 #define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 19384 #define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b 19385 #define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 19386 #define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c 19387 #define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 19388 #define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d 19389 #define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 19390 #define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e 19391 #define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 19392 #define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f 19393 #define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f 19394 #define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 19395 #define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 19396 #define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 19397 #define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 19398 #define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 19399 #define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 19400 #define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 19401 #define VGT_DEBUG_REG10__SPARE2_MASK 0x600 19402 #define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 19403 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 19404 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb 19405 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 19406 #define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc 19407 #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 19408 #define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd 19409 #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 19410 #define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 19411 #define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 19412 #define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 19413 #define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 19414 #define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 19415 #define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 19416 #define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 19417 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 19418 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 19419 #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 19420 #define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 19421 #define VGT_DEBUG_REG11__SPARE1_MASK 0x20 19422 #define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 19423 #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 19424 #define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 19425 #define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 19426 #define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 19427 #define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 19428 #define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 19429 #define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 19430 #define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 19431 #define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 19432 #define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa 19433 #define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 19434 #define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb 19435 #define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 19436 #define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc 19437 #define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 19438 #define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd 19439 #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 19440 #define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe 19441 #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 19442 #define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf 19443 #define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 19444 #define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 19445 #define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 19446 #define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 19447 #define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 19448 #define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 19449 #define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 19450 #define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 19451 #define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 19452 #define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 19453 #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 19454 #define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 19455 #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 19456 #define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 19457 #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 19458 #define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 19459 #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 19460 #define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 19461 #define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 19462 #define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 19463 #define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 19464 #define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a 19465 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 19466 #define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b 19467 #define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 19468 #define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c 19469 #define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 19470 #define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d 19471 #define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 19472 #define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e 19473 #define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 19474 #define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f 19475 #define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 19476 #define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 19477 #define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 19478 #define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 19479 #define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 19480 #define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 19481 #define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 19482 #define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 19483 #define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 19484 #define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc 19485 #define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 19486 #define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf 19487 #define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 19488 #define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 19489 #define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 19490 #define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 19491 #define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 19492 #define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 19493 #define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 19494 #define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b 19495 #define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 19496 #define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e 19497 #define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 19498 #define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f 19499 #define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 19500 #define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 19501 #define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 19502 #define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 19503 #define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 19504 #define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 19505 #define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 19506 #define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 19507 #define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 19508 #define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc 19509 #define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 19510 #define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf 19511 #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 19512 #define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 19513 #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 19514 #define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 19515 #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 19516 #define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 19517 #define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 19518 #define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 19519 #define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 19520 #define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 19521 #define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 19522 #define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a 19523 #define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 19524 #define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b 19525 #define VGT_DEBUG_REG14__SPARE3_MASK 0xf 19526 #define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 19527 #define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 19528 #define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 19529 #define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 19530 #define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 19531 #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 19532 #define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 19533 #define VGT_DEBUG_REG14__SPARE8_MASK 0x180 19534 #define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 19535 #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 19536 #define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 19537 #define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 19538 #define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa 19539 #define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 19540 #define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb 19541 #define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 19542 #define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc 19543 #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 19544 #define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 19545 #define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 19546 #define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 19547 #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 19548 #define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 19549 #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 19550 #define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a 19551 #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 19552 #define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b 19553 #define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 19554 #define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c 19555 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 19556 #define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d 19557 #define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 19558 #define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e 19559 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 19560 #define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f 19561 #define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 19562 #define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 19563 #define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 19564 #define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 19565 #define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 19566 #define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 19567 #define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 19568 #define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 19569 #define VGT_DEBUG_REG15__counters_full_MASK 0x10 19570 #define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 19571 #define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 19572 #define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 19573 #define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 19574 #define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa 19575 #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 19576 #define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf 19577 #define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 19578 #define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 19579 #define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 19580 #define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a 19581 #define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 19582 #define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c 19583 #define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 19584 #define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d 19585 #define VGT_DEBUG_REG16__gog_busy_MASK 0x1 19586 #define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 19587 #define VGT_DEBUG_REG16__gog_state_q_MASK 0xe 19588 #define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 19589 #define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 19590 #define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 19591 #define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 19592 #define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 19593 #define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 19594 #define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 19595 #define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 19596 #define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 19597 #define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 19598 #define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 19599 #define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 19600 #define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 19601 #define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 19602 #define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa 19603 #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 19604 #define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb 19605 #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 19606 #define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc 19607 #define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 19608 #define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd 19609 #define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 19610 #define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe 19611 #define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 19612 #define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf 19613 #define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 19614 #define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 19615 #define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 19616 #define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 19617 #define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 19618 #define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 19619 #define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 19620 #define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 19621 #define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 19622 #define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 19623 #define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 19624 #define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 19625 #define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 19626 #define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 19627 #define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 19628 #define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 19629 #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 19630 #define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 19631 #define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 19632 #define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 19633 #define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 19634 #define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c 19635 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 19636 #define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d 19637 #define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 19638 #define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e 19639 #define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 19640 #define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f 19641 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f 19642 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 19643 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 19644 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 19645 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 19646 #define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc 19647 #define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 19648 #define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 19649 #define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 19650 #define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 19651 #define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 19652 #define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 19653 #define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 19654 #define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 19655 #define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 19656 #define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 19657 #define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 19658 #define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 19659 #define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 19660 #define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 19661 #define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 19662 #define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 19663 #define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 19664 #define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 19665 #define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 19666 #define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 19667 #define VGT_DEBUG_REG18__valid_indices_MASK 0x800 19668 #define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb 19669 #define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 19670 #define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc 19671 #define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 19672 #define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd 19673 #define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 19674 #define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe 19675 #define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 19676 #define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf 19677 #define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 19678 #define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 19679 #define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 19680 #define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 19681 #define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 19682 #define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 19683 #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 19684 #define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 19685 #define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 19686 #define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 19687 #define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 19688 #define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 19689 #define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 19690 #define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 19691 #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 19692 #define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 19693 #define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 19694 #define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 19695 #define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 19696 #define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b 19697 #define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 19698 #define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c 19699 #define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 19700 #define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d 19701 #define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 19702 #define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 19703 #define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 19704 #define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 19705 #define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 19706 #define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 19707 #define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 19708 #define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 19709 #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 19710 #define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 19711 #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 19712 #define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 19713 #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 19714 #define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 19715 #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 19716 #define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 19717 #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 19718 #define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 19719 #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 19720 #define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 19721 #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 19722 #define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa 19723 #define VGT_DEBUG_REG19__hold_prim_MASK 0x800 19724 #define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb 19725 #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 19726 #define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc 19727 #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 19728 #define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd 19729 #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 19730 #define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe 19731 #define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 19732 #define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf 19733 #define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 19734 #define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 19735 #define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 19736 #define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 19737 #define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 19738 #define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 19739 #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 19740 #define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 19741 #define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 19742 #define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 19743 #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 19744 #define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a 19745 #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 19746 #define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b 19747 #define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 19748 #define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c 19749 #define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 19750 #define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e 19751 #define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 19752 #define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f 19753 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff 19754 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 19755 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 19756 #define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 19757 #define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 19758 #define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 19759 #define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 19760 #define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 19761 #define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 19762 #define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 19763 #define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 19764 #define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d 19765 #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 19766 #define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e 19767 #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 19768 #define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f 19769 #define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 19770 #define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 19771 #define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 19772 #define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 19773 #define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 19774 #define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 19775 #define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 19776 #define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 19777 #define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 19778 #define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 19779 #define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 19780 #define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 19781 #define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 19782 #define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 19783 #define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 19784 #define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 19785 #define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 19786 #define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 19787 #define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 19788 #define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 19789 #define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 19790 #define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa 19791 #define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 19792 #define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb 19793 #define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 19794 #define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc 19795 #define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 19796 #define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd 19797 #define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 19798 #define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe 19799 #define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 19800 #define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf 19801 #define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 19802 #define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 19803 #define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 19804 #define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 19805 #define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 19806 #define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 19807 #define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 19808 #define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 19809 #define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 19810 #define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 19811 #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 19812 #define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 19813 #define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 19814 #define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 19815 #define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 19816 #define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 19817 #define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 19818 #define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a 19819 #define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 19820 #define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b 19821 #define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 19822 #define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c 19823 #define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 19824 #define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d 19825 #define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 19826 #define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e 19827 #define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 19828 #define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f 19829 #define VGT_DEBUG_REG22__cm_state16_MASK 0x3 19830 #define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 19831 #define VGT_DEBUG_REG22__cm_state17_MASK 0xc 19832 #define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 19833 #define VGT_DEBUG_REG22__cm_state18_MASK 0x30 19834 #define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 19835 #define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 19836 #define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 19837 #define VGT_DEBUG_REG22__cm_state20_MASK 0x300 19838 #define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 19839 #define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 19840 #define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa 19841 #define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 19842 #define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc 19843 #define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 19844 #define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe 19845 #define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 19846 #define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 19847 #define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 19848 #define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 19849 #define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 19850 #define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 19851 #define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 19852 #define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 19853 #define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 19854 #define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 19855 #define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 19856 #define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a 19857 #define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 19858 #define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c 19859 #define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 19860 #define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e 19861 #define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 19862 #define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 19863 #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 19864 #define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 19865 #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 19866 #define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 19867 #define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 19868 #define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 19869 #define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 19870 #define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 19871 #define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 19872 #define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 19873 #define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 19874 #define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 19875 #define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 19876 #define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 19877 #define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 19878 #define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 19879 #define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 19880 #define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 19881 #define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 19882 #define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa 19883 #define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 19884 #define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb 19885 #define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 19886 #define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc 19887 #define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 19888 #define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd 19889 #define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 19890 #define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe 19891 #define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 19892 #define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf 19893 #define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 19894 #define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 19895 #define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 19896 #define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 19897 #define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 19898 #define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 19899 #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff 19900 #define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 19901 #define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 19902 #define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 19903 #define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 19904 #define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a 19905 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff 19906 #define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 19907 #define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 19908 #define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a 19909 #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 19910 #define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e 19911 #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 19912 #define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f 19913 #define VGT_DEBUG_REG26__cm_state0_MASK 0x3 19914 #define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 19915 #define VGT_DEBUG_REG26__cm_state1_MASK 0xc 19916 #define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 19917 #define VGT_DEBUG_REG26__cm_state2_MASK 0x30 19918 #define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 19919 #define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 19920 #define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 19921 #define VGT_DEBUG_REG26__cm_state4_MASK 0x300 19922 #define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 19923 #define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 19924 #define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa 19925 #define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 19926 #define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc 19927 #define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 19928 #define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe 19929 #define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 19930 #define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 19931 #define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 19932 #define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 19933 #define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 19934 #define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 19935 #define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 19936 #define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 19937 #define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 19938 #define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 19939 #define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 19940 #define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a 19941 #define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 19942 #define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c 19943 #define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 19944 #define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e 19945 #define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 19946 #define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 19947 #define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 19948 #define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 19949 #define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 19950 #define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 19951 #define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 19952 #define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 19953 #define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 19954 #define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 19955 #define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 19956 #define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 19957 #define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 19958 #define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 19959 #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 19960 #define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 19961 #define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 19962 #define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 19963 #define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 19964 #define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa 19965 #define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 19966 #define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb 19967 #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 19968 #define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc 19969 #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 19970 #define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe 19971 #define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 19972 #define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf 19973 #define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 19974 #define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 19975 #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 19976 #define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 19977 #define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 19978 #define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 19979 #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 19980 #define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 19981 #define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 19982 #define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 19983 #define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 19984 #define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f 19985 #define VGT_DEBUG_REG28__con_state_q_MASK 0xf 19986 #define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 19987 #define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 19988 #define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 19989 #define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 19990 #define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 19991 #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 19992 #define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 19993 #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 19994 #define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 19995 #define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 19996 #define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 19997 #define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 19998 #define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 19999 #define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 20000 #define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa 20001 #define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 20002 #define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb 20003 #define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 20004 #define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc 20005 #define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 20006 #define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd 20007 #define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 20008 #define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe 20009 #define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 20010 #define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf 20011 #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 20012 #define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 20013 #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 20014 #define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 20015 #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 20016 #define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 20017 #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 20018 #define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 20019 #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 20020 #define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 20021 #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 20022 #define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 20023 #define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 20024 #define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 20025 #define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 20026 #define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 20027 #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 20028 #define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 20029 #define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 20030 #define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 20031 #define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 20032 #define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a 20033 #define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 20034 #define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b 20035 #define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 20036 #define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c 20037 #define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 20038 #define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d 20039 #define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 20040 #define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e 20041 #define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 20042 #define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f 20043 #define VGT_DEBUG_REG29__con_state_q_MASK 0xf 20044 #define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 20045 #define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 20046 #define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 20047 #define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 20048 #define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 20049 #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 20050 #define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 20051 #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 20052 #define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 20053 #define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 20054 #define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 20055 #define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 20056 #define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 20057 #define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 20058 #define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa 20059 #define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 20060 #define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb 20061 #define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 20062 #define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc 20063 #define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 20064 #define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd 20065 #define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 20066 #define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe 20067 #define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 20068 #define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf 20069 #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 20070 #define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 20071 #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 20072 #define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 20073 #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 20074 #define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 20075 #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 20076 #define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 20077 #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 20078 #define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 20079 #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 20080 #define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 20081 #define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 20082 #define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 20083 #define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 20084 #define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 20085 #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 20086 #define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 20087 #define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 20088 #define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 20089 #define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 20090 #define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a 20091 #define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 20092 #define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b 20093 #define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 20094 #define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c 20095 #define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 20096 #define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d 20097 #define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 20098 #define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e 20099 #define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 20100 #define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f 20101 #define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 20102 #define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 20103 #define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 20104 #define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 20105 #define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 20106 #define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 20107 #define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 20108 #define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 20109 #define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 20110 #define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 20111 #define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 20112 #define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 20113 #define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 20114 #define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 20115 #define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 20116 #define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 20117 #define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 20118 #define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 20119 #define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 20120 #define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 20121 #define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 20122 #define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa 20123 #define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 20124 #define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb 20125 #define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 20126 #define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc 20127 #define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 20128 #define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd 20129 #define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 20130 #define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe 20131 #define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 20132 #define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf 20133 #define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 20134 #define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 20135 #define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 20136 #define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 20137 #define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 20138 #define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 20139 #define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 20140 #define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 20141 #define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 20142 #define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 20143 #define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 20144 #define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 20145 #define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 20146 #define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 20147 #define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 20148 #define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 20149 #define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 20150 #define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 20151 #define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 20152 #define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 20153 #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 20154 #define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a 20155 #define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 20156 #define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b 20157 #define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 20158 #define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c 20159 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 20160 #define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d 20161 #define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 20162 #define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e 20163 #define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 20164 #define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f 20165 #define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 20166 #define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 20167 #define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 20168 #define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 20169 #define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 20170 #define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 20171 #define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 20172 #define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 20173 #define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 20174 #define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 20175 #define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 20176 #define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 20177 #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 20178 #define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 20179 #define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 20180 #define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 20181 #define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 20182 #define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 20183 #define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 20184 #define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 20185 #define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 20186 #define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa 20187 #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 20188 #define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb 20189 #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 20190 #define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc 20191 #define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 20192 #define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe 20193 #define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 20194 #define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf 20195 #define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 20196 #define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 20197 #define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 20198 #define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 20199 #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 20200 #define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 20201 #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 20202 #define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 20203 #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 20204 #define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 20205 #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 20206 #define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 20207 #define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 20208 #define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 20209 #define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 20210 #define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 20211 #define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 20212 #define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 20213 #define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 20214 #define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 20215 #define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 20216 #define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a 20217 #define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 20218 #define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b 20219 #define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 20220 #define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c 20221 #define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 20222 #define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 20223 #define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 20224 #define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 20225 #define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 20226 #define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 20227 #define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 20228 #define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 20229 #define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 20230 #define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 20231 #define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 20232 #define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 20233 #define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 20234 #define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 20235 #define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 20236 #define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 20237 #define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 20238 #define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 20239 #define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 20240 #define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 20241 #define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 20242 #define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa 20243 #define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 20244 #define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb 20245 #define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 20246 #define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc 20247 #define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 20248 #define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd 20249 #define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 20250 #define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe 20251 #define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 20252 #define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf 20253 #define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 20254 #define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 20255 #define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 20256 #define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 20257 #define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 20258 #define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 20259 #define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 20260 #define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 20261 #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 20262 #define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 20263 #define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 20264 #define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 20265 #define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 20266 #define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 20267 #define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 20268 #define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 20269 #define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 20270 #define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 20271 #define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 20272 #define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a 20273 #define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 20274 #define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c 20275 #define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 20276 #define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d 20277 #define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 20278 #define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e 20279 #define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 20280 #define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f 20281 #define VGT_DEBUG_REG34__con_state_q_MASK 0xf 20282 #define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 20283 #define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 20284 #define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 20285 #define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 20286 #define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 20287 #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 20288 #define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 20289 #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 20290 #define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 20291 #define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 20292 #define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 20293 #define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 20294 #define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 20295 #define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 20296 #define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa 20297 #define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 20298 #define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb 20299 #define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 20300 #define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc 20301 #define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 20302 #define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd 20303 #define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 20304 #define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe 20305 #define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 20306 #define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf 20307 #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 20308 #define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 20309 #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 20310 #define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 20311 #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 20312 #define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 20313 #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 20314 #define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 20315 #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 20316 #define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 20317 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 20318 #define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 20319 #define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 20320 #define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 20321 #define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 20322 #define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 20323 #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 20324 #define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 20325 #define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 20326 #define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 20327 #define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 20328 #define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a 20329 #define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 20330 #define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b 20331 #define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 20332 #define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c 20333 #define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 20334 #define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d 20335 #define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 20336 #define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e 20337 #define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 20338 #define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f 20339 #define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff 20340 #define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0 20341 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff 20342 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 20343 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 20344 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 20345 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 20346 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 20347 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 20348 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 20349 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 20350 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 20351 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 20352 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 20353 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff 20354 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 20355 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 20356 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 20357 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 20358 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 20359 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 20360 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 20361 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 20362 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 20363 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 20364 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 20365 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 20366 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 20367 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 20368 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 20369 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 20370 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 20371 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 20372 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 20373 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 20374 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 20375 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 20376 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 20377 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 20378 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 20379 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff 20380 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 20381 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 20382 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 20383 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 20384 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 20385 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 20386 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 20387 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 20388 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 20389 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 20390 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 20391 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 20392 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 20393 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 20394 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 20395 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 20396 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 20397 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 20398 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 20399 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 20400 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 20401 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 20402 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 20403 #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff 20404 #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 20405 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 20406 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 20407 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 20408 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 20409 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 20410 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 20411 #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 20412 #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 20413 #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 20414 #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 20415 #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 20416 #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 20417 #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 20418 #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 20419 #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 20420 #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 20421 #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 20422 #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 20423 #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 20424 #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 20425 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff 20426 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 20427 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 20428 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 20429 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 20430 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 20431 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 20432 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 20433 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 20434 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 20435 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 20436 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 20437 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 20438 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 20439 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 20440 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 20441 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 20442 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 20443 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 20444 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 20445 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 20446 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 20447 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 20448 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 20449 #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff 20450 #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 20451 #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 20452 #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 20453 #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff 20454 #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 20455 #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 20456 #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 20457 #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff 20458 #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 20459 #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 20460 #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 20461 #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff 20462 #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 20463 #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 20464 #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 20465 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff 20466 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 20467 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff 20468 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 20469 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff 20470 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 20471 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff 20472 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 20473 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff 20474 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 20475 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff 20476 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 20477 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff 20478 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 20479 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff 20480 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 20481 #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff 20482 #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 20483 #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff 20484 #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 20485 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 20486 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 20487 #define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 20488 #define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 20489 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc 20490 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 20491 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 20492 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 20493 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 20494 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 20495 #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff 20496 #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 20497 #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 20498 #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 20499 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 20500 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 20501 #define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000 20502 #define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe 20503 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 20504 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 20505 #define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000 20506 #define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a 20507 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 20508 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 20509 #define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000 20510 #define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f 20511 #define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff 20512 #define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0 20513 #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 20514 #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 20515 #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff 20516 #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 20517 #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 20518 #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 20519 #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 20520 #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 20521 #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 20522 #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 20523 #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff 20524 #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 20525 #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 20526 #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 20527 #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 20528 #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 20529 #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 20530 #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 20531 #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff 20532 #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 20533 #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 20534 #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 20535 #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 20536 #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 20537 #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 20538 #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 20539 #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 20540 #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 20541 #define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 20542 #define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 20543 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc 20544 #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 20545 #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 20546 #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 20547 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 20548 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 20549 #define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff 20550 #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 20551 #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 20552 #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 20553 #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 20554 #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 20555 #define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000 20556 #define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe 20557 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 20558 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 20559 #define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000 20560 #define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a 20561 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 20562 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 20563 #define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000 20564 #define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f 20565 #define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff 20566 #define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0 20567 #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 20568 #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 20569 #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff 20570 #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 20571 #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 20572 #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 20573 #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 20574 #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 20575 #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 20576 #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 20577 #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff 20578 #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 20579 #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 20580 #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 20581 #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 20582 #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 20583 #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 20584 #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 20585 #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff 20586 #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 20587 #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 20588 #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 20589 #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 20590 #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 20591 #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 20592 #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 20593 #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 20594 #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 20595 #define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 20596 #define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 20597 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc 20598 #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 20599 #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 20600 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 20601 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 20602 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 20603 #define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff 20604 #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 20605 #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 20606 #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 20607 #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 20608 #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 20609 #define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000 20610 #define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe 20611 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 20612 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 20613 #define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000 20614 #define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a 20615 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 20616 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 20617 #define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000 20618 #define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f 20619 #define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff 20620 #define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0 20621 #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 20622 #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 20623 #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff 20624 #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 20625 #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 20626 #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 20627 #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 20628 #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 20629 #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 20630 #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 20631 #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff 20632 #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 20633 #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 20634 #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 20635 #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 20636 #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 20637 #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 20638 #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 20639 #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff 20640 #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 20641 #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 20642 #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 20643 #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 20644 #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 20645 #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 20646 #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 20647 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 20648 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 20649 #define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 20650 #define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 20651 #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc 20652 #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 20653 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 20654 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 20655 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 20656 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 20657 #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff 20658 #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 20659 #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 20660 #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 20661 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 20662 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 20663 #define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000 20664 #define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe 20665 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 20666 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 20667 #define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000 20668 #define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a 20669 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 20670 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 20671 #define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000 20672 #define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f 20673 #define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff 20674 #define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0 20675 #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 20676 #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 20677 #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff 20678 #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 20679 #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 20680 #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 20681 #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 20682 #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 20683 #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 20684 #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 20685 #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff 20686 #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 20687 #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 20688 #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 20689 #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 20690 #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 20691 #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 20692 #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 20693 #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff 20694 #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 20695 #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 20696 #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 20697 #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 20698 #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 20699 #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 20700 #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 20701 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1 20702 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 20703 #define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2 20704 #define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1 20705 #define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc 20706 #define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2 20707 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10 20708 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 20709 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 20710 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 20711 #define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff 20712 #define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 20713 #define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000 20714 #define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 20715 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff 20716 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 20717 #define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000 20718 #define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe 20719 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 20720 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 20721 #define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000 20722 #define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a 20723 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 20724 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 20725 #define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000 20726 #define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f 20727 #define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff 20728 #define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0 20729 #define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 20730 #define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 20731 #define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff 20732 #define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 20733 #define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00 20734 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 20735 #define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000 20736 #define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 20737 #define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000 20738 #define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 20739 #define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff 20740 #define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 20741 #define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00 20742 #define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 20743 #define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000 20744 #define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 20745 #define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000 20746 #define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 20747 #define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff 20748 #define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 20749 #define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00 20750 #define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 20751 #define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000 20752 #define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 20753 #define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000 20754 #define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 20755 20756 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001 20757 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000 20758 20759 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007e 20760 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L 20761 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001 20762 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007 20763 20764 #define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L 20765 #define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d 20766 20767 #define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xe0000000L 20768 #define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d 20769 20770 #define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L 20771 #define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000 20772 20773 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL 20774 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001 20775 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L 20776 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f 20777 20778 #define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001L 20779 #define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000 20780 20781 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007eL 20782 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L 20783 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001 20784 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007 20785 20786 #define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L 20787 #define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d 20788 20789 #define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L 20790 #define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L 20791 #define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006 20792 #define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c 20793 20794 #define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L 20795 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL 20796 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L 20797 20798 #define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000 20799 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001 20800 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f 20801 20802 #define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xe0000000L 20803 #define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d 20804 20805 #define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L 20806 #define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L 20807 #define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006 20808 #define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c 20809 20810 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK 0x00000001L 20811 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000 20812 20813 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000007eL 20814 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00001f80L 20815 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x00000001 20816 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x00000007 20817 20818 #define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK 0x1fffe000L 20819 #define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d 20820 20821 #define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xe0000000L 20822 #define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x0000001d 20823 20824 #define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK 0x00000001L 20825 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00007ffeL 20826 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x1fff8000L 20827 #define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT 0x00000000 20828 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x00000001 20829 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0x0000000f 20830 20831 #define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x00000fc0L 20832 #define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x0003f000L 20833 #define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0x00000006 20834 #define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x0000000c 20835 20836 #endif /* GFX_8_0_SH_MASK_H */ 20837