1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * cx18 ADEC header 4 * 5 * Derived from cx25840-core.h 6 * 7 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 8 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> 9 */ 10 11 #ifndef _CX18_AV_CORE_H_ 12 #define _CX18_AV_CORE_H_ 13 14 #include <media/v4l2-device.h> 15 #include <media/v4l2-ctrls.h> 16 17 struct cx18; 18 19 enum cx18_av_video_input { 20 /* Composite video inputs In1-In8 */ 21 CX18_AV_COMPOSITE1 = 1, 22 CX18_AV_COMPOSITE2, 23 CX18_AV_COMPOSITE3, 24 CX18_AV_COMPOSITE4, 25 CX18_AV_COMPOSITE5, 26 CX18_AV_COMPOSITE6, 27 CX18_AV_COMPOSITE7, 28 CX18_AV_COMPOSITE8, 29 30 /* S-Video inputs consist of one luma input (In1-In8) ORed with one 31 chroma input (In5-In8) */ 32 CX18_AV_SVIDEO_LUMA1 = 0x10, 33 CX18_AV_SVIDEO_LUMA2 = 0x20, 34 CX18_AV_SVIDEO_LUMA3 = 0x30, 35 CX18_AV_SVIDEO_LUMA4 = 0x40, 36 CX18_AV_SVIDEO_LUMA5 = 0x50, 37 CX18_AV_SVIDEO_LUMA6 = 0x60, 38 CX18_AV_SVIDEO_LUMA7 = 0x70, 39 CX18_AV_SVIDEO_LUMA8 = 0x80, 40 CX18_AV_SVIDEO_CHROMA4 = 0x400, 41 CX18_AV_SVIDEO_CHROMA5 = 0x500, 42 CX18_AV_SVIDEO_CHROMA6 = 0x600, 43 CX18_AV_SVIDEO_CHROMA7 = 0x700, 44 CX18_AV_SVIDEO_CHROMA8 = 0x800, 45 46 /* S-Video aliases for common luma/chroma combinations */ 47 CX18_AV_SVIDEO1 = 0x510, 48 CX18_AV_SVIDEO2 = 0x620, 49 CX18_AV_SVIDEO3 = 0x730, 50 CX18_AV_SVIDEO4 = 0x840, 51 52 /* Component Video inputs consist of one luma input (In1-In8) ORed 53 with a red chroma (In4-In6) and blue chroma input (In7-In8) */ 54 CX18_AV_COMPONENT_LUMA1 = 0x1000, 55 CX18_AV_COMPONENT_LUMA2 = 0x2000, 56 CX18_AV_COMPONENT_LUMA3 = 0x3000, 57 CX18_AV_COMPONENT_LUMA4 = 0x4000, 58 CX18_AV_COMPONENT_LUMA5 = 0x5000, 59 CX18_AV_COMPONENT_LUMA6 = 0x6000, 60 CX18_AV_COMPONENT_LUMA7 = 0x7000, 61 CX18_AV_COMPONENT_LUMA8 = 0x8000, 62 CX18_AV_COMPONENT_R_CHROMA4 = 0x40000, 63 CX18_AV_COMPONENT_R_CHROMA5 = 0x50000, 64 CX18_AV_COMPONENT_R_CHROMA6 = 0x60000, 65 CX18_AV_COMPONENT_B_CHROMA7 = 0x700000, 66 CX18_AV_COMPONENT_B_CHROMA8 = 0x800000, 67 68 /* Component Video aliases for common combinations */ 69 CX18_AV_COMPONENT1 = 0x861000, 70 }; 71 72 enum cx18_av_audio_input { 73 /* Audio inputs: serial or In4-In8 */ 74 CX18_AV_AUDIO_SERIAL1, 75 CX18_AV_AUDIO_SERIAL2, 76 CX18_AV_AUDIO4 = 4, 77 CX18_AV_AUDIO5, 78 CX18_AV_AUDIO6, 79 CX18_AV_AUDIO7, 80 CX18_AV_AUDIO8, 81 }; 82 83 struct cx18_av_state { 84 struct v4l2_subdev sd; 85 struct v4l2_ctrl_handler hdl; 86 struct v4l2_ctrl *volume; 87 int radio; 88 v4l2_std_id std; 89 enum cx18_av_video_input vid_input; 90 enum cx18_av_audio_input aud_input; 91 u32 audclk_freq; 92 int audmode; 93 u32 rev; 94 int is_initialized; 95 96 /* 97 * The VBI slicer starts operating and counting lines, beginning at 98 * slicer line count of 1, at D lines after the deassertion of VRESET. 99 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525 100 * line systems respectively. Sliced ancillary data captured on VBI 101 * slicer line M is inserted after the VBI slicer is done with line M, 102 * when VBI slicer line count is N = M+1. Thus when the VBI slicer 103 * reports a VBI slicer line number with ancillary data, the IDID0 byte 104 * indicates VBI slicer line N. The actual field line that the captured 105 * data comes from is 106 * 107 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2). 108 * 109 * L is the line in the field, not frame, from which the VBI data came. 110 * N is the line reported by the slicer in the ancillary data. 111 * D is the slicer_line_delay value programmed into register 0x47f. 112 * S is 6 for 625 line systems or 10 for 525 line systems 113 * (S+D-2) is the slicer_line_offset used to convert slicer reported 114 * line counts to actual field lines. 115 */ 116 int slicer_line_delay; 117 int slicer_line_offset; 118 }; 119 120 121 /* Registers */ 122 #define CXADEC_CHIP_TYPE_TIGER 0x837 123 #define CXADEC_CHIP_TYPE_MAKO 0x843 124 125 #define CXADEC_HOST_REG1 0x000 126 #define CXADEC_HOST_REG2 0x001 127 128 #define CXADEC_CHIP_CTRL 0x100 129 #define CXADEC_AFE_CTRL 0x104 130 #define CXADEC_PLL_CTRL1 0x108 131 #define CXADEC_VID_PLL_FRAC 0x10C 132 #define CXADEC_AUX_PLL_FRAC 0x110 133 #define CXADEC_PIN_CTRL1 0x114 134 #define CXADEC_PIN_CTRL2 0x118 135 #define CXADEC_PIN_CFG1 0x11C 136 #define CXADEC_PIN_CFG2 0x120 137 138 #define CXADEC_PIN_CFG3 0x124 139 #define CXADEC_I2S_MCLK 0x127 140 141 #define CXADEC_AUD_LOCK1 0x128 142 #define CXADEC_AUD_LOCK2 0x12C 143 #define CXADEC_POWER_CTRL 0x130 144 #define CXADEC_AFE_DIAG_CTRL1 0x134 145 #define CXADEC_AFE_DIAG_CTRL2 0x138 146 #define CXADEC_AFE_DIAG_CTRL3 0x13C 147 #define CXADEC_PLL_DIAG_CTRL 0x140 148 #define CXADEC_TEST_CTRL1 0x144 149 #define CXADEC_TEST_CTRL2 0x148 150 #define CXADEC_BIST_STAT 0x14C 151 #define CXADEC_DLL1_DIAG_CTRL 0x158 152 #define CXADEC_DLL2_DIAG_CTRL 0x15C 153 154 /* IR registers */ 155 #define CXADEC_IR_CTRL_REG 0x200 156 #define CXADEC_IR_TXCLK_REG 0x204 157 #define CXADEC_IR_RXCLK_REG 0x208 158 #define CXADEC_IR_CDUTY_REG 0x20C 159 #define CXADEC_IR_STAT_REG 0x210 160 #define CXADEC_IR_IRQEN_REG 0x214 161 #define CXADEC_IR_FILTER_REG 0x218 162 #define CXADEC_IR_FIFO_REG 0x21C 163 164 /* Video Registers */ 165 #define CXADEC_MODE_CTRL 0x400 166 #define CXADEC_OUT_CTRL1 0x404 167 #define CXADEC_OUT_CTRL2 0x408 168 #define CXADEC_GEN_STAT 0x40C 169 #define CXADEC_INT_STAT_MASK 0x410 170 #define CXADEC_LUMA_CTRL 0x414 171 172 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414 173 #define CXADEC_CONTRAST_CTRL_BYTE 0x415 174 #define CXADEC_LUMA_CTRL_BYTE_3 0x416 175 176 #define CXADEC_HSCALE_CTRL 0x418 177 #define CXADEC_VSCALE_CTRL 0x41C 178 179 #define CXADEC_CHROMA_CTRL 0x420 180 181 #define CXADEC_USAT_CTRL_BYTE 0x420 182 #define CXADEC_VSAT_CTRL_BYTE 0x421 183 #define CXADEC_HUE_CTRL_BYTE 0x422 184 185 #define CXADEC_VBI_LINE_CTRL1 0x424 186 #define CXADEC_VBI_LINE_CTRL2 0x428 187 #define CXADEC_VBI_LINE_CTRL3 0x42C 188 #define CXADEC_VBI_LINE_CTRL4 0x430 189 #define CXADEC_VBI_LINE_CTRL5 0x434 190 #define CXADEC_VBI_FC_CFG 0x438 191 #define CXADEC_VBI_MISC_CFG1 0x43C 192 #define CXADEC_VBI_MISC_CFG2 0x440 193 #define CXADEC_VBI_PAY1 0x444 194 #define CXADEC_VBI_PAY2 0x448 195 #define CXADEC_VBI_CUST1_CFG1 0x44C 196 #define CXADEC_VBI_CUST1_CFG2 0x450 197 #define CXADEC_VBI_CUST1_CFG3 0x454 198 #define CXADEC_VBI_CUST2_CFG1 0x458 199 #define CXADEC_VBI_CUST2_CFG2 0x45C 200 #define CXADEC_VBI_CUST2_CFG3 0x460 201 #define CXADEC_VBI_CUST3_CFG1 0x464 202 #define CXADEC_VBI_CUST3_CFG2 0x468 203 #define CXADEC_VBI_CUST3_CFG3 0x46C 204 #define CXADEC_HORIZ_TIM_CTRL 0x470 205 #define CXADEC_VERT_TIM_CTRL 0x474 206 #define CXADEC_SRC_COMB_CFG 0x478 207 #define CXADEC_CHROMA_VBIOFF_CFG 0x47C 208 #define CXADEC_FIELD_COUNT 0x480 209 #define CXADEC_MISC_TIM_CTRL 0x484 210 #define CXADEC_DFE_CTRL1 0x488 211 #define CXADEC_DFE_CTRL2 0x48C 212 #define CXADEC_DFE_CTRL3 0x490 213 #define CXADEC_PLL_CTRL2 0x494 214 #define CXADEC_HTL_CTRL 0x498 215 #define CXADEC_COMB_CTRL 0x49C 216 #define CXADEC_CRUSH_CTRL 0x4A0 217 #define CXADEC_SOFT_RST_CTRL 0x4A4 218 #define CXADEC_MV_DT_CTRL2 0x4A8 219 #define CXADEC_MV_DT_CTRL3 0x4AC 220 #define CXADEC_MISC_DIAG_CTRL 0x4B8 221 222 #define CXADEC_DL_CTL 0x800 223 #define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 224 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 225 #define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 226 #define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 227 228 #define CXADEC_STD_DET_STATUS 0x804 229 230 #define CXADEC_STD_DET_CTL 0x808 231 #define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 232 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 233 234 #define CXADEC_DW8051_INT 0x80C 235 #define CXADEC_GENERAL_CTL 0x810 236 #define CXADEC_AAGC_CTL 0x814 237 #define CXADEC_IF_SRC_CTL 0x818 238 #define CXADEC_ANLOG_DEMOD_CTL 0x81C 239 #define CXADEC_ROT_FREQ_CTL 0x820 240 #define CXADEC_FM1_CTL 0x824 241 #define CXADEC_PDF_CTL 0x828 242 #define CXADEC_DFT1_CTL1 0x82C 243 #define CXADEC_DFT1_CTL2 0x830 244 #define CXADEC_DFT_STATUS 0x834 245 #define CXADEC_DFT2_CTL1 0x838 246 #define CXADEC_DFT2_CTL2 0x83C 247 #define CXADEC_DFT2_STATUS 0x840 248 #define CXADEC_DFT3_CTL1 0x844 249 #define CXADEC_DFT3_CTL2 0x848 250 #define CXADEC_DFT3_STATUS 0x84C 251 #define CXADEC_DFT4_CTL1 0x850 252 #define CXADEC_DFT4_CTL2 0x854 253 #define CXADEC_DFT4_STATUS 0x858 254 #define CXADEC_AM_MTS_DET 0x85C 255 #define CXADEC_ANALOG_MUX_CTL 0x860 256 #define CXADEC_DIG_PLL_CTL1 0x864 257 #define CXADEC_DIG_PLL_CTL2 0x868 258 #define CXADEC_DIG_PLL_CTL3 0x86C 259 #define CXADEC_DIG_PLL_CTL4 0x870 260 #define CXADEC_DIG_PLL_CTL5 0x874 261 #define CXADEC_DEEMPH_GAIN_CTL 0x878 262 #define CXADEC_DEEMPH_COEF1 0x87C 263 #define CXADEC_DEEMPH_COEF2 0x880 264 #define CXADEC_DBX1_CTL1 0x884 265 #define CXADEC_DBX1_CTL2 0x888 266 #define CXADEC_DBX1_STATUS 0x88C 267 #define CXADEC_DBX2_CTL1 0x890 268 #define CXADEC_DBX2_CTL2 0x894 269 #define CXADEC_DBX2_STATUS 0x898 270 #define CXADEC_AM_FM_DIFF 0x89C 271 272 /* NICAM registers go here */ 273 #define CXADEC_NICAM_STATUS 0x8C8 274 #define CXADEC_DEMATRIX_CTL 0x8CC 275 276 #define CXADEC_PATH1_CTL1 0x8D0 277 #define CXADEC_PATH1_VOL_CTL 0x8D4 278 #define CXADEC_PATH1_EQ_CTL 0x8D8 279 #define CXADEC_PATH1_SC_CTL 0x8DC 280 281 #define CXADEC_PATH2_CTL1 0x8E0 282 #define CXADEC_PATH2_VOL_CTL 0x8E4 283 #define CXADEC_PATH2_EQ_CTL 0x8E8 284 #define CXADEC_PATH2_SC_CTL 0x8EC 285 286 #define CXADEC_SRC_CTL 0x8F0 287 #define CXADEC_SRC_LF_COEF 0x8F4 288 #define CXADEC_SRC1_CTL 0x8F8 289 #define CXADEC_SRC2_CTL 0x8FC 290 #define CXADEC_SRC3_CTL 0x900 291 #define CXADEC_SRC4_CTL 0x904 292 #define CXADEC_SRC5_CTL 0x908 293 #define CXADEC_SRC6_CTL 0x90C 294 295 #define CXADEC_BASEBAND_OUT_SEL 0x910 296 #define CXADEC_I2S_IN_CTL 0x914 297 #define CXADEC_I2S_OUT_CTL 0x918 298 #define CXADEC_AC97_CTL 0x91C 299 #define CXADEC_QAM_PDF 0x920 300 #define CXADEC_QAM_CONST_DEC 0x924 301 #define CXADEC_QAM_ROTATOR_FREQ 0x948 302 303 /* Bit definitions / settings used in Mako Audio */ 304 #define CXADEC_PREF_MODE_MONO_LANGA 0 305 #define CXADEC_PREF_MODE_MONO_LANGB 1 306 #define CXADEC_PREF_MODE_MONO_LANGC 2 307 #define CXADEC_PREF_MODE_FALLBACK 3 308 #define CXADEC_PREF_MODE_STEREO 4 309 #define CXADEC_PREF_MODE_DUAL_LANG_AC 5 310 #define CXADEC_PREF_MODE_DUAL_LANG_BC 6 311 #define CXADEC_PREF_MODE_DUAL_LANG_AB 7 312 313 314 #define CXADEC_DETECT_STEREO 1 315 #define CXADEC_DETECT_DUAL 2 316 #define CXADEC_DETECT_TRI 4 317 #define CXADEC_DETECT_SAP 0x10 318 #define CXADEC_DETECT_NO_SIGNAL 0xFF 319 320 #define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */ 321 #define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */ 322 #define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2 323 #define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3 324 #define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */ 325 #define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */ 326 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6 327 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7 328 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */ 329 #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */ 330 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */ 331 to_cx18_av_state(struct v4l2_subdev * sd)332 static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd) 333 { 334 return container_of(sd, struct cx18_av_state, sd); 335 } 336 to_sd(struct v4l2_ctrl * ctrl)337 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 338 { 339 return &container_of(ctrl->handler, struct cx18_av_state, hdl)->sd; 340 } 341 342 /* ----------------------------------------------------------------------- */ 343 /* cx18_av-core.c */ 344 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); 345 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); 346 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value); 347 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask); 348 int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, 349 u32 mask); 350 u8 cx18_av_read(struct cx18 *cx, u16 addr); 351 u32 cx18_av_read4(struct cx18 *cx, u16 addr); 352 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); 353 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); 354 void cx18_av_std_setup(struct cx18 *cx); 355 356 int cx18_av_probe(struct cx18 *cx); 357 358 /* ----------------------------------------------------------------------- */ 359 /* cx18_av-firmware.c */ 360 int cx18_av_loadfw(struct cx18 *cx); 361 362 /* ----------------------------------------------------------------------- */ 363 /* cx18_av-audio.c */ 364 int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq); 365 void cx18_av_audio_set_path(struct cx18 *cx); 366 extern const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops; 367 368 /* ----------------------------------------------------------------------- */ 369 /* cx18_av-vbi.c */ 370 int cx18_av_decode_vbi_line(struct v4l2_subdev *sd, 371 struct v4l2_decode_vbi_line *vbi); 372 int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt); 373 int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); 374 int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt); 375 376 #endif 377