1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the MMC / SD / SDIO cell found in: 4 * 5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3 6 * 7 * Copyright (C) 2015-19 Renesas Electronics Corporation 8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 10 * Copyright (C) 2007 Ian Molton 11 * Copyright (C) 2004 Ian Molton 12 */ 13 14 #ifndef TMIO_MMC_H 15 #define TMIO_MMC_H 16 17 #include <linux/dmaengine.h> 18 #include <linux/highmem.h> 19 #include <linux/mutex.h> 20 #include <linux/pagemap.h> 21 #include <linux/scatterlist.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 26 #define CTL_SD_CMD 0x00 27 #define CTL_ARG_REG 0x04 28 #define CTL_STOP_INTERNAL_ACTION 0x08 29 #define CTL_XFER_BLK_COUNT 0xa 30 #define CTL_RESPONSE 0x0c 31 /* driver merges STATUS and following STATUS2 */ 32 #define CTL_STATUS 0x1c 33 /* driver merges IRQ_MASK and following IRQ_MASK2 */ 34 #define CTL_IRQ_MASK 0x20 35 #define CTL_SD_CARD_CLK_CTL 0x24 36 #define CTL_SD_XFER_LEN 0x26 37 #define CTL_SD_MEM_CARD_OPT 0x28 38 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c 39 #define CTL_SD_DATA_PORT 0x30 40 #define CTL_TRANSACTION_CTL 0x34 41 #define CTL_SDIO_STATUS 0x36 42 #define CTL_SDIO_IRQ_MASK 0x38 43 #define CTL_DMA_ENABLE 0xd8 44 #define CTL_RESET_SD 0xe0 45 #define CTL_VERSION 0xe2 46 #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */ 47 48 /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ 49 #define TMIO_STOP_STP BIT(0) 50 #define TMIO_STOP_SEC BIT(8) 51 52 /* Definitions for values the CTL_STATUS register can take */ 53 #define TMIO_STAT_CMDRESPEND BIT(0) 54 #define TMIO_STAT_DATAEND BIT(2) 55 #define TMIO_STAT_CARD_REMOVE BIT(3) 56 #define TMIO_STAT_CARD_INSERT BIT(4) 57 #define TMIO_STAT_SIGSTATE BIT(5) 58 #define TMIO_STAT_WRPROTECT BIT(7) 59 #define TMIO_STAT_CARD_REMOVE_A BIT(8) 60 #define TMIO_STAT_CARD_INSERT_A BIT(9) 61 #define TMIO_STAT_SIGSTATE_A BIT(10) 62 63 /* These belong technically to CTL_STATUS2, but the driver merges them */ 64 #define TMIO_STAT_CMD_IDX_ERR BIT(16) 65 #define TMIO_STAT_CRCFAIL BIT(17) 66 #define TMIO_STAT_STOPBIT_ERR BIT(18) 67 #define TMIO_STAT_DATATIMEOUT BIT(19) 68 #define TMIO_STAT_RXOVERFLOW BIT(20) 69 #define TMIO_STAT_TXUNDERRUN BIT(21) 70 #define TMIO_STAT_CMDTIMEOUT BIT(22) 71 #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */ 72 #define TMIO_STAT_RXRDY BIT(24) 73 #define TMIO_STAT_TXRQ BIT(25) 74 #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */ 75 #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */ 76 #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */ 77 #define TMIO_STAT_CMD_BUSY BIT(30) 78 #define TMIO_STAT_ILL_ACCESS BIT(31) 79 80 /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */ 81 #define CLK_CTL_DIV_MASK 0xff 82 #define CLK_CTL_SCLKEN BIT(8) 83 84 /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */ 85 #define CARD_OPT_TOP_MASK 0xf0 86 #define CARD_OPT_TOP_SHIFT 4 87 #define CARD_OPT_EXTOP BIT(9) /* first appeared on R-Car Gen3 SDHI */ 88 #define CARD_OPT_WIDTH8 BIT(13) 89 #define CARD_OPT_ALWAYS1 BIT(14) 90 #define CARD_OPT_WIDTH BIT(15) 91 92 /* Definitions for values the CTL_SDIO_STATUS register can take */ 93 #define TMIO_SDIO_STAT_IOIRQ 0x0001 94 #define TMIO_SDIO_STAT_EXPUB52 0x4000 95 #define TMIO_SDIO_STAT_EXWT 0x8000 96 #define TMIO_SDIO_MASK_ALL 0xc007 97 98 #define TMIO_SDIO_SETBITS_MASK 0x0006 99 100 /* Definitions for values the CTL_DMA_ENABLE register can take */ 101 #define DMA_ENABLE_DMASDRW BIT(1) 102 103 /* Definitions for values the CTL_SDIF_MODE register can take */ 104 #define SDIF_MODE_HS400 BIT(0) /* only known on R-Car 2+ */ 105 106 /* Define some IRQ masks */ 107 /* This is the mask used at reset by the chip */ 108 #define TMIO_MASK_ALL 0x837f031d 109 #define TMIO_MASK_ALL_RCAR2 0x8b7f031d 110 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) 111 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) 112 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ 113 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) 114 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) 115 116 #define TMIO_MAX_BLK_SIZE 512 117 118 struct tmio_mmc_data; 119 struct tmio_mmc_host; 120 121 struct tmio_mmc_dma_ops { 122 void (*start)(struct tmio_mmc_host *host, struct mmc_data *data); 123 void (*enable)(struct tmio_mmc_host *host, bool enable); 124 void (*request)(struct tmio_mmc_host *host, 125 struct tmio_mmc_data *pdata); 126 void (*release)(struct tmio_mmc_host *host); 127 void (*abort)(struct tmio_mmc_host *host); 128 void (*dataend)(struct tmio_mmc_host *host); 129 130 /* optional */ 131 void (*end)(struct tmio_mmc_host *host); /* held host->lock */ 132 bool (*dma_irq)(struct tmio_mmc_host *host); 133 }; 134 135 struct tmio_mmc_host { 136 void __iomem *ctl; 137 struct mmc_command *cmd; 138 struct mmc_request *mrq; 139 struct mmc_data *data; 140 struct mmc_host *mmc; 141 struct mmc_host_ops ops; 142 143 /* pio related stuff */ 144 struct scatterlist *sg_ptr; 145 struct scatterlist *sg_orig; 146 unsigned int sg_len; 147 unsigned int sg_off; 148 unsigned int bus_shift; 149 150 struct platform_device *pdev; 151 struct tmio_mmc_data *pdata; 152 153 /* DMA support */ 154 bool dma_on; 155 struct dma_chan *chan_rx; 156 struct dma_chan *chan_tx; 157 struct work_struct dma_issue; 158 struct scatterlist bounce_sg; 159 u8 *bounce_buf; 160 161 /* Track lost interrupts */ 162 struct delayed_work delayed_reset_work; 163 struct work_struct done; 164 165 /* Cache */ 166 u32 sdcard_irq_mask; 167 u32 sdio_irq_mask; 168 unsigned int clk_cache; 169 u32 sdcard_irq_setbit_mask; 170 u32 sdcard_irq_mask_all; 171 172 spinlock_t lock; /* protect host private data */ 173 unsigned long last_req_ts; 174 struct mutex ios_lock; /* protect set_ios() context */ 175 bool native_hotplug; 176 bool sdio_irq_enabled; 177 178 /* Mandatory callback */ 179 int (*clk_enable)(struct tmio_mmc_host *host); 180 void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); 181 182 /* Optional callbacks */ 183 void (*clk_disable)(struct tmio_mmc_host *host); 184 int (*multi_io_quirk)(struct mmc_card *card, 185 unsigned int direction, int blk_size); 186 int (*write16_hook)(struct tmio_mmc_host *host, int addr); 187 void (*reset)(struct tmio_mmc_host *host, bool preserve); 188 bool (*check_retune)(struct tmio_mmc_host *host, struct mmc_request *mrq); 189 void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq); 190 unsigned int (*get_timeout_cycles)(struct tmio_mmc_host *host); 191 192 const struct tmio_mmc_dma_ops *dma_ops; 193 }; 194 195 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev, 196 struct tmio_mmc_data *pdata); 197 void tmio_mmc_host_free(struct tmio_mmc_host *host); 198 int tmio_mmc_host_probe(struct tmio_mmc_host *host); 199 void tmio_mmc_host_remove(struct tmio_mmc_host *host); 200 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host); 201 202 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 203 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 204 irqreturn_t tmio_mmc_irq(int irq, void *devid); 205 206 #ifdef CONFIG_PM 207 int tmio_mmc_host_runtime_suspend(struct device *dev); 208 int tmio_mmc_host_runtime_resume(struct device *dev); 209 #endif 210 sd_ctrl_read16(struct tmio_mmc_host * host,int addr)211 static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) 212 { 213 return ioread16(host->ctl + (addr << host->bus_shift)); 214 } 215 sd_ctrl_read16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)216 static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, 217 u16 *buf, int count) 218 { 219 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count); 220 } 221 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host * host,int addr)222 static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, 223 int addr) 224 { 225 return ioread16(host->ctl + (addr << host->bus_shift)) | 226 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16; 227 } 228 sd_ctrl_read32_rep(struct tmio_mmc_host * host,int addr,u32 * buf,int count)229 static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr, 230 u32 *buf, int count) 231 { 232 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count); 233 } 234 sd_ctrl_write16(struct tmio_mmc_host * host,int addr,u16 val)235 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, 236 u16 val) 237 { 238 /* If there is a hook and it returns non-zero then there 239 * is an error and the write should be skipped 240 */ 241 if (host->write16_hook && host->write16_hook(host, addr)) 242 return; 243 iowrite16(val, host->ctl + (addr << host->bus_shift)); 244 } 245 sd_ctrl_write16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)246 static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, 247 u16 *buf, int count) 248 { 249 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count); 250 } 251 sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host * host,int addr,u32 val)252 static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, 253 int addr, u32 val) 254 { 255 if (addr == CTL_IRQ_MASK || addr == CTL_STATUS) 256 val |= host->sdcard_irq_setbit_mask; 257 258 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift)); 259 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); 260 } 261 sd_ctrl_write32(struct tmio_mmc_host * host,int addr,u32 val)262 static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) 263 { 264 iowrite32(val, host->ctl + (addr << host->bus_shift)); 265 } 266 sd_ctrl_write32_rep(struct tmio_mmc_host * host,int addr,const u32 * buf,int count)267 static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr, 268 const u32 *buf, int count) 269 { 270 iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count); 271 } 272 273 #endif 274