1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Performance Monitor Drivers
4#
5
6menu "Performance monitor support"
7	depends on PERF_EVENTS
8
9config ARM_CCI_PMU
10	tristate "ARM CCI PMU driver"
11	depends on (ARM && CPU_V7) || ARM64
12	select ARM_CCI
13	help
14	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
15	  Interconnect) family of products.
16
17	  If compiled as a module, it will be called arm-cci.
18
19config ARM_CCI400_PMU
20	bool "support CCI-400"
21	default y
22	depends on ARM_CCI_PMU
23	select ARM_CCI400_COMMON
24	help
25	  CCI-400 provides 4 independent event counters counting events related
26	  to the connected slave/master interfaces, plus a cycle counter.
27
28config ARM_CCI5xx_PMU
29	bool "support CCI-500/CCI-550"
30	default y
31	depends on ARM_CCI_PMU
32	help
33	  CCI-500/CCI-550 both provide 8 independent event counters, which can
34	  count events pertaining to the slave/master interfaces as well as the
35	  internal events to the CCI.
36
37config ARM_CCN
38	tristate "ARM CCN driver support"
39	depends on ARM || ARM64 || COMPILE_TEST
40	help
41	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
42	  interconnect.
43
44config ARM_CMN
45	tristate "Arm CMN-600 PMU support"
46	depends on ARM64 || COMPILE_TEST
47	help
48	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
49	  Network interconnect.
50
51config ARM_NI
52	tristate "Arm NI-700 PMU support"
53	depends on ARM64 || COMPILE_TEST
54	help
55	  Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
56	  interconnect and family.
57
58config ARM_PMU
59	depends on ARM || ARM64
60	bool "ARM PMU framework"
61	default y
62	help
63	  Say y if you want to use CPU performance monitors on ARM-based
64	  systems.
65
66config ARM_V6_PMU
67	depends on ARM_PMU && (CPU_V6 || CPU_V6K)
68	def_bool y
69
70config ARM_V7_PMU
71	depends on ARM_PMU && CPU_V7
72	def_bool y
73
74config ARM_XSCALE_PMU
75	depends on ARM_PMU && CPU_XSCALE
76	def_bool y
77
78config RISCV_PMU
79	depends on RISCV
80	bool "RISC-V PMU framework"
81	default y
82	help
83	  Say y if you want to use CPU performance monitors on RISCV-based
84	  systems. This provides the core PMU framework that abstracts common
85	  PMU functionalities in a core library so that different PMU drivers
86	  can reuse it.
87
88config RISCV_PMU_LEGACY
89	depends on RISCV_PMU
90	bool "RISC-V legacy PMU implementation"
91	default y
92	help
93	  Say y if you want to use the legacy CPU performance monitor
94	  implementation on RISC-V based systems. This only allows counting
95	  of cycle/instruction counter and doesn't support counter overflow,
96	  or programmable counters. It will be removed in future.
97
98config RISCV_PMU_SBI
99	depends on RISCV_PMU && RISCV_SBI
100	bool "RISC-V PMU based on SBI PMU extension"
101	default y
102	help
103	  Say y if you want to use the CPU performance monitor
104	  using SBI PMU extension on RISC-V based systems. This option provides
105	  full perf feature support i.e. counter overflow, privilege mode
106	  filtering, counter configuration.
107
108config STARFIVE_STARLINK_PMU
109	depends on ARCH_STARFIVE || COMPILE_TEST
110	depends on 64BIT
111	bool "StarFive StarLink PMU"
112	help
113	   Provide support for StarLink Performance Monitor Unit.
114	   StarLink Performance Monitor Unit integrates one or more cores with
115	   an L3 memory system. The L3 cache events are added into perf event
116	   subsystem, allowing monitoring of various L3 cache perf events.
117
118config ANDES_CUSTOM_PMU
119	bool "Andes custom PMU support"
120	depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
121	default y
122	help
123	  The Andes cores implement the PMU overflow extension very
124	  similar to the standard Sscofpmf and Smcntrpmf extension.
125
126	  This will patch the overflow and pending CSRs and handle the
127	  non-standard behaviour via the regular SBI PMU driver and
128	  interface.
129
130	  If you don't know what to do here, say "Y".
131
132config ARM_PMU_ACPI
133	depends on ARM_PMU && ACPI
134	def_bool y
135
136config ARM_SMMU_V3_PMU
137	 tristate "ARM SMMUv3 Performance Monitors Extension"
138	 depends on ARM64 || (COMPILE_TEST && 64BIT)
139	 depends on GENERIC_MSI_IRQ
140	   help
141	   Provides support for the ARM SMMUv3 Performance Monitor Counter
142	   Groups (PMCG), which provide monitoring of transactions passing
143	   through the SMMU and allow the resulting information to be filtered
144	   based on the Stream ID of the corresponding master.
145
146config ARM_PMUV3
147	depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64)
148	bool "ARM PMUv3 support" if !ARM64
149	default ARM64
150	  help
151	  Say y if you want to use the ARM performance monitor unit (PMU)
152	  version 3. The PMUv3 is the CPU performance monitors on ARMv8
153	  (aarch32 and aarch64) systems that implement the PMUv3
154	  architecture.
155
156config ARM_DSU_PMU
157	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
158	depends on ARM64
159	  help
160	  Provides support for performance monitor unit in ARM DynamIQ Shared
161	  Unit (DSU). The DSU integrates one or more cores with an L3 memory
162	  system, control logic. The PMU allows counting various events related
163	  to DSU.
164
165config FSL_IMX8_DDR_PMU
166	tristate "Freescale i.MX8 DDR perf monitor"
167	depends on ARCH_MXC || COMPILE_TEST
168	  help
169	  Provides support for the DDR performance monitor in i.MX8, which
170	  can give information about memory throughput and other related
171	  events.
172
173config FSL_IMX9_DDR_PMU
174	tristate "Freescale i.MX9 DDR perf monitor"
175	depends on ARCH_MXC
176	 help
177	 Provides support for the DDR performance monitor in i.MX9, which
178	 can give information about memory throughput and other related
179	 events.
180
181config QCOM_L2_PMU
182	bool "Qualcomm Technologies L2-cache PMU"
183	depends on ARCH_QCOM && ARM64 && ACPI
184	select QCOM_KRYO_L2_ACCESSORS
185	  help
186	  Provides support for the L2 cache performance monitor unit (PMU)
187	  in Qualcomm Technologies processors.
188	  Adds the L2 cache PMU into the perf events subsystem for
189	  monitoring L2 cache events.
190
191config QCOM_L3_PMU
192	bool "Qualcomm Technologies L3-cache PMU"
193	depends on ARCH_QCOM && ARM64 && ACPI
194	select QCOM_IRQ_COMBINER
195	help
196	   Provides support for the L3 cache performance monitor unit (PMU)
197	   in Qualcomm Technologies processors.
198	   Adds the L3 cache PMU into the perf events subsystem for
199	   monitoring L3 cache events.
200
201config THUNDERX2_PMU
202	tristate "Cavium ThunderX2 SoC PMU UNCORE"
203	depends on ARCH_THUNDER2 || COMPILE_TEST
204	depends on NUMA && ACPI
205	default m
206	help
207	   Provides support for ThunderX2 UNCORE events.
208	   The SoC has PMU support in its L3 cache controller (L3C) and
209	   in the DDR4 Memory Controller (DMC).
210
211config XGENE_PMU
212        depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
213        bool "APM X-Gene SoC PMU"
214        default n
215        help
216          Say y if you want to use APM X-Gene SoC performance monitors.
217
218config ARM_SPE_PMU
219	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
220	depends on ARM64
221	help
222	  Enable perf support for the ARMv8.2 Statistical Profiling
223	  Extension, which provides periodic sampling of operations in
224	  the CPU pipeline and reports this via the perf AUX interface.
225
226config ARM_DMC620_PMU
227	tristate "Enable PMU support for the ARM DMC-620 memory controller"
228	depends on (ARM64 && ACPI) || COMPILE_TEST
229	help
230	  Support for PMU events monitoring on the ARM DMC-620 memory
231	  controller.
232
233config MARVELL_CN10K_TAD_PMU
234	tristate "Marvell CN10K LLC-TAD PMU"
235	depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
236	help
237	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
238	  performance monitors on CN10K family silicons.
239
240config APPLE_M1_CPU_PMU
241	bool "Apple M1 CPU PMU support"
242	depends on ARM_PMU && ARCH_APPLE
243	help
244	  Provides support for the non-architectural CPU PMUs present on
245	  the Apple M1 SoCs and derivatives.
246
247config ALIBABA_UNCORE_DRW_PMU
248	tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
249	depends on (ARM64 && ACPI) || COMPILE_TEST
250	help
251	  Support for Driveway PMU events monitoring on Yitian 710 DDR
252	  Sub-system.
253
254source "drivers/perf/hisilicon/Kconfig"
255
256config MARVELL_CN10K_DDR_PMU
257	tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
258	depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
259	help
260	  Enable perf support for Marvell DDR Performance monitoring
261	  event on CN10K platform.
262
263config DWC_PCIE_PMU
264	tristate "Synopsys DesignWare PCIe PMU"
265	depends on PCI
266	help
267	  Enable perf support for Synopsys DesignWare PCIe PMU Performance
268	  monitoring event on platform including the Alibaba Yitian 710.
269
270source "drivers/perf/arm_cspmu/Kconfig"
271
272source "drivers/perf/amlogic/Kconfig"
273
274config CXL_PMU
275	tristate "CXL Performance Monitoring Unit"
276	depends on CXL_BUS
277	help
278	  Support performance monitoring as defined in CXL rev 3.0
279	  section 13.2: Performance Monitoring. CXL components may have
280	  one or more CXL Performance Monitoring Units (CPMUs).
281
282	  Say 'y/m' to enable a driver that will attach to performance
283	  monitoring units and provide standard perf based interfaces.
284
285	  If unsure say 'm'.
286
287endmenu
288