1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/firmware.h> 17 #include <linux/panic_notifier.h> 18 #include "qmi.h" 19 #include "htc.h" 20 #include "wmi.h" 21 #include "hal.h" 22 #include "dp.h" 23 #include "ce.h" 24 #include "mac.h" 25 #include "hw.h" 26 #include "hal_rx.h" 27 #include "reg.h" 28 #include "dbring.h" 29 #include "fw.h" 30 #include "acpi.h" 31 #include "wow.h" 32 #include "debugfs_htt_stats.h" 33 34 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 35 36 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 37 38 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 39 40 /* Pending management packets threshold for dropping probe responses */ 41 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 42 43 /* SMBIOS type containing Board Data File Name Extension */ 44 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8 45 46 /* SMBIOS type structure length (excluding strings-set) */ 47 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9 48 49 /* The magic used by QCA spec */ 50 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_" 51 52 #define ATH12K_INVALID_HW_MAC_ID 0xFF 53 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ) 54 #define ATH12K_RX_RATE_TABLE_NUM 320 55 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 56 57 #define ATH12K_MON_TIMER_INTERVAL 10 58 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 59 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 60 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 61 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 62 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 63 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 64 65 enum ath12k_bdf_search { 66 ATH12K_BDF_SEARCH_DEFAULT, 67 ATH12K_BDF_SEARCH_BUS_AND_BOARD, 68 }; 69 70 enum wme_ac { 71 WME_AC_BE, 72 WME_AC_BK, 73 WME_AC_VI, 74 WME_AC_VO, 75 WME_NUM_AC 76 }; 77 78 #define ATH12K_HT_MCS_MAX 7 79 #define ATH12K_VHT_MCS_MAX 9 80 #define ATH12K_HE_MCS_MAX 11 81 82 enum ath12k_crypt_mode { 83 /* Only use hardware crypto engine */ 84 ATH12K_CRYPT_MODE_HW, 85 /* Only use software crypto */ 86 ATH12K_CRYPT_MODE_SW, 87 }; 88 ath12k_tid_to_ac(u32 tid)89 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 90 { 91 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 92 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 93 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 94 WME_AC_VO); 95 } 96 97 enum ath12k_skb_flags { 98 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 99 ATH12K_SKB_CIPHER_SET = BIT(1), 100 }; 101 102 struct ath12k_skb_cb { 103 dma_addr_t paddr; 104 struct ath12k *ar; 105 struct ieee80211_vif *vif; 106 dma_addr_t paddr_ext_desc; 107 u32 cipher; 108 u8 flags; 109 }; 110 111 struct ath12k_skb_rxcb { 112 dma_addr_t paddr; 113 bool is_first_msdu; 114 bool is_last_msdu; 115 bool is_continuation; 116 bool is_mcbc; 117 bool is_eapol; 118 struct hal_rx_desc *rx_desc; 119 u8 err_rel_src; 120 u8 err_code; 121 u8 mac_id; 122 u8 unmapped; 123 u8 is_frag; 124 u8 tid; 125 u16 peer_id; 126 }; 127 128 enum ath12k_hw_rev { 129 ATH12K_HW_QCN9274_HW10, 130 ATH12K_HW_QCN9274_HW20, 131 ATH12K_HW_WCN7850_HW20 132 }; 133 134 enum ath12k_firmware_mode { 135 /* the default mode, standard 802.11 functionality */ 136 ATH12K_FIRMWARE_MODE_NORMAL, 137 138 /* factory tests etc */ 139 ATH12K_FIRMWARE_MODE_FTM, 140 }; 141 142 #define ATH12K_IRQ_NUM_MAX 57 143 #define ATH12K_EXT_IRQ_NUM_MAX 16 144 145 struct ath12k_ext_irq_grp { 146 struct ath12k_base *ab; 147 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 148 u32 num_irq; 149 u32 grp_id; 150 u64 timestamp; 151 struct napi_struct napi; 152 struct net_device *napi_ndev; 153 }; 154 155 struct ath12k_smbios_bdf { 156 struct dmi_header hdr; 157 u32 padding; 158 u8 bdf_enabled; 159 u8 bdf_ext[]; 160 } __packed; 161 162 #define HEHANDLE_CAP_PHYINFO_SIZE 3 163 #define HECAP_PHYINFO_SIZE 9 164 #define HECAP_MACINFO_SIZE 5 165 #define HECAP_TXRX_MCS_NSS_SIZE 2 166 #define HECAP_PPET16_PPET8_MAX_SIZE 25 167 168 #define HE_PPET16_PPET8_SIZE 8 169 170 /* 802.11ax PPE (PPDU packet Extension) threshold */ 171 struct he_ppe_threshold { 172 u32 numss_m1; 173 u32 ru_mask; 174 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 175 }; 176 177 struct ath12k_he { 178 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 179 u32 hecap_rxmcsnssmap; 180 u32 hecap_txmcsnssmap; 181 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 182 struct he_ppe_threshold hecap_ppet; 183 u32 heop_param; 184 }; 185 186 enum { 187 WMI_HOST_TP_SCALE_MAX = 0, 188 WMI_HOST_TP_SCALE_50 = 1, 189 WMI_HOST_TP_SCALE_25 = 2, 190 WMI_HOST_TP_SCALE_12 = 3, 191 WMI_HOST_TP_SCALE_MIN = 4, 192 WMI_HOST_TP_SCALE_SIZE = 5, 193 }; 194 195 enum ath12k_scan_state { 196 ATH12K_SCAN_IDLE, 197 ATH12K_SCAN_STARTING, 198 ATH12K_SCAN_RUNNING, 199 ATH12K_SCAN_ABORTING, 200 }; 201 202 enum ath12k_dev_flags { 203 ATH12K_CAC_RUNNING, 204 ATH12K_FLAG_CRASH_FLUSH, 205 ATH12K_FLAG_RAW_MODE, 206 ATH12K_FLAG_HW_CRYPTO_DISABLED, 207 ATH12K_FLAG_RECOVERY, 208 ATH12K_FLAG_UNREGISTERING, 209 ATH12K_FLAG_REGISTERED, 210 ATH12K_FLAG_QMI_FAIL, 211 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 212 ATH12K_FLAG_CE_IRQ_ENABLED, 213 ATH12K_FLAG_EXT_IRQ_ENABLED, 214 }; 215 216 struct ath12k_tx_conf { 217 bool changed; 218 u16 ac; 219 struct ieee80211_tx_queue_params tx_queue_params; 220 }; 221 222 struct ath12k_key_conf { 223 bool changed; 224 enum set_key_cmd cmd; 225 struct ieee80211_key_conf *key; 226 }; 227 228 struct ath12k_vif_cache { 229 struct ath12k_tx_conf tx_conf; 230 struct ath12k_key_conf key_conf; 231 u32 bss_conf_changed; 232 }; 233 234 struct ath12k_rekey_data { 235 u8 kck[NL80211_KCK_LEN]; 236 u8 kek[NL80211_KCK_LEN]; 237 u64 replay_ctr; 238 bool enable_offload; 239 }; 240 241 struct ath12k_vif { 242 u32 vdev_id; 243 enum wmi_vdev_type vdev_type; 244 enum wmi_vdev_subtype vdev_subtype; 245 u32 beacon_interval; 246 u32 dtim_period; 247 u16 ast_hash; 248 u16 ast_idx; 249 u16 tcl_metadata; 250 u8 hal_addr_search_flags; 251 u8 search_type; 252 253 struct ath12k *ar; 254 struct ieee80211_vif *vif; 255 256 int bank_id; 257 u8 vdev_id_check_en; 258 259 struct wmi_wmm_params_all_arg wmm_params; 260 struct list_head list; 261 union { 262 struct { 263 u32 uapsd; 264 } sta; 265 struct { 266 /* 127 stations; wmi limit */ 267 u8 tim_bitmap[16]; 268 u8 tim_len; 269 u32 ssid_len; 270 u8 ssid[IEEE80211_MAX_SSID_LEN]; 271 bool hidden_ssid; 272 /* P2P_IE with NoA attribute for P2P_GO case */ 273 u32 noa_len; 274 u8 *noa_data; 275 } ap; 276 } u; 277 278 bool is_created; 279 bool is_started; 280 bool is_up; 281 u32 aid; 282 u8 bssid[ETH_ALEN]; 283 struct cfg80211_bitrate_mask bitrate_mask; 284 struct delayed_work connection_loss_work; 285 int num_legacy_stations; 286 int rtscts_prot_mode; 287 int txpower; 288 bool rsnie_present; 289 bool wpaie_present; 290 u32 key_cipher; 291 u8 tx_encap_type; 292 u8 vdev_stats_id; 293 u32 punct_bitmap; 294 bool ps; 295 struct ath12k_vif_cache *cache; 296 struct ath12k_rekey_data rekey_data; 297 298 /* Must be last - ends in a flexible-array member. 299 * 300 * FIXME: Driver should not copy struct ieee80211_chanctx_conf, 301 * especially because it has a flexible array. Find a better way. 302 */ 303 struct ieee80211_chanctx_conf chanctx; 304 }; 305 306 struct ath12k_vif_iter { 307 u32 vdev_id; 308 struct ath12k *ar; 309 struct ath12k_vif *arvif; 310 }; 311 312 #define HAL_AST_IDX_INVALID 0xFFFF 313 #define HAL_RX_MAX_MCS 12 314 #define HAL_RX_MAX_MCS_HT 31 315 #define HAL_RX_MAX_MCS_VHT 9 316 #define HAL_RX_MAX_MCS_HE 11 317 #define HAL_RX_MAX_NSS 8 318 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 319 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 320 #define ATH12K_RX_RATE_TABLE_NUM 320 321 322 struct ath12k_rx_peer_rate_stats { 323 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 324 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 325 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 326 u64 nss_count[HAL_RX_MAX_NSS]; 327 u64 bw_count[HAL_RX_BW_MAX]; 328 u64 gi_count[HAL_RX_GI_MAX]; 329 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 330 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 331 }; 332 333 struct ath12k_rx_peer_stats { 334 u64 num_msdu; 335 u64 num_mpdu_fcs_ok; 336 u64 num_mpdu_fcs_err; 337 u64 tcp_msdu_count; 338 u64 udp_msdu_count; 339 u64 other_msdu_count; 340 u64 ampdu_msdu_count; 341 u64 non_ampdu_msdu_count; 342 u64 stbc_count; 343 u64 beamformed_count; 344 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 345 u64 nss_count[HAL_RX_MAX_NSS]; 346 u64 bw_count[HAL_RX_BW_MAX]; 347 u64 gi_count[HAL_RX_GI_MAX]; 348 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 349 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 350 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 351 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 352 u64 rx_duration; 353 u64 dcm_count; 354 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 355 struct ath12k_rx_peer_rate_stats pkt_stats; 356 struct ath12k_rx_peer_rate_stats byte_stats; 357 }; 358 359 #define ATH12K_HE_MCS_NUM 12 360 #define ATH12K_VHT_MCS_NUM 10 361 #define ATH12K_BW_NUM 5 362 #define ATH12K_NSS_NUM 4 363 #define ATH12K_LEGACY_NUM 12 364 #define ATH12K_GI_NUM 4 365 #define ATH12K_HT_MCS_NUM 32 366 367 enum ath12k_pkt_rx_err { 368 ATH12K_PKT_RX_ERR_FCS, 369 ATH12K_PKT_RX_ERR_TKIP, 370 ATH12K_PKT_RX_ERR_CRYPT, 371 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 372 ATH12K_PKT_RX_ERR_MAX, 373 }; 374 375 enum ath12k_ampdu_subfrm_num { 376 ATH12K_AMPDU_SUBFRM_NUM_10, 377 ATH12K_AMPDU_SUBFRM_NUM_20, 378 ATH12K_AMPDU_SUBFRM_NUM_30, 379 ATH12K_AMPDU_SUBFRM_NUM_40, 380 ATH12K_AMPDU_SUBFRM_NUM_50, 381 ATH12K_AMPDU_SUBFRM_NUM_60, 382 ATH12K_AMPDU_SUBFRM_NUM_MORE, 383 ATH12K_AMPDU_SUBFRM_NUM_MAX, 384 }; 385 386 enum ath12k_amsdu_subfrm_num { 387 ATH12K_AMSDU_SUBFRM_NUM_1, 388 ATH12K_AMSDU_SUBFRM_NUM_2, 389 ATH12K_AMSDU_SUBFRM_NUM_3, 390 ATH12K_AMSDU_SUBFRM_NUM_4, 391 ATH12K_AMSDU_SUBFRM_NUM_MORE, 392 ATH12K_AMSDU_SUBFRM_NUM_MAX, 393 }; 394 395 enum ath12k_counter_type { 396 ATH12K_COUNTER_TYPE_BYTES, 397 ATH12K_COUNTER_TYPE_PKTS, 398 ATH12K_COUNTER_TYPE_MAX, 399 }; 400 401 enum ath12k_stats_type { 402 ATH12K_STATS_TYPE_SUCC, 403 ATH12K_STATS_TYPE_FAIL, 404 ATH12K_STATS_TYPE_RETRY, 405 ATH12K_STATS_TYPE_AMPDU, 406 ATH12K_STATS_TYPE_MAX, 407 }; 408 409 struct ath12k_htt_data_stats { 410 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 411 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 412 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 413 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 414 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 415 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 416 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 417 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 418 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 419 }; 420 421 struct ath12k_htt_tx_stats { 422 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 423 u64 tx_duration; 424 u64 ba_fails; 425 u64 ack_fails; 426 u16 ru_start; 427 u16 ru_tones; 428 u32 mu_group[MAX_MU_GROUP_ID]; 429 }; 430 431 struct ath12k_per_ppdu_tx_stats { 432 u16 succ_pkts; 433 u16 failed_pkts; 434 u16 retry_pkts; 435 u32 succ_bytes; 436 u32 failed_bytes; 437 u32 retry_bytes; 438 }; 439 440 struct ath12k_wbm_tx_stats { 441 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 442 }; 443 444 struct ath12k_sta { 445 struct ath12k_vif *arvif; 446 447 /* the following are protected by ar->data_lock */ 448 u32 changed; /* IEEE80211_RC_* */ 449 u32 bw; 450 u32 nss; 451 u32 smps; 452 enum hal_pn_type pn_type; 453 454 struct work_struct update_wk; 455 struct rate_info txrate; 456 struct rate_info last_txrate; 457 u64 rx_duration; 458 u64 tx_duration; 459 u8 rssi_comb; 460 struct ath12k_rx_peer_stats *rx_stats; 461 struct ath12k_wbm_tx_stats *wbm_tx_stats; 462 u32 bw_prev; 463 }; 464 465 #define ATH12K_MIN_5G_FREQ 4150 466 #define ATH12K_MIN_6G_FREQ 5925 467 #define ATH12K_MAX_6G_FREQ 7115 468 #define ATH12K_NUM_CHANS 101 469 #define ATH12K_MAX_5G_CHAN 173 470 471 enum ath12k_hw_state { 472 ATH12K_HW_STATE_OFF, 473 ATH12K_HW_STATE_ON, 474 ATH12K_HW_STATE_RESTARTING, 475 ATH12K_HW_STATE_RESTARTED, 476 ATH12K_HW_STATE_WEDGED, 477 /* Add other states as required */ 478 }; 479 480 /* Antenna noise floor */ 481 #define ATH12K_DEFAULT_NOISE_FLOOR -95 482 483 struct ath12k_fw_stats { 484 u32 pdev_id; 485 u32 stats_id; 486 struct list_head pdevs; 487 struct list_head vdevs; 488 struct list_head bcn; 489 }; 490 491 struct ath12k_dbg_htt_stats { 492 enum ath12k_dbg_htt_ext_stats_type type; 493 u32 cfg_param[4]; 494 u8 reset; 495 struct debug_htt_stats_req *stats_req; 496 }; 497 498 struct ath12k_debug { 499 struct dentry *debugfs_pdev; 500 struct dentry *debugfs_pdev_symlink; 501 struct ath12k_dbg_htt_stats htt_stats; 502 }; 503 504 struct ath12k_per_peer_tx_stats { 505 u32 succ_bytes; 506 u32 retry_bytes; 507 u32 failed_bytes; 508 u32 duration; 509 u16 succ_pkts; 510 u16 retry_pkts; 511 u16 failed_pkts; 512 u16 ru_start; 513 u16 ru_tones; 514 u8 ba_fails; 515 u8 ppdu_type; 516 u32 mu_grpid; 517 u32 mu_pos; 518 bool is_ampdu; 519 }; 520 521 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 522 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 523 524 struct ath12k { 525 struct ath12k_base *ab; 526 struct ath12k_pdev *pdev; 527 struct ath12k_hw *ah; 528 struct ath12k_wmi_pdev *wmi; 529 struct ath12k_pdev_dp dp; 530 u8 mac_addr[ETH_ALEN]; 531 u32 ht_cap_info; 532 u32 vht_cap_info; 533 struct ath12k_he ar_he; 534 bool supports_6ghz; 535 struct { 536 struct completion started; 537 struct completion completed; 538 struct completion on_channel; 539 struct delayed_work timeout; 540 enum ath12k_scan_state state; 541 bool is_roc; 542 int vdev_id; 543 int roc_freq; 544 bool roc_notify; 545 } scan; 546 547 struct { 548 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 549 struct ieee80211_sband_iftype_data 550 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 551 } mac; 552 553 unsigned long dev_flags; 554 unsigned int filter_flags; 555 u32 min_tx_power; 556 u32 max_tx_power; 557 u32 txpower_limit_2g; 558 u32 txpower_limit_5g; 559 u32 txpower_scale; 560 u32 power_scale; 561 u32 chan_tx_pwr; 562 u32 num_stations; 563 u32 max_num_stations; 564 bool monitor_present; 565 /* To synchronize concurrent synchronous mac80211 callback operations, 566 * concurrent debugfs configuration and concurrent FW statistics events. 567 */ 568 struct mutex conf_mutex; 569 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 570 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 571 * channel context data, survey info, test mode data. 572 */ 573 spinlock_t data_lock; 574 575 struct list_head arvifs; 576 /* should never be NULL; needed for regular htt rx */ 577 struct ieee80211_channel *rx_channel; 578 579 /* valid during scan; needed for mgmt rx during scan */ 580 struct ieee80211_channel *scan_channel; 581 582 u8 cfg_tx_chainmask; 583 u8 cfg_rx_chainmask; 584 u8 num_rx_chains; 585 u8 num_tx_chains; 586 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 587 u8 pdev_idx; 588 u8 lmac_id; 589 u8 hw_link_id; 590 591 struct completion peer_assoc_done; 592 struct completion peer_delete_done; 593 594 int install_key_status; 595 struct completion install_key_done; 596 597 int last_wmi_vdev_start_status; 598 struct completion vdev_setup_done; 599 struct completion vdev_delete_done; 600 601 int num_peers; 602 int max_num_peers; 603 u32 num_started_vdevs; 604 u32 num_created_vdevs; 605 unsigned long long allocated_vdev_map; 606 607 struct idr txmgmt_idr; 608 /* protects txmgmt_idr data */ 609 spinlock_t txmgmt_idr_lock; 610 atomic_t num_pending_mgmt_tx; 611 wait_queue_head_t txmgmt_empty_waitq; 612 613 /* cycle count is reported twice for each visited channel during scan. 614 * access protected by data_lock 615 */ 616 u32 survey_last_rx_clear_count; 617 u32 survey_last_cycle_count; 618 619 /* Channel info events are expected to come in pairs without and with 620 * COMPLETE flag set respectively for each channel visit during scan. 621 * 622 * However there are deviations from this rule. This flag is used to 623 * avoid reporting garbage data. 624 */ 625 bool ch_info_can_report_survey; 626 struct survey_info survey[ATH12K_NUM_CHANS]; 627 struct completion bss_survey_done; 628 629 struct work_struct regd_update_work; 630 631 struct work_struct wmi_mgmt_tx_work; 632 struct sk_buff_head wmi_mgmt_tx_queue; 633 634 struct ath12k_wow wow; 635 struct completion target_suspend; 636 bool target_suspend_ack; 637 struct ath12k_per_peer_tx_stats peer_tx_stats; 638 struct list_head ppdu_stats_info; 639 u32 ppdu_stat_list_depth; 640 641 struct ath12k_per_peer_tx_stats cached_stats; 642 u32 last_ppdu_id; 643 u32 cached_ppdu_id; 644 #ifdef CONFIG_ATH12K_DEBUGFS 645 struct ath12k_debug debug; 646 #endif 647 648 bool dfs_block_radar_events; 649 bool monitor_conf_enabled; 650 bool monitor_vdev_created; 651 bool monitor_started; 652 int monitor_vdev_id; 653 654 u32 freq_low; 655 u32 freq_high; 656 657 bool nlo_enabled; 658 }; 659 660 struct ath12k_hw { 661 struct ieee80211_hw *hw; 662 /* Protect the write operation of the hardware state ath12k_hw::state 663 * between hardware start<=>reconfigure<=>stop transitions. 664 */ 665 struct mutex hw_mutex; 666 enum ath12k_hw_state state; 667 bool regd_updated; 668 bool use_6ghz_regd; 669 u8 num_radio; 670 671 /* Keep last */ 672 struct ath12k radio[] __aligned(sizeof(void *)); 673 }; 674 675 struct ath12k_band_cap { 676 u32 phy_id; 677 u32 max_bw_supported; 678 u32 ht_cap_info; 679 u32 he_cap_info[2]; 680 u32 he_mcs; 681 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 682 struct ath12k_wmi_ppe_threshold_arg he_ppet; 683 u16 he_6ghz_capa; 684 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 685 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 686 u32 eht_mcs_20_only; 687 u32 eht_mcs_80; 688 u32 eht_mcs_160; 689 u32 eht_mcs_320; 690 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 691 u32 eht_cap_info_internal; 692 }; 693 694 struct ath12k_pdev_cap { 695 u32 supported_bands; 696 u32 ampdu_density; 697 u32 vht_cap; 698 u32 vht_mcs; 699 u32 he_mcs; 700 u32 tx_chain_mask; 701 u32 rx_chain_mask; 702 u32 tx_chain_mask_shift; 703 u32 rx_chain_mask_shift; 704 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 705 }; 706 707 struct mlo_timestamp { 708 u32 info; 709 u32 sync_timestamp_lo_us; 710 u32 sync_timestamp_hi_us; 711 u32 mlo_offset_lo; 712 u32 mlo_offset_hi; 713 u32 mlo_offset_clks; 714 u32 mlo_comp_clks; 715 u32 mlo_comp_timer; 716 }; 717 718 struct ath12k_pdev { 719 struct ath12k *ar; 720 u32 pdev_id; 721 u32 hw_link_id; 722 struct ath12k_pdev_cap cap; 723 u8 mac_addr[ETH_ALEN]; 724 struct mlo_timestamp timestamp; 725 }; 726 727 struct ath12k_fw_pdev { 728 u32 pdev_id; 729 u32 phy_id; 730 u32 supported_bands; 731 }; 732 733 struct ath12k_board_data { 734 const struct firmware *fw; 735 const void *data; 736 size_t len; 737 }; 738 739 struct ath12k_soc_dp_tx_err_stats { 740 /* TCL Ring Descriptor unavailable */ 741 u32 desc_na[DP_TCL_NUM_RING_MAX]; 742 /* Other failures during dp_tx due to mem allocation failure 743 * idr unavailable etc. 744 */ 745 atomic_t misc_fail; 746 }; 747 748 struct ath12k_soc_dp_stats { 749 u32 err_ring_pkts; 750 u32 invalid_rbm; 751 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 752 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 753 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 754 struct ath12k_soc_dp_tx_err_stats tx_err; 755 }; 756 757 /** 758 * enum ath12k_link_capable_flags - link capable flags 759 * 760 * Single/Multi link capability information 761 * 762 * @ATH12K_INTRA_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 763 * the links (radios) present within a device. 764 * @ATH12K_INTER_DEVICE_MLO_SUPPORT: SLO/MLO form between the radio, where all 765 * the links (radios) present across the devices. 766 */ 767 enum ath12k_link_capable_flags { 768 ATH12K_INTRA_DEVICE_MLO_SUPPORT = BIT(0), 769 ATH12K_INTER_DEVICE_MLO_SUPPORT = BIT(1), 770 }; 771 772 /* Master structure to hold the hw data which may be used in core module */ 773 struct ath12k_base { 774 enum ath12k_hw_rev hw_rev; 775 struct platform_device *pdev; 776 struct device *dev; 777 struct ath12k_qmi qmi; 778 struct ath12k_wmi_base wmi_ab; 779 struct completion fw_ready; 780 u8 device_id; 781 int num_radios; 782 /* HW channel counters frequency value in hertz common to all MACs */ 783 u32 cc_freq_hz; 784 785 struct ath12k_htc htc; 786 787 struct ath12k_dp dp; 788 789 void __iomem *mem; 790 unsigned long mem_len; 791 792 struct { 793 enum ath12k_bus bus; 794 const struct ath12k_hif_ops *ops; 795 } hif; 796 797 struct { 798 struct completion wakeup_completed; 799 u32 wmi_conf_rx_decap_mode; 800 } wow; 801 802 struct ath12k_ce ce; 803 struct timer_list rx_replenish_retry; 804 struct ath12k_hal hal; 805 /* To synchronize core_start/core_stop */ 806 struct mutex core_lock; 807 /* Protects data like peers */ 808 spinlock_t base_lock; 809 810 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 811 * 812 * Firmware maintains data for all bands but advertises a single 813 * phy to the host which is stored as a single element in this 814 * array. 815 * 816 * Other devices: 817 * 818 * This array will contain as many elements as the number of 819 * radios. 820 */ 821 struct ath12k_pdev pdevs[MAX_RADIOS]; 822 823 /* struct ath12k_hw_params::single_pdev_only devices use this to 824 * store phy specific data 825 */ 826 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 827 u8 fw_pdev_count; 828 829 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 830 831 /* Holds information of wiphy (hw) registration. 832 * 833 * In Multi/Single Link Operation case, all pdevs are registered as 834 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is 835 * registered as separate wiphys. 836 */ 837 struct ath12k_hw *ah[MAX_RADIOS]; 838 u8 num_hw; 839 840 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 841 unsigned long long free_vdev_map; 842 unsigned long long free_vdev_stats_id_map; 843 struct list_head peers; 844 wait_queue_head_t peer_mapping_wq; 845 u8 mac_addr[ETH_ALEN]; 846 bool wmi_ready; 847 u32 wlan_init_status; 848 int irq_num[ATH12K_IRQ_NUM_MAX]; 849 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 850 struct napi_struct *napi; 851 struct ath12k_wmi_target_cap_arg target_caps; 852 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 853 bool pdevs_macaddr_valid; 854 855 const struct ath12k_hw_params *hw_params; 856 857 const struct firmware *cal_file; 858 859 /* Below regd's are protected by ab->data_lock */ 860 /* This is the regd set for every radio 861 * by the firmware during initialization 862 */ 863 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 864 /* This regd is set during dynamic country setting 865 * This may or may not be used during the runtime 866 */ 867 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 868 869 /* Current DFS Regulatory */ 870 enum ath12k_dfs_region dfs_region; 871 struct ath12k_soc_dp_stats soc_stats; 872 #ifdef CONFIG_ATH12K_DEBUGFS 873 struct dentry *debugfs_soc; 874 #endif 875 876 unsigned long dev_flags; 877 struct completion driver_recovery; 878 struct workqueue_struct *workqueue; 879 struct work_struct restart_work; 880 struct workqueue_struct *workqueue_aux; 881 struct work_struct reset_work; 882 atomic_t reset_count; 883 atomic_t recovery_count; 884 bool is_reset; 885 struct completion reset_complete; 886 /* continuous recovery fail count */ 887 atomic_t fail_cont_count; 888 unsigned long reset_fail_timeout; 889 struct { 890 /* protected by data_lock */ 891 u32 fw_crash_counter; 892 } stats; 893 u32 pktlog_defs_checksum; 894 895 struct ath12k_dbring_cap *db_caps; 896 u32 num_db_cap; 897 898 struct timer_list mon_reap_timer; 899 900 struct completion htc_suspend; 901 902 u64 fw_soc_drop_count; 903 bool static_window_map; 904 905 struct work_struct rfkill_work; 906 /* true means radio is on */ 907 bool rfkill_radio_on; 908 909 struct { 910 enum ath12k_bdf_search bdf_search; 911 u32 vendor; 912 u32 device; 913 u32 subsystem_vendor; 914 u32 subsystem_device; 915 } id; 916 917 struct { 918 u32 api_version; 919 920 const struct firmware *fw; 921 const u8 *amss_data; 922 size_t amss_len; 923 const u8 *amss_dualmac_data; 924 size_t amss_dualmac_len; 925 const u8 *m3_data; 926 size_t m3_len; 927 928 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT); 929 } fw; 930 931 const struct hal_rx_ops *hal_rx_ops; 932 933 /* mlo_capable_flags denotes the single/multi link operation 934 * capabilities of the Device. 935 * 936 * See enum ath12k_link_capable_flags 937 */ 938 u8 mlo_capable_flags; 939 940 struct completion restart_completed; 941 942 #ifdef CONFIG_ACPI 943 944 struct { 945 bool started; 946 u32 func_bit; 947 bool acpi_tas_enable; 948 bool acpi_bios_sar_enable; 949 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE]; 950 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE]; 951 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE]; 952 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE]; 953 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE]; 954 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE]; 955 } acpi; 956 957 #endif /* CONFIG_ACPI */ 958 959 struct notifier_block panic_nb; 960 961 /* must be last */ 962 u8 drv_priv[] __aligned(sizeof(void *)); 963 }; 964 965 struct ath12k_pdev_map { 966 struct ath12k_base *ab; 967 u8 pdev_idx; 968 }; 969 970 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 971 int ath12k_core_pre_init(struct ath12k_base *ab); 972 int ath12k_core_init(struct ath12k_base *ath12k); 973 void ath12k_core_deinit(struct ath12k_base *ath12k); 974 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 975 enum ath12k_bus bus); 976 void ath12k_core_free(struct ath12k_base *ath12k); 977 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 978 struct ath12k_board_data *bd, 979 char *filename); 980 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 981 struct ath12k_board_data *bd); 982 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 983 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd); 984 int ath12k_core_check_dt(struct ath12k_base *ath12k); 985 int ath12k_core_check_smbios(struct ath12k_base *ab); 986 void ath12k_core_halt(struct ath12k *ar); 987 int ath12k_core_resume_early(struct ath12k_base *ab); 988 int ath12k_core_resume(struct ath12k_base *ab); 989 int ath12k_core_suspend(struct ath12k_base *ab); 990 int ath12k_core_suspend_late(struct ath12k_base *ab); 991 992 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 993 const char *filename); 994 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab); 995 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab); 996 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab); 997 ath12k_scan_state_str(enum ath12k_scan_state state)998 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 999 { 1000 switch (state) { 1001 case ATH12K_SCAN_IDLE: 1002 return "idle"; 1003 case ATH12K_SCAN_STARTING: 1004 return "starting"; 1005 case ATH12K_SCAN_RUNNING: 1006 return "running"; 1007 case ATH12K_SCAN_ABORTING: 1008 return "aborting"; 1009 } 1010 1011 return "unknown"; 1012 } 1013 ATH12K_SKB_CB(struct sk_buff * skb)1014 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 1015 { 1016 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 1017 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1018 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1019 } 1020 ATH12K_SKB_RXCB(struct sk_buff * skb)1021 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 1022 { 1023 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 1024 return (struct ath12k_skb_rxcb *)skb->cb; 1025 } 1026 ath12k_vif_to_arvif(struct ieee80211_vif * vif)1027 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 1028 { 1029 return (struct ath12k_vif *)vif->drv_priv; 1030 } 1031 ath12k_sta_to_arsta(struct ieee80211_sta * sta)1032 static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta) 1033 { 1034 return (struct ath12k_sta *)sta->drv_priv; 1035 } 1036 ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1037 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 1038 int mac_id) 1039 { 1040 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 1041 } 1042 ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1043 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 1044 const char *filename, 1045 void *buf, size_t buf_len) 1046 { 1047 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 1048 ab->hw_params->fw.dir, filename); 1049 } 1050 ath12k_bus_str(enum ath12k_bus bus)1051 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 1052 { 1053 switch (bus) { 1054 case ATH12K_BUS_PCI: 1055 return "pci"; 1056 } 1057 1058 return "unknown"; 1059 } 1060 ath12k_hw_to_ah(struct ieee80211_hw * hw)1061 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw) 1062 { 1063 return hw->priv; 1064 } 1065 ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1066 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id) 1067 { 1068 if (WARN(hw_link_id >= ah->num_radio, 1069 "bad hw link id %d, so switch to default link\n", hw_link_id)) 1070 hw_link_id = 0; 1071 1072 return &ah->radio[hw_link_id]; 1073 } 1074 ath12k_ar_to_ah(struct ath12k * ar)1075 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar) 1076 { 1077 return ar->ah; 1078 } 1079 ath12k_ar_to_hw(struct ath12k * ar)1080 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar) 1081 { 1082 return ar->ah->hw; 1083 } 1084 1085 #define for_each_ar(ah, ar, index) \ 1086 for ((index) = 0; ((index) < (ah)->num_radio && \ 1087 ((ar) = &(ah)->radio[(index)])); (index)++) 1088 #endif /* _CORE_H_ */ 1089