1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASM_X86_APIC_H 3 #define _ASM_X86_APIC_H 4 5 #include <linux/cpumask.h> 6 #include <linux/static_call.h> 7 8 #include <asm/alternative.h> 9 #include <asm/cpufeature.h> 10 #include <asm/apicdef.h> 11 #include <linux/atomic.h> 12 #include <asm/fixmap.h> 13 #include <asm/mpspec.h> 14 #include <asm/msr.h> 15 #include <asm/hardirq.h> 16 #include <asm/io.h> 17 #include <asm/posted_intr.h> 18 19 #define ARCH_APICTIMER_STOPS_ON_C3 1 20 21 /* Macros for apic_extnmi which controls external NMI masking */ 22 #define APIC_EXTNMI_BSP 0 /* Default */ 23 #define APIC_EXTNMI_ALL 1 24 #define APIC_EXTNMI_NONE 2 25 26 /* 27 * Debugging macros 28 */ 29 #define APIC_QUIET 0 30 #define APIC_VERBOSE 1 31 #define APIC_DEBUG 2 32 33 /* 34 * Define the default level of output to be very little This can be turned 35 * up by using apic=verbose for more information and apic=debug for _lots_ 36 * of information. apic_verbosity is defined in apic.c 37 */ 38 #define apic_printk(v, s, a...) \ 39 do { \ 40 if ((v) <= apic_verbosity) \ 41 printk(s, ##a); \ 42 } while (0) 43 44 #define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a) 45 #define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) 46 #define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a) 47 /* Unconditional debug prints for code which is guarded by apic_verbosity already */ 48 #define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) 49 50 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 51 extern void x86_32_probe_apic(void); 52 #else x86_32_probe_apic(void)53 static inline void x86_32_probe_apic(void) { } 54 #endif 55 56 extern u32 cpuid_to_apicid[]; 57 58 #define CPU_ACPIID_INVALID U32_MAX 59 60 #ifdef CONFIG_X86_LOCAL_APIC 61 62 extern int apic_verbosity; 63 extern int local_apic_timer_c2_ok; 64 65 extern bool apic_is_disabled; 66 extern unsigned int lapic_timer_period; 67 68 extern enum apic_intr_mode_id apic_intr_mode; 69 enum apic_intr_mode_id { 70 APIC_PIC, 71 APIC_VIRTUAL_WIRE, 72 APIC_VIRTUAL_WIRE_NO_CONFIG, 73 APIC_SYMMETRIC_IO, 74 APIC_SYMMETRIC_IO_NO_ROUTING 75 }; 76 77 /* 78 * With 82489DX we can't rely on apic feature bit 79 * retrieved via cpuid but still have to deal with 80 * such an apic chip so we assume that SMP configuration 81 * is found from MP table (64bit case uses ACPI mostly 82 * which set smp presence flag as well so we are safe 83 * to use this helper too). 84 */ apic_from_smp_config(void)85 static inline bool apic_from_smp_config(void) 86 { 87 return smp_found_config && !apic_is_disabled; 88 } 89 90 /* 91 * Basic functions accessing APICs. 92 */ 93 #ifdef CONFIG_PARAVIRT 94 #include <asm/paravirt.h> 95 #endif 96 native_apic_mem_write(u32 reg,u32 v)97 static inline void native_apic_mem_write(u32 reg, u32 v) 98 { 99 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 100 101 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 102 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 103 ASM_OUTPUT2("0" (v), "m" (*addr))); 104 } 105 native_apic_mem_read(u32 reg)106 static inline u32 native_apic_mem_read(u32 reg) 107 { 108 return readl((void __iomem *)(APIC_BASE + reg)); 109 } 110 native_apic_mem_eoi(void)111 static inline void native_apic_mem_eoi(void) 112 { 113 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 114 } 115 116 extern void native_apic_icr_write(u32 low, u32 id); 117 extern u64 native_apic_icr_read(void); 118 apic_is_x2apic_enabled(void)119 static inline bool apic_is_x2apic_enabled(void) 120 { 121 u64 msr; 122 123 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 124 return false; 125 return msr & X2APIC_ENABLE; 126 } 127 128 extern void enable_IR_x2apic(void); 129 130 extern int lapic_get_maxlvt(void); 131 extern void clear_local_APIC(void); 132 extern void disconnect_bsp_APIC(int virt_wire_setup); 133 extern void disable_local_APIC(void); 134 extern void apic_soft_disable(void); 135 extern void lapic_shutdown(void); 136 extern void sync_Arb_IDs(void); 137 extern void init_bsp_APIC(void); 138 extern void apic_intr_mode_select(void); 139 extern void apic_intr_mode_init(void); 140 extern void init_apic_mappings(void); 141 void register_lapic_address(unsigned long address); 142 extern void setup_boot_APIC_clock(void); 143 extern void setup_secondary_APIC_clock(void); 144 extern void lapic_update_tsc_freq(void); 145 146 #ifdef CONFIG_X86_64 apic_force_enable(unsigned long addr)147 static inline bool apic_force_enable(unsigned long addr) 148 { 149 return false; 150 } 151 #else 152 extern bool apic_force_enable(unsigned long addr); 153 #endif 154 155 extern void apic_ap_setup(void); 156 157 /* 158 * On 32bit this is mach-xxx local 159 */ 160 #ifdef CONFIG_X86_64 161 extern int apic_is_clustered_box(void); 162 #else apic_is_clustered_box(void)163 static inline int apic_is_clustered_box(void) 164 { 165 return 0; 166 } 167 #endif 168 169 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 170 extern void lapic_assign_system_vectors(void); 171 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 172 extern void lapic_update_legacy_vectors(void); 173 extern void lapic_online(void); 174 extern void lapic_offline(void); 175 extern bool apic_needs_pit(void); 176 177 extern void apic_send_IPI_allbutself(unsigned int vector); 178 179 extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); 180 extern void topology_register_boot_apic(u32 apic_id); 181 extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); 182 extern void topology_hotunplug_apic(unsigned int cpu); 183 extern void topology_apply_cmdline_limits_early(void); 184 extern void topology_init_possible_cpus(void); 185 extern void topology_reset_possible_cpus_up(void); 186 187 #else /* !CONFIG_X86_LOCAL_APIC */ lapic_shutdown(void)188 static inline void lapic_shutdown(void) { } 189 #define local_apic_timer_c2_ok 1 init_apic_mappings(void)190 static inline void init_apic_mappings(void) { } disable_local_APIC(void)191 static inline void disable_local_APIC(void) { } 192 # define setup_boot_APIC_clock x86_init_noop 193 # define setup_secondary_APIC_clock x86_init_noop lapic_update_tsc_freq(void)194 static inline void lapic_update_tsc_freq(void) { } init_bsp_APIC(void)195 static inline void init_bsp_APIC(void) { } apic_intr_mode_select(void)196 static inline void apic_intr_mode_select(void) { } apic_intr_mode_init(void)197 static inline void apic_intr_mode_init(void) { } lapic_assign_system_vectors(void)198 static inline void lapic_assign_system_vectors(void) { } lapic_assign_legacy_vector(unsigned int i,bool r)199 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } apic_needs_pit(void)200 static inline bool apic_needs_pit(void) { return true; } topology_apply_cmdline_limits_early(void)201 static inline void topology_apply_cmdline_limits_early(void) { } topology_init_possible_cpus(void)202 static inline void topology_init_possible_cpus(void) { } 203 #endif /* !CONFIG_X86_LOCAL_APIC */ 204 205 #ifdef CONFIG_X86_X2APIC native_apic_msr_write(u32 reg,u32 v)206 static inline void native_apic_msr_write(u32 reg, u32 v) 207 { 208 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 209 reg == APIC_LVR) 210 return; 211 212 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 213 } 214 native_apic_msr_eoi(void)215 static inline void native_apic_msr_eoi(void) 216 { 217 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 218 } 219 native_apic_msr_read(u32 reg)220 static inline u32 native_apic_msr_read(u32 reg) 221 { 222 u64 msr; 223 224 if (reg == APIC_DFR) 225 return -1; 226 227 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 228 return (u32)msr; 229 } 230 native_x2apic_icr_write(u32 low,u32 id)231 static inline void native_x2apic_icr_write(u32 low, u32 id) 232 { 233 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 234 } 235 native_x2apic_icr_read(void)236 static inline u64 native_x2apic_icr_read(void) 237 { 238 unsigned long val; 239 240 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 241 return val; 242 } 243 244 extern int x2apic_mode; 245 extern int x2apic_phys; 246 extern void __init x2apic_set_max_apicid(u32 apicid); 247 extern void x2apic_setup(void); x2apic_enabled(void)248 static inline int x2apic_enabled(void) 249 { 250 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 251 } 252 253 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 254 #else /* !CONFIG_X86_X2APIC */ x2apic_setup(void)255 static inline void x2apic_setup(void) { } x2apic_enabled(void)256 static inline int x2apic_enabled(void) { return 0; } native_apic_msr_read(u32 reg)257 static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 258 #define x2apic_mode (0) 259 #define x2apic_supported() (0) 260 #endif /* !CONFIG_X86_X2APIC */ 261 extern void __init check_x2apic(void); 262 263 struct irq_data; 264 265 /* 266 * Copyright 2004 James Cleverdon, IBM. 267 * 268 * Generic APIC sub-arch data struct. 269 * 270 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 271 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 272 * James Cleverdon. 273 */ 274 struct apic { 275 /* Hotpath functions first */ 276 void (*eoi)(void); 277 void (*native_eoi)(void); 278 void (*write)(u32 reg, u32 v); 279 u32 (*read)(u32 reg); 280 281 /* IPI related functions */ 282 void (*wait_icr_idle)(void); 283 u32 (*safe_wait_icr_idle)(void); 284 285 void (*send_IPI)(int cpu, int vector); 286 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 287 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 288 void (*send_IPI_allbutself)(int vector); 289 void (*send_IPI_all)(int vector); 290 void (*send_IPI_self)(int vector); 291 292 u32 disable_esr : 1, 293 dest_mode_logical : 1, 294 x2apic_set_max_apicid : 1, 295 nmi_to_offline_cpu : 1; 296 297 u32 (*calc_dest_apicid)(unsigned int cpu); 298 299 /* ICR related functions */ 300 u64 (*icr_read)(void); 301 void (*icr_write)(u32 low, u32 high); 302 303 /* The limit of the APIC ID space. */ 304 u32 max_apic_id; 305 306 /* Probe, setup and smpboot functions */ 307 int (*probe)(void); 308 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 309 310 void (*init_apic_ldr)(void); 311 u32 (*cpu_present_to_apicid)(int mps_cpu); 312 313 u32 (*get_apic_id)(u32 id); 314 315 /* wakeup_secondary_cpu */ 316 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 317 /* wakeup secondary CPU using 64-bit wakeup point */ 318 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 319 320 char *name; 321 }; 322 323 struct apic_override { 324 void (*eoi)(void); 325 void (*native_eoi)(void); 326 void (*write)(u32 reg, u32 v); 327 u32 (*read)(u32 reg); 328 void (*send_IPI)(int cpu, int vector); 329 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 330 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 331 void (*send_IPI_allbutself)(int vector); 332 void (*send_IPI_all)(int vector); 333 void (*send_IPI_self)(int vector); 334 u64 (*icr_read)(void); 335 void (*icr_write)(u32 low, u32 high); 336 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 337 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 338 }; 339 340 /* 341 * Pointer to the local APIC driver in use on this system (there's 342 * always just one such driver in use - the kernel decides via an 343 * early probing process which one it picks - and then sticks to it): 344 */ 345 extern struct apic *apic; 346 347 /* 348 * APIC drivers are probed based on how they are listed in the .apicdrivers 349 * section. So the order is important and enforced by the ordering 350 * of different apic driver files in the Makefile. 351 */ 352 #define apic_driver(sym) \ 353 static const struct apic *__apicdrivers_##sym __used \ 354 __aligned(sizeof(struct apic *)) \ 355 __section(".apicdrivers") = { &sym } 356 357 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 358 359 /* 360 * APIC functionality to boot other CPUs - only used on SMP: 361 */ 362 #ifdef CONFIG_SMP 363 extern int lapic_can_unplug_cpu(void); 364 #endif 365 366 #ifdef CONFIG_X86_LOCAL_APIC 367 extern struct apic_override __x86_apic_override; 368 369 void __init apic_setup_apic_calls(void); 370 void __init apic_install_driver(struct apic *driver); 371 372 #define apic_update_callback(_callback, _fn) { \ 373 __x86_apic_override._callback = _fn; \ 374 apic->_callback = _fn; \ 375 static_call_update(apic_call_##_callback, _fn); \ 376 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ 377 } 378 379 #define DECLARE_APIC_CALL(__cb) \ 380 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) 381 382 DECLARE_APIC_CALL(eoi); 383 DECLARE_APIC_CALL(native_eoi); 384 DECLARE_APIC_CALL(icr_read); 385 DECLARE_APIC_CALL(icr_write); 386 DECLARE_APIC_CALL(read); 387 DECLARE_APIC_CALL(send_IPI); 388 DECLARE_APIC_CALL(send_IPI_mask); 389 DECLARE_APIC_CALL(send_IPI_mask_allbutself); 390 DECLARE_APIC_CALL(send_IPI_allbutself); 391 DECLARE_APIC_CALL(send_IPI_all); 392 DECLARE_APIC_CALL(send_IPI_self); 393 DECLARE_APIC_CALL(wait_icr_idle); 394 DECLARE_APIC_CALL(wakeup_secondary_cpu); 395 DECLARE_APIC_CALL(wakeup_secondary_cpu_64); 396 DECLARE_APIC_CALL(write); 397 apic_read(u32 reg)398 static __always_inline u32 apic_read(u32 reg) 399 { 400 return static_call(apic_call_read)(reg); 401 } 402 apic_write(u32 reg,u32 val)403 static __always_inline void apic_write(u32 reg, u32 val) 404 { 405 static_call(apic_call_write)(reg, val); 406 } 407 apic_eoi(void)408 static __always_inline void apic_eoi(void) 409 { 410 static_call(apic_call_eoi)(); 411 } 412 apic_native_eoi(void)413 static __always_inline void apic_native_eoi(void) 414 { 415 static_call(apic_call_native_eoi)(); 416 } 417 apic_icr_read(void)418 static __always_inline u64 apic_icr_read(void) 419 { 420 return static_call(apic_call_icr_read)(); 421 } 422 apic_icr_write(u32 low,u32 high)423 static __always_inline void apic_icr_write(u32 low, u32 high) 424 { 425 static_call(apic_call_icr_write)(low, high); 426 } 427 __apic_send_IPI(int cpu,int vector)428 static __always_inline void __apic_send_IPI(int cpu, int vector) 429 { 430 static_call(apic_call_send_IPI)(cpu, vector); 431 } 432 __apic_send_IPI_mask(const struct cpumask * mask,int vector)433 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) 434 { 435 static_call_mod(apic_call_send_IPI_mask)(mask, vector); 436 } 437 __apic_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)438 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 439 { 440 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); 441 } 442 __apic_send_IPI_allbutself(int vector)443 static __always_inline void __apic_send_IPI_allbutself(int vector) 444 { 445 static_call(apic_call_send_IPI_allbutself)(vector); 446 } 447 __apic_send_IPI_all(int vector)448 static __always_inline void __apic_send_IPI_all(int vector) 449 { 450 static_call(apic_call_send_IPI_all)(vector); 451 } 452 __apic_send_IPI_self(int vector)453 static __always_inline void __apic_send_IPI_self(int vector) 454 { 455 static_call_mod(apic_call_send_IPI_self)(vector); 456 } 457 apic_wait_icr_idle(void)458 static __always_inline void apic_wait_icr_idle(void) 459 { 460 static_call_cond(apic_call_wait_icr_idle)(); 461 } 462 safe_apic_wait_icr_idle(void)463 static __always_inline u32 safe_apic_wait_icr_idle(void) 464 { 465 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 466 } 467 apic_id_valid(u32 apic_id)468 static __always_inline bool apic_id_valid(u32 apic_id) 469 { 470 return apic_id <= apic->max_apic_id; 471 } 472 473 #else /* CONFIG_X86_LOCAL_APIC */ 474 apic_read(u32 reg)475 static inline u32 apic_read(u32 reg) { return 0; } apic_write(u32 reg,u32 val)476 static inline void apic_write(u32 reg, u32 val) { } apic_eoi(void)477 static inline void apic_eoi(void) { } apic_icr_read(void)478 static inline u64 apic_icr_read(void) { return 0; } apic_icr_write(u32 low,u32 high)479 static inline void apic_icr_write(u32 low, u32 high) { } apic_wait_icr_idle(void)480 static inline void apic_wait_icr_idle(void) { } safe_apic_wait_icr_idle(void)481 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } apic_native_eoi(void)482 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } apic_setup_apic_calls(void)483 static inline void apic_setup_apic_calls(void) { } 484 485 #define apic_update_callback(_callback, _fn) do { } while (0) 486 487 #endif /* CONFIG_X86_LOCAL_APIC */ 488 489 extern void apic_ack_irq(struct irq_data *data); 490 lapic_vector_set_in_irr(unsigned int vector)491 static inline bool lapic_vector_set_in_irr(unsigned int vector) 492 { 493 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 494 495 return !!(irr & (1U << (vector % 32))); 496 } 497 is_vector_pending(unsigned int vector)498 static inline bool is_vector_pending(unsigned int vector) 499 { 500 return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector); 501 } 502 503 /* 504 * Warm reset vector position: 505 */ 506 #define TRAMPOLINE_PHYS_LOW 0x467 507 #define TRAMPOLINE_PHYS_HIGH 0x469 508 509 #ifdef CONFIG_X86_LOCAL_APIC 510 511 #include <asm/smp.h> 512 513 extern struct apic apic_noop; 514 read_apic_id(void)515 static inline u32 read_apic_id(void) 516 { 517 u32 reg = apic_read(APIC_ID); 518 519 return apic->get_apic_id(reg); 520 } 521 522 #ifdef CONFIG_X86_64 523 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 524 extern int default_acpi_madt_oem_check(char *, char *); 525 extern void x86_64_probe_apic(void); 526 #else default_acpi_madt_oem_check(char * a,char * b)527 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } x86_64_probe_apic(void)528 static inline void x86_64_probe_apic(void) { } 529 #endif 530 531 extern u32 apic_default_calc_apicid(unsigned int cpu); 532 extern u32 apic_flat_calc_apicid(unsigned int cpu); 533 534 extern u32 default_cpu_present_to_apicid(int mps_cpu); 535 536 void apic_send_nmi_to_offline_cpu(unsigned int cpu); 537 538 #else /* CONFIG_X86_LOCAL_APIC */ 539 read_apic_id(void)540 static inline u32 read_apic_id(void) { return 0; } 541 542 #endif /* !CONFIG_X86_LOCAL_APIC */ 543 544 #ifdef CONFIG_SMP 545 void apic_smt_update(void); 546 #else apic_smt_update(void)547 static inline void apic_smt_update(void) { } 548 #endif 549 550 struct msi_msg; 551 struct irq_cfg; 552 553 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 554 bool dmar); 555 556 extern void ioapic_zap_locks(void); 557 558 #endif /* _ASM_X86_APIC_H */ 559