/*
 * Copyright (c) 2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2021,2023 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
 * above copyright notice and this permission notice appear in all
 * copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _HAL_RX_HW_DEFINES_H_
#define _HAL_RX_HW_DEFINES_H_

/* Unified 32-bit desc fields */
#define HAL_RX_USER_TLV32_TYPE_OFFSET		0x00000000
#define HAL_RX_USER_TLV32_TYPE_LSB		1
#define HAL_RX_USER_TLV32_TYPE_MASK		0x000003FE

#define HAL_RX_USER_TLV32_LEN_OFFSET		0x00000000
#define HAL_RX_USER_TLV32_LEN_LSB		10
#define HAL_RX_USER_TLV32_LEN_MASK		0x003FFC00

#define HAL_RX_USER_TLV32_USERID_OFFSET		0x00000000
#define HAL_RX_USER_TLV32_USERID_LSB		26
#define HAL_RX_USER_TLV32_USERID_MASK		0xFC000000

/* rx mpdu desc info */
#define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET		0x0
#define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_LSB		0
#define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_MASK		0x000000ff

/* reo entrance ring */
#define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET	0x1c
#define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_LSB		28
#define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_MASK	0xf0000000

#define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET		0x18
#define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB		0
#define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK		0x00000003

#define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET		0x18
#define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB		2
#define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK		0x0000007c

#define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET	0x8
#define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB	0
#define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK	0x00000007

#define HAL_SW2WBM_RELEASE_RING_BM_ACTION_OFFSET		0x8
#define HAL_SW2WBM_RELEASE_RING_BM_ACTION_LSB			3
#define HAL_SW2WBM_RELEASE_RING_BM_ACTION_MASK			0x00000038

#define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET	0x8
#define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB		6
#define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK	0x000001c0

/* REO CMD entry offsets */
#define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET	0x0
#define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB		0
#define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK		0x0000ffff

#define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET		0x00000000
#define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB			0
#define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK		0x0000000f

#define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET	0x00000000
#define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB		4
#define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK		0x000000f0

#define HAL_WBM_INTERNAL_ERROR_OFFSET		0x8
#define HAL_WBM_INTERNAL_ERROR_LSB		31
#define HAL_WBM_INTERNAL_ERROR_MASK		0x80000000

#define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET	0x8
#define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB	6
#define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK	0x000001c0

/* RX Flow search entry MACROS */
#define HAL_RX_FLOW_SEARCH_ENTRY_VALID_OFFSET			0x00000024
#define HAL_RX_FLOW_SEARCH_ENTRY_VALID_LSB			8
#define HAL_RX_FLOW_SEARCH_ENTRY_VALID_MASK			0x00000100

#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET		0x00000000
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET		0x00000004
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET		0x00000008
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET		0x0000000c
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET		0x00000010
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET		0x00000014
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET		0x00000018
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET		0x0000001c
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK		0xffffffff

#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET		0x00000020
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB			16
#define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK			0xffff0000

#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET		0x00000020
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB			0
#define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK			0x0000ffff

#define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET		0x00000024
#define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB		0
#define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK		0x000000ff

#endif /* _HAL_RX_HW_DEFINES_H_ */