Lines Matching refs:scn
292 (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
294 (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
296 (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
298 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
300 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
302 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
304 (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
306 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
308 (scn->targetdef->d_RESET_CONTROL_OFFSET)
310 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
312 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
314 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
316 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
318 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
320 (scn->targetdef->d_GPIO_BASE_ADDRESS)
322 (scn->targetdef->d_GPIO_PIN0_OFFSET)
324 (scn->targetdef->d_GPIO_PIN1_OFFSET)
326 (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
328 (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
330 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
332 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
334 (scn->targetdef->d_SI_CONFIG_I2C_LSB)
336 (scn->targetdef->d_SI_CONFIG_I2C_MASK)
338 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
340 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
342 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
344 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
346 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
348 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
350 (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
352 (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
354 (scn->targetdef->d_SI_BASE_ADDRESS)
356 (scn->targetdef->d_SI_CONFIG_OFFSET)
358 (scn->targetdef->d_SI_TX_DATA0_OFFSET)
360 (scn->targetdef->d_SI_TX_DATA1_OFFSET)
362 (scn->targetdef->d_SI_RX_DATA0_OFFSET)
364 (scn->targetdef->d_SI_RX_DATA1_OFFSET)
366 (scn->targetdef->d_SI_CS_OFFSET)
368 (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
370 (scn->targetdef->d_SI_CS_DONE_INT_MASK)
372 (scn->targetdef->d_SI_CS_START_LSB)
374 (scn->targetdef->d_SI_CS_START_MASK)
376 (scn->targetdef->d_SI_CS_RX_CNT_LSB)
378 (scn->targetdef->d_SI_CS_RX_CNT_MASK)
380 (scn->targetdef->d_SI_CS_TX_CNT_LSB)
382 (scn->targetdef->d_SI_CS_TX_CNT_MASK)
384 (scn->targetdef->d_BOARD_DATA_SZ)
386 (scn->targetdef->d_BOARD_EXT_DATA_SZ)
388 (scn->targetdef->d_MBOX_BASE_ADDRESS)
390 (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
392 (scn->targetdef->d_CPU_CLOCK_OFFSET)
394 (scn->targetdef->d_LPO_CAL_OFFSET)
396 (scn->targetdef->d_GPIO_PIN10_OFFSET)
398 (scn->targetdef->d_GPIO_PIN11_OFFSET)
400 (scn->targetdef->d_GPIO_PIN12_OFFSET)
402 (scn->targetdef->d_GPIO_PIN13_OFFSET)
404 (scn->targetdef->d_CLOCK_GPIO_OFFSET)
406 (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
408 (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
410 (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
412 (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
414 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
416 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
418 (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
420 (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
422 (scn->targetdef->d_CE0_BASE_ADDRESS)
424 (scn->targetdef->d_CE1_BASE_ADDRESS)
426 (scn->targetdef->d_FW_INDICATOR_ADDRESS)
428 (scn->targetdef->d_DRAM_BASE_ADDRESS)
430 (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
432 (scn->targetdef->d_CORE_CTRL_ADDRESS)
434 (scn->targetdef->d_CE_COUNT)
436 (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
438 (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
440 (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
442 (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
444 (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
446 (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
448 (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
450 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
452 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
454 (scn->targetdef->d_CPU_INTR_ADDRESS)
456 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
458 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
460 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
462 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
464 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
475 (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
477 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
479 (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
481 (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
483 (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
492 (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
494 (scn->targetdef->d_DST_WATERMARK_ADDRESS)
496 (scn->targetdef->d_SOC_POWER_REG_OFFSET)
501 (scn->targetdef->d_DST_WR_INDEX_ADDRESS)
503 (scn->targetdef->d_SRC_WATERMARK_ADDRESS)
505 (scn->targetdef->d_SRC_WATERMARK_LOW_MASK)
507 (scn->targetdef->d_SRC_WATERMARK_HIGH_MASK)
509 (scn->targetdef->d_DST_WATERMARK_LOW_MASK)
511 (scn->targetdef->d_DST_WATERMARK_HIGH_MASK)
513 (scn->targetdef->d_CURRENT_SRRI_ADDRESS)
515 (scn->targetdef->d_CURRENT_DRRI_ADDRESS)
517 (scn->targetdef->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
519 (scn->targetdef->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
521 (scn->targetdef->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
523 (scn->targetdef->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
525 (scn->targetdef->d_HOST_IS_ADDRESS)
527 (scn->targetdef->d_HOST_IS_COPY_COMPLETE_MASK)
529 (scn->targetdef->d_CE_WRAPPER_BASE_ADDRESS)
531 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
533 (scn->targetdef->d_HOST_IE_ADDRESS)
535 (scn->targetdef->d_HOST_IE_COPY_COMPLETE_MASK)
537 (scn->targetdef->d_SR_BA_ADDRESS)
539 (scn->targetdef->d_SR_SIZE_ADDRESS)
541 (scn->targetdef->d_CE_CTRL1_ADDRESS)
543 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_MASK)
545 (scn->targetdef->d_DR_BA_ADDRESS)
547 (scn->targetdef->d_DR_SIZE_ADDRESS)
549 (scn->targetdef->d_MISC_IE_ADDRESS)
551 (scn->targetdef->d_MISC_IS_AXI_ERR_MASK)
553 (scn->targetdef->d_MISC_IS_DST_ADDR_ERR_MASK)
555 (scn->targetdef->d_MISC_IS_SRC_LEN_ERR_MASK)
557 (scn->targetdef->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
559 (scn->targetdef->d_MISC_IS_DST_RING_OVERFLOW_MASK)
561 (scn->targetdef->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
563 (scn->targetdef->d_SRC_WATERMARK_LOW_LSB)
565 (scn->targetdef->d_SRC_WATERMARK_HIGH_LSB)
567 (scn->targetdef->d_DST_WATERMARK_LOW_LSB)
569 (scn->targetdef->d_DST_WATERMARK_HIGH_LSB)
571 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
573 (scn->targetdef->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
575 (scn->targetdef->d_CE_CTRL1_DMAX_LENGTH_LSB)
577 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
579 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
581 (scn->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
583 (scn->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
585 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
587 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
589 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
591 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
593 (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
595 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
597 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
599 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
601 (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
603 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
605 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
607 (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
609 (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
611 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
613 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
615 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
617 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
619 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
621 (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
623 (scn->targetdef->d_CE_WRAPPER_DEBUG_OFFSET)
625 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB)
627 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB)
629 (scn->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK)
631 (scn->targetdef->d_CE_DEBUG_OFFSET)
633 (scn->targetdef->d_CE_DEBUG_SEL_MSB)
635 (scn->targetdef->d_CE_DEBUG_SEL_LSB)
637 (scn->targetdef->d_CE_DEBUG_SEL_MASK)
641 (scn->targetdef->d_EFUSE_OFFSET)
643 (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
645 (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
647 (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
649 (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
651 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
653 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
655 (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
657 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
659 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
661 (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
663 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
665 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
667 (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
669 (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
671 (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
673 (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
675 (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
677 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
679 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
681 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
683 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
685 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
687 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
689 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
691 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
693 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
695 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
697 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
699 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
701 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
703 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
705 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
707 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
709 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
711 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
713 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
715 (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
717 (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
719 (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
721 (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
723 (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
725 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
727 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
729 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
731 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
733 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
735 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
737 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
739 (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
741 (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
743 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
745 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
747 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
978 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
980 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
982 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
984 (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
986 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
988 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
990 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
992 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
994 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
996 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
998 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
1000 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
1002 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
1004 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
1006 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
1008 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
1010 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
1012 (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
1014 (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
1016 (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
1018 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
1020 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
1022 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
1024 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
1026 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
1028 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
1030 (scn->hostdef->d_COUNT_DEC_ADDRESS)
1032 (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
1034 (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
1036 (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
1038 (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
1040 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
1042 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
1044 (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
1046 (scn->hostdef->d_WINDOW_DATA_ADDRESS)
1048 (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
1050 (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
1052 (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
1054 (scn->hostdef->d_RTC_STATE_ADDRESS)
1056 (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
1058 (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
1060 (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
1062 (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
1064 (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
1066 (scn->hostdef->d_RTC_STATE_V_MASK)
1068 (scn->hostdef->d_RTC_STATE_V_LSB)
1070 (scn->hostdef->d_FW_IND_EVENT_PENDING)
1072 (scn->hostdef->d_FW_IND_INITIALIZED)
1074 (scn->hostdef->d_RTC_STATE_V_ON)
1077 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
1079 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
1218 void target_register_tbl_attach(struct hif_softc *scn,
1220 void hif_register_tbl_attach(struct hif_softc *scn,