Lines Matching refs:uint32_t
26 uint32_t d_RTC_SOC_BASE_ADDRESS;
27 uint32_t d_RTC_WMAC_BASE_ADDRESS;
28 uint32_t d_SYSTEM_SLEEP_OFFSET;
29 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
30 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
31 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
32 uint32_t d_CLOCK_CONTROL_OFFSET;
33 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
34 uint32_t d_RESET_CONTROL_OFFSET;
35 uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
36 uint32_t d_RESET_CONTROL_SI0_RST_MASK;
37 uint32_t d_WLAN_RESET_CONTROL_OFFSET;
38 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
39 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
40 uint32_t d_GPIO_BASE_ADDRESS;
41 uint32_t d_GPIO_PIN0_OFFSET;
42 uint32_t d_GPIO_PIN1_OFFSET;
43 uint32_t d_GPIO_PIN0_CONFIG_MASK;
44 uint32_t d_GPIO_PIN1_CONFIG_MASK;
45 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
46 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
47 uint32_t d_SI_CONFIG_I2C_LSB;
48 uint32_t d_SI_CONFIG_I2C_MASK;
49 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
50 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
51 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
52 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
53 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
54 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
55 uint32_t d_SI_CONFIG_DIVIDER_LSB;
56 uint32_t d_SI_CONFIG_DIVIDER_MASK;
57 uint32_t d_SI_BASE_ADDRESS;
58 uint32_t d_SI_CONFIG_OFFSET;
59 uint32_t d_SI_TX_DATA0_OFFSET;
60 uint32_t d_SI_TX_DATA1_OFFSET;
61 uint32_t d_SI_RX_DATA0_OFFSET;
62 uint32_t d_SI_RX_DATA1_OFFSET;
63 uint32_t d_SI_CS_OFFSET;
64 uint32_t d_SI_CS_DONE_ERR_MASK;
65 uint32_t d_SI_CS_DONE_INT_MASK;
66 uint32_t d_SI_CS_START_LSB;
67 uint32_t d_SI_CS_START_MASK;
68 uint32_t d_SI_CS_RX_CNT_LSB;
69 uint32_t d_SI_CS_RX_CNT_MASK;
70 uint32_t d_SI_CS_TX_CNT_LSB;
71 uint32_t d_SI_CS_TX_CNT_MASK;
72 uint32_t d_BOARD_DATA_SZ;
73 uint32_t d_BOARD_EXT_DATA_SZ;
74 uint32_t d_MBOX_BASE_ADDRESS;
75 uint32_t d_LOCAL_SCRATCH_OFFSET;
76 uint32_t d_CPU_CLOCK_OFFSET;
77 uint32_t d_LPO_CAL_OFFSET;
78 uint32_t d_GPIO_PIN10_OFFSET;
79 uint32_t d_GPIO_PIN11_OFFSET;
80 uint32_t d_GPIO_PIN12_OFFSET;
81 uint32_t d_GPIO_PIN13_OFFSET;
82 uint32_t d_CLOCK_GPIO_OFFSET;
83 uint32_t d_CPU_CLOCK_STANDARD_LSB;
84 uint32_t d_CPU_CLOCK_STANDARD_MASK;
85 uint32_t d_LPO_CAL_ENABLE_LSB;
86 uint32_t d_LPO_CAL_ENABLE_MASK;
87 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
88 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
89 uint32_t d_ANALOG_INTF_BASE_ADDRESS;
90 uint32_t d_WLAN_MAC_BASE_ADDRESS;
91 uint32_t d_FW_INDICATOR_ADDRESS;
92 uint32_t d_DRAM_BASE_ADDRESS;
93 uint32_t d_SOC_CORE_BASE_ADDRESS;
94 uint32_t d_CORE_CTRL_ADDRESS;
95 uint32_t d_MSI_NUM_REQUEST;
96 uint32_t d_MSI_ASSIGN_FW;
97 uint32_t d_CORE_CTRL_CPU_INTR_MASK;
98 uint32_t d_SR_WR_INDEX_ADDRESS;
99 uint32_t d_DST_WATERMARK_ADDRESS;
102 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
103 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
104 uint32_t d_RX_MPDU_START_0_RETRY_LSB;
105 uint32_t d_RX_MPDU_START_0_RETRY_MASK;
106 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
107 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
108 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
109 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
110 uint32_t d_RX_MPDU_START_2_TID_LSB;
111 uint32_t d_RX_MPDU_START_2_TID_MASK;
112 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
113 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
114 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
115 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
116 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
117 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
118 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
119 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
120 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
121 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
122 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
123 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
124 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
125 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
126 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
127 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
128 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
129 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
130 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
131 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
132 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
133 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
134 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
138 uint32_t d_EFUSE_OFFSET;
139 uint32_t d_EFUSE_XTAL_SEL_MSB;
140 uint32_t d_EFUSE_XTAL_SEL_LSB;
141 uint32_t d_EFUSE_XTAL_SEL_MASK;
142 uint32_t d_BB_PLL_CONFIG_OFFSET;
143 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
144 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
145 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
146 uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
147 uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
148 uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
149 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
150 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
151 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
152 uint32_t d_WLAN_PLL_SETTLE_OFFSET;
153 uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
154 uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
155 uint32_t d_WLAN_PLL_SETTLE_RESET;
156 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
157 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
158 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
159 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
160 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
161 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
162 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
163 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
164 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
165 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
166 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
167 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
168 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
169 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
170 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
171 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
172 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
173 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
174 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
175 uint32_t d_WLAN_PLL_CONTROL_OFFSET;
176 uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
177 uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
178 uint32_t d_WLAN_PLL_CONTROL_RESET;
179 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
180 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
181 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
182 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
183 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
184 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
185 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
186 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
187 uint32_t d_RTC_SYNC_STATUS_OFFSET;
188 uint32_t d_SOC_CPU_CLOCK_OFFSET;
189 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
190 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
191 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
194 uint32_t d_SOC_POWER_REG_OFFSET;
195 uint32_t d_SOC_RESET_CONTROL_ADDRESS;
196 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
197 uint32_t d_CPU_INTR_ADDRESS;
198 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
199 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
200 uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;
203 uint32_t d_SOC_CHIP_ID_ADDRESS;
204 uint32_t d_SOC_CHIP_ID_VERSION_MASK;
205 uint32_t d_SOC_CHIP_ID_VERSION_LSB;
206 uint32_t d_SOC_CHIP_ID_REVISION_MASK;
207 uint32_t d_SOC_CHIP_ID_REVISION_LSB;
210 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
211 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
212 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
213 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
214 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
215 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
216 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
217 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
218 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
219 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
221 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
222 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
223 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
224 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
225 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
226 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
227 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
228 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
229 uint32_t d_WLAN_DEBUG_OUT_OFFSET;
230 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
231 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
232 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
233 uint32_t d_AMBA_DEBUG_BUS_OFFSET;
234 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
235 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
236 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
239 uint32_t d_Q6_ENABLE_REGISTER_0;
240 uint32_t d_Q6_ENABLE_REGISTER_1;
241 uint32_t d_Q6_CAUSE_REGISTER_0;
242 uint32_t d_Q6_CAUSE_REGISTER_1;
243 uint32_t d_Q6_CLEAR_REGISTER_0;
244 uint32_t d_Q6_CLEAR_REGISTER_1;
563 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
564 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
565 uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
566 uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
567 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
568 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
569 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
570 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
571 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
572 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
573 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
574 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
575 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
576 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
577 uint32_t d_INT_STATUS_ENABLE_ADDRESS;
578 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
579 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
580 uint32_t d_HOST_INT_STATUS_ADDRESS;
581 uint32_t d_CPU_INT_STATUS_ADDRESS;
582 uint32_t d_ERROR_INT_STATUS_ADDRESS;
583 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
584 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
585 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
586 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
587 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
588 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
589 uint32_t d_COUNT_DEC_ADDRESS;
590 uint32_t d_HOST_INT_STATUS_CPU_MASK;
591 uint32_t d_HOST_INT_STATUS_CPU_LSB;
592 uint32_t d_HOST_INT_STATUS_ERROR_MASK;
593 uint32_t d_HOST_INT_STATUS_ERROR_LSB;
594 uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
595 uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
596 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
597 uint32_t d_WINDOW_DATA_ADDRESS;
598 uint32_t d_WINDOW_READ_ADDR_ADDRESS;
599 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
600 uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
601 uint32_t d_RTC_STATE_ADDRESS;
602 uint32_t d_RTC_STATE_COLD_RESET_MASK;
603 uint32_t d_RTC_STATE_V_MASK;
604 uint32_t d_RTC_STATE_V_LSB;
605 uint32_t d_FW_IND_EVENT_PENDING;
606 uint32_t d_FW_IND_INITIALIZED;
607 uint32_t d_FW_IND_HELPER;
608 uint32_t d_RTC_STATE_V_ON;
610 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
611 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
613 uint32_t d_MSI_MAGIC_ADR_ADDRESS;
614 uint32_t d_MSI_MAGIC_ADDRESS;
615 uint32_t d_ENABLE_MSI;
616 uint32_t d_MUX_ID_MASK;
617 uint32_t d_TRANSACTION_ID_MASK;
618 uint32_t d_DESC_DATA_FLAG_MASK;
788 uint32_t refdiv;
789 uint32_t div;
790 uint32_t rnfrac;
791 uint32_t outdiv;
796 uint32_t refclk_hz;
797 uint32_t pll_settling_time; /* 50us */
802 uint32_t start_addr;
803 uint32_t end_addr;
809 uint32_t section_size;