Lines Matching refs:mem
229 target_enable0 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0); in hif_pci_route_adrastea_interrupt()
230 target_enable1 = hif_read32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1); in hif_pci_route_adrastea_interrupt()
231 target_cause0 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_0); in hif_pci_route_adrastea_interrupt()
232 target_cause1 = hif_read32_mb(sc, sc->mem + Q6_CAUSE_REGISTER_1); in hif_pci_route_adrastea_interrupt()
236 hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_0, 0); in hif_pci_route_adrastea_interrupt()
237 hif_write32_mb(sc, sc->mem + Q6_ENABLE_REGISTER_1, 0); in hif_pci_route_adrastea_interrupt()
270 hif_write32_mb(scn, scn->mem + in pci_dispatch_interrupt()
275 hif_read32_mb(scn, scn->mem + in pci_dispatch_interrupt()
311 host_enable = hif_read32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
313 host_cause = hif_read32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
326 hif_write32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
330 hif_write32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
337 hif_write32_mb(sc, sc->mem + 0x2f100c, in hif_pci_legacy_ce_interrupt_handler()
345 hif_read32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
369 hif_read32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
373 hif_read32_mb(sc, sc->mem + in hif_pci_legacy_ce_interrupt_handler()
377 hif_read32_mb(sc, sc->mem + 0x80008), in hif_pci_legacy_ce_interrupt_handler()
378 hif_read32_mb(sc, sc->mem + 0x8000c)); in hif_pci_legacy_ce_interrupt_handler()
380 hif_read32_mb(sc, sc->mem + 0x80010), in hif_pci_legacy_ce_interrupt_handler()
381 hif_read32_mb(sc, sc->mem + 0x80014)); in hif_pci_legacy_ce_interrupt_handler()
383 hif_read32_mb(sc, sc->mem + 0x80018), in hif_pci_legacy_ce_interrupt_handler()
384 hif_read32_mb(sc, sc->mem + 0x8001c)); in hif_pci_legacy_ce_interrupt_handler()
417 bool hif_pci_targ_is_present(struct hif_softc *scn, void *__iomem *mem) in hif_pci_targ_is_present() argument
459 A_target_id_t pci_addr = scn->mem; in hif_pci_cancel_deferred_target_sleep()
483 #define A_PCIE_LOCAL_REG_READ(sc, mem, addr) \ argument
484 hif_read32_mb(sc, (char *)(mem) + \
487 #define A_PCIE_LOCAL_REG_WRITE(sc, mem, addr, val) \ argument
488 hif_write32_mb(sc, ((char *)(mem) + \
501 static bool hif_targ_is_awake(struct hif_softc *hif_ctx, void *__iomem *mem) in hif_targ_is_awake() argument
513 static bool hif_targ_is_awake(struct hif_softc *scn, void *__iomem *mem) in hif_targ_is_awake() argument
519 val = hif_read32_mb(scn, mem + PCIE_LOCAL_BASE_ADDRESS in hif_targ_is_awake()
528 void __iomem *mem = sc->mem; in hif_pci_device_reset() local
543 if (!mem) in hif_pci_device_reset()
552 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, in hif_pci_device_reset()
555 if (hif_targ_is_awake(scn, mem)) in hif_pci_device_reset()
562 val = A_PCIE_LOCAL_REG_READ(sc, mem, SOC_GLOBAL_RESET_ADDRESS); in hif_pci_device_reset()
564 A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val); in hif_pci_device_reset()
566 if (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) & in hif_pci_device_reset()
575 A_PCIE_LOCAL_REG_WRITE(sc, mem, SOC_GLOBAL_RESET_ADDRESS, val); in hif_pci_device_reset()
578 (A_PCIE_LOCAL_REG_READ(sc, mem, RTC_STATE_ADDRESS) & in hif_pci_device_reset()
585 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, in hif_pci_device_reset()
600 void __iomem *mem = sc->mem; in hif_pci_device_warm_reset() local
610 if (!mem) in hif_pci_device_warm_reset()
619 A_PCIE_LOCAL_REG_WRITE(sc, mem, PCIE_SOC_WAKE_ADDRESS, in hif_pci_device_warm_reset()
622 if (hif_targ_is_awake(scn, mem)) in hif_pci_device_warm_reset()
631 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
637 val = hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
642 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
645 hif_write32_mb(sc, (mem + in hif_pci_device_warm_reset()
647 hif_write32_mb(sc, (mem + in hif_pci_device_warm_reset()
655 fw_indicator = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS); in hif_pci_device_warm_reset()
656 hif_write32_mb(sc, mem + FW_INDICATOR_ADDRESS, 0); in hif_pci_device_warm_reset()
661 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
667 hif_write32_mb(sc, mem + in hif_pci_device_warm_reset()
673 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
677 hif_write32_mb(sc, (mem + in hif_pci_device_warm_reset()
681 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
688 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
691 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
697 val = hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
703 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
707 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
710 hif_read32_mb(sc, mem + in hif_pci_device_warm_reset()
726 void __iomem *mem = sc->mem; in hif_check_fw_reg() local
731 val = hif_read32_mb(sc, mem + FW_INDICATOR_ADDRESS); in hif_check_fw_reg()
761 val = hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_check_soc_status()
766 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_check_soc_status()
769 hif_read32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_check_soc_status()
773 while (!hif_targ_is_awake(scn, sc->mem)) { in hif_check_soc_status()
776 hif_read32_mb(sc, sc->mem + in hif_check_soc_status()
779 hif_read32_mb(sc, sc->mem + in hif_check_soc_status()
785 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_check_soc_status()
794 hif_read32_mb(sc, sc->mem + RTC_SOC_BASE_ADDRESS + in hif_check_soc_status()
813 void __iomem *mem = sc->mem; in __hif_pci_dump_registers() local
823 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
827 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
831 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
835 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
839 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
841 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
847 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
851 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, in __hif_pci_dump_registers()
856 val = hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + in __hif_pci_dump_registers()
860 hif_write32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + in __hif_pci_dump_registers()
865 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
867 hif_read32_mb(sc, mem + CE_WRAPPER_BASE_ADDRESS + in __hif_pci_dump_registers()
875 hif_read32_mb(sc, mem + ce_base + in __hif_pci_dump_registers()
879 hif_write32_mb(sc, mem + ce_base + in __hif_pci_dump_registers()
885 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS in __hif_pci_dump_registers()
891 hif_read32_mb(sc, mem + ce_base + in __hif_pci_dump_registers()
897 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
908 val = hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
912 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
918 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
922 hif_write32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
927 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
932 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
934 hif_read32_mb(sc, mem + GPIO_BASE_ADDRESS + in __hif_pci_dump_registers()
1205 hif_write32_mb(scn, scn->mem + in soc_wake_reset()
1272 = CHIP_ID_REVISION_GET(hif_read32_mb(scn, scn->mem in hif_set_hia_extnd()
1454 host_interest_area = hif_read32_mb(scn, scn->mem + in hif_set_hia()
1464 hif_write32_mb(scn, scn->mem + 0x113014, 0); in hif_set_hia()
1843 void __iomem *mem; in hif_enable_pci_nopld() local
1913 mem = pci_iomap(pdev, BAR_NUM, 0); in hif_enable_pci_nopld()
1914 if (!mem) { in hif_enable_pci_nopld()
1920 hif_info("*****BAR is %pK", (void *)mem); in hif_enable_pci_nopld()
1922 sc->mem = mem; in hif_enable_pci_nopld()
1931 mem = mem + 0x0c000000; in hif_enable_pci_nopld()
1932 sc->mem = mem; in hif_enable_pci_nopld()
1933 hif_info("Changing PCI mem base to %pK", sc->mem); in hif_enable_pci_nopld()
1937 ol_sc->mem = mem; in hif_enable_pci_nopld()
1969 pci_iounmap(sc->pdev, sc->mem); in hif_pci_deinit_nopld()
1990 sc->mem = NULL; in hif_disable_pci()
1991 ol_sc->mem = NULL; in hif_disable_pci()
2013 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_pci_probe_tgt_wakeup()
2015 while (!hif_targ_is_awake(scn, sc->mem)) { in hif_pci_probe_tgt_wakeup()
2030 !(hif_read32_mb(sc, c->mem + in hif_pci_probe_tgt_wakeup()
2046 fw_indicator = hif_read32_mb(sc, sc->mem + FW_INDICATOR_ADDRESS); in hif_pci_probe_tgt_wakeup()
2047 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_pci_probe_tgt_wakeup()
2084 hif_write32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | in hif_pci_configure_legacy_irq()
2087 hif_read32_mb(sc, sc->mem + (SOC_CORE_BASE_ADDRESS | in hif_pci_configure_legacy_irq()
2089 hif_write32_mb(sc, sc->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_pci_configure_legacy_irq()
2099 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_pci_configure_legacy_irq()
2240 void __iomem *mem; in hif_pci_disable_bus() local
2253 hif_write32_mb(sc, sc->mem + PCIE_INTR_ENABLE_ADDRESS, 0); in hif_pci_disable_bus()
2254 hif_write32_mb(sc, sc->mem + PCIE_INTR_CLR_ADDRESS, in hif_pci_disable_bus()
2271 mem = (void __iomem *)sc->mem; in hif_pci_disable_bus()
2272 if (mem) { in hif_pci_disable_bus()
2279 scn->mem = NULL; in hif_pci_disable_bus()
2348 address = scn->mem + PCIE_LOW_POWER_INT_MASK_OFFSET; in hif_pci_config_low_power_int_register()
2626 A_target_id_t pci_addr = scn->mem; in hif_log_soc_wakeup_timeout()
2713 A_target_id_t pci_addr = scn->mem; in hif_pci_target_sleep_state_adjust()
2803 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + in hif_pci_target_sleep_state_adjust()
2805 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + in hif_pci_target_sleep_state_adjust()
2807 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + in hif_pci_target_sleep_state_adjust()
2809 hif_read32_mb(sc, sc->mem + SOC_CORE_BASE_ADDRESS + in hif_pci_target_sleep_state_adjust()
2811 hif_read32_mb(sc, sc->mem + CE_WRAPPER_BASE_ADDRESS + in hif_pci_target_sleep_state_adjust()
2824 addr = scn->mem + offset; in hif_target_read_checked()
2848 addr = scn->mem + (offset); in hif_target_write_checked()
3617 tmp = hif_read32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + in hif_trigger_timer_irq()
3622 hif_write32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + in hif_trigger_timer_irq()
3639 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | in hif_target_sync()
3643 (void)hif_read32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | in hif_target_sync()
3646 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_target_sync()
3649 while (!hif_targ_is_awake(scn, scn->mem)) in hif_target_sync()
3660 fw_ind = hif_read32_mb(scn, scn->mem + in hif_target_sync()
3666 hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS | in hif_target_sync()
3670 (void)hif_read32_mb(scn, scn->mem + in hif_target_sync()
3688 hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS + in hif_target_sync()
3699 sc->mem = info.v_addr; in hif_pci_get_soc_info_pld()
3700 sc->ce_sc.ol_sc.mem = info.v_addr; in hif_pci_get_soc_info_pld()
3940 hif_write32_mb(scn, scn->mem + in hif_pci_irq_enable()
3945 hif_read32_mb(scn, scn->mem + in hif_pci_irq_enable()
4049 hif_write32_mb(scn, scn->mem + PCIE_REG_WAKE_UMAC_OFFSET, 1); in hif_soc_wake_request()
4058 scn, scn->mem + in hif_soc_wake_request()
4092 hif_write32_mb(scn, scn->mem + PCIE_REG_WAKE_UMAC_OFFSET, 0); in hif_soc_wake_release()