Lines Matching refs:target_ce_def
26 #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
27 #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
28 #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
29 #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
30 #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
31 #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
32 #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
33 #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
102 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
104 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
106 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
108 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
109 #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
111 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
112 #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
114 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
116 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
118 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
120 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
121 #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
122 #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
123 #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
124 #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
126 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
127 #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
128 #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
129 #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
130 #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
131 #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
132 #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
133 #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
134 #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
136 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_INT_SETUP)
138 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_INT_SETUP)
139 #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
140 #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
142 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
144 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
146 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
148 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
150 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
151 #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
152 #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
153 #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
154 #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
156 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
158 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
160 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
161 #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
163 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
165 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
167 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
169 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
200 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
202 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
204 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
206 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
207 #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
208 #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
209 #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
210 #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
211 #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
212 #define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB)
213 #define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2)
214 #define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB)
215 #define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3)
216 #define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB)
217 #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
218 #define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS)
219 #define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS)
220 #define PMM_SCRATCH_BASE (scn->target_ce_def->d_PMM_SCRATCH_BASE)
419 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_MASK)
421 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_LSB)
423 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_MASK)
425 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_LSB)
427 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_MASK)
429 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_LSB)
431 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_MASK)
433 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_LSB)
446 (scn->target_ce_def->d_HOST_IE_SRC_TIMER_BATCH_MASK)
448 (scn->target_ce_def->d_HOST_IE_DST_TIMER_BATCH_MASK)
625 #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
626 #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)