Lines Matching refs:scn
26 #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
27 #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
28 #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
29 #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
30 #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
31 #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
32 #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
33 #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
35 #define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
36 #define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
37 #define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
38 #define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
39 #define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
40 #define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
41 #define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
42 #define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
43 #define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
44 #define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
45 #define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
46 #define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
47 #define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
48 #define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
49 #define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
50 #define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
51 #define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
52 #define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
53 #define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
54 #define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
55 #define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
56 #define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
57 #define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
58 #define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
59 #define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
60 #define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
61 #define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
62 #define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
63 #define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
64 #define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
65 #define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
66 #define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
67 #define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
68 #define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
70 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
72 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
74 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
76 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
78 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
80 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
82 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
84 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
86 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
88 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
90 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
92 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
94 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
96 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
102 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
104 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
106 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
108 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
109 #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
111 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
112 #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
114 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
116 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
118 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
120 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
121 #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
122 #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
123 #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
124 #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
126 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
127 #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
128 #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
129 #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
130 #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
131 #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
132 #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
133 #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
134 #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
136 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_INT_SETUP)
138 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_INT_SETUP)
139 #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
140 #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
142 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
144 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
146 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
148 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
150 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
151 #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
152 #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
153 #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
154 #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
156 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
158 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
160 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
161 #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
163 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
165 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
167 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
169 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
171 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
173 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
175 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
177 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
178 #define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
180 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
182 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
184 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
185 #define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
186 #define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
187 #define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
188 #define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
189 #define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
191 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
193 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
195 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
196 #define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
197 #define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
198 #define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
200 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
202 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
204 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
206 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
207 #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
208 #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
209 #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
210 #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
211 #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
212 #define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB)
213 #define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2)
214 #define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB)
215 #define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3)
216 #define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB)
217 #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
218 #define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS)
219 #define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS)
220 #define PMM_SCRATCH_BASE (scn->target_ce_def->d_PMM_SCRATCH_BASE)
277 uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn,
279 uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn,
295 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ argument
296 (((uint64_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr))
300 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ argument
301 (((uint32_t *)((scn)->vaddr_rri_on_ddr)) + COPY_ENGINE_ID(CE_ctrl_addr))
306 #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ argument
307 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
308 #define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ argument
309 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
313 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ argument
314 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
315 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ argument
316 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
318 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ argument
319 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
320 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ argument
321 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
325 unsigned int hif_get_src_ring_read_index(struct hif_softc *scn,
327 unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn,
330 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ argument
331 hif_get_src_ring_read_index(scn, CE_ctrl_addr)
332 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ argument
333 hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
335 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ argument
336 CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)
337 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ argument
338 CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)
341 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \ argument
342 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
343 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ argument
344 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
351 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ argument
352 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
361 #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ argument
362 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
364 #define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ argument
365 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
367 #define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ argument
368 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
370 #define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \ argument
371 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
373 #define CE_IDX_UPD_EN_DMAX_LEN_SET(scn, CE_ctrl_addr, n) \ argument
374 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
375 ((A_TARGET_READ(scn, (CE_ctrl_addr) + \
379 #define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \ argument
380 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
381 (A_TARGET_READ(scn, (CE_ctrl_addr) + \
385 #define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \ argument
386 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
387 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
390 #define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \ argument
391 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
393 #define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \ argument
394 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
396 #define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \ argument
397 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
399 #define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ argument
400 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
402 #define CE_MSI_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ argument
403 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH)
405 #define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \ argument
406 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
408 #define CE_MSI_EN_SET(scn, CE_ctrl_addr) \ argument
409 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
410 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
419 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_MASK)
421 (scn->target_ce_def->d_CE_SRC_BATCH_TIMER_THRESH_LSB)
423 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_MASK)
425 (scn->target_ce_def->d_CE_SRC_BATCH_COUNTER_THRESH_LSB)
427 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_MASK)
429 (scn->target_ce_def->d_CE_DST_BATCH_TIMER_THRESH_LSB)
431 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_MASK)
433 (scn->target_ce_def->d_CE_DST_BATCH_COUNTER_THRESH_LSB)
435 #define CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP_GET(scn, CE_ctrl_addr) \ argument
436 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_SRC_BATCH_TIMER_INT_SETUP)
437 #define CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP_GET(scn, CE_ctrl_addr) \ argument
438 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_DST_BATCH_TIMER_INT_SETUP)
440 #define CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP(scn, CE_ctrl_addr, data) \ argument
441 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_SRC_BATCH_TIMER_INT_SETUP, data)
442 #define CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP(scn, CE_ctrl_addr, data) \ argument
443 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_DST_BATCH_TIMER_INT_SETUP, data)
446 (scn->target_ce_def->d_HOST_IE_SRC_TIMER_BATCH_MASK)
448 (scn->target_ce_def->d_HOST_IE_DST_TIMER_BATCH_MASK)
450 #define CE_CHANNEL_SRC_TIMER_BATCH_INT_EN(scn, CE_ctrl_addr) \ argument
451 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
452 A_TARGET_READ(scn, \
455 #define CE_CHANNEL_DST_TIMER_BATCH_INT_EN(scn, CE_ctrl_addr) \ argument
456 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
457 A_TARGET_READ(scn, \
461 #define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \ argument
462 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
464 #define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \ argument
465 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
467 #define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ argument
468 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
469 (A_TARGET_READ(scn, \
474 #define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ argument
475 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
476 (A_TARGET_READ(scn, \
482 #define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ argument
483 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
485 #define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ argument
486 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
488 #define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ argument
489 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
491 #define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \ argument
492 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
494 #define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ argument
495 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
496 (A_TARGET_READ(scn, \
501 #define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ argument
502 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
503 (A_TARGET_READ(scn, \
508 #define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ argument
509 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
510 (A_TARGET_READ(scn, \
515 #define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ argument
516 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
517 (A_TARGET_READ(scn, \
522 #define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \ argument
523 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
524 A_TARGET_READ(scn, \
528 #define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \ argument
529 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
530 A_TARGET_READ(scn, \
538 #define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \ argument
539 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
540 A_TARGET_READ(scn, \
544 #define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \ argument
545 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
546 A_TARGET_READ(scn, \
550 #define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \ argument
551 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
552 A_TARGET_READ(scn, \
555 #define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \ argument
556 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
558 #define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \ argument
559 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
561 #define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \ argument
562 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
591 #define CE_INTERRUPT_SUMMARY(scn) \ argument
593 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
596 #define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \ argument
597 (A_TARGET_READ(scn, \
600 #define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \ argument
601 (A_TARGET_READ(scn, \
604 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \ argument
605 (A_TARGET_WRITE(scn, \
609 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \ argument
610 (A_TARGET_WRITE(scn, \
625 #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
626 #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)
631 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
632 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
634 #define CE_SRC_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ argument
635 shadow_sr_wr_ind_addr(scn, CE_ctrl_addr)
636 #define CE_DST_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ argument
637 shadow_dst_wr_ind_addr(scn, CE_ctrl_addr)
639 #define CE_SRC_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ argument
641 #define CE_DST_WR_IDX_OFFSET_GET(scn, CE_ctrl_addr) \ argument
646 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
647 A_TARGET_DELAYED_REG_WRITE(scn, CE_ctrl_addr, n)
648 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
649 A_TARGET_DELAYED_REG_WRITE(scn, CE_ctrl_addr, n)
651 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
652 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
653 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
654 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
656 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
657 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
658 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ argument
659 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
666 #define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ argument
667 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
668 #define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ argument
669 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)