Lines Matching refs:ATH_UNSUPPORTED_REG_OFFSET
29 #define ATH_UNSUPPORTED_REG_OFFSET UNSUPPORTED_REGISTER_OFFSET macro
31 ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET)
41 #define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET
47 #define WLAN_MAC_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
51 #define CE0_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
52 #define CE1_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
63 #define FW_INDICATOR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
67 #define FW_CPU_PLL_CONFIG ATH_UNSUPPORTED_REG_OFFSET
71 #define DRAM_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
75 #define SOC_CORE_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
79 #define CPU_INTR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
83 #define SOC_LF_TIMER_CONTROL0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
84 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET
88 #define SOC_LF_TIMER_STATUS0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
92 #define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
93 #define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET
94 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET
98 #define CORE_CTRL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
103 #define PCIE_INTR_ENABLE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
104 #define PCIE_INTR_CLR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
105 #define PCIE_INTR_FIRMWARE_MASK ATH_UNSUPPORTED_REG_OFFSET
106 #define PCIE_INTR_CE_MASK_ALL ATH_UNSUPPORTED_REG_OFFSET
107 #define PCIE_INTR_CAUSE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
111 #define WIFICMN_PCIE_BAR_REG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
115 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
119 #define FW_AXI_MSI_ADDR ATH_UNSUPPORTED_REG_OFFSET
123 #define FW_AXI_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET
127 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
131 #define FPGA_VERSION_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
135 #define SI_CONFIG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
149 #define SI_TX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET
150 #define SI_TX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET
151 #define SI_RX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET
152 #define SI_RX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET
153 #define SI_CS_OFFSET ATH_UNSUPPORTED_REG_OFFSET
165 #define SI_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
169 #define WLAN_GPIO_PIN10_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
173 #define WLAN_GPIO_PIN11_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
177 #define WLAN_GPIO_PIN12_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
181 #define WLAN_GPIO_PIN13_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
185 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
323 #define CE_DDR_ADDRESS_FOR_RRI_LOW ATH_UNSUPPORTED_REG_OFFSET
326 #define CE_DDR_ADDRESS_FOR_RRI_HIGH ATH_UNSUPPORTED_REG_OFFSET
329 #define SR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET
332 #define DR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET
335 #define CE_CMD_REGISTER ATH_UNSUPPORTED_REG_OFFSET
338 #define CE_MSI_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
341 #define CE_MSI_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET
344 #define CE_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET
347 #define CE_MSI_ENABLE_BIT ATH_UNSUPPORTED_REG_OFFSET
350 #define CE_CTRL1_IDX_UPD_EN_MASK ATH_UNSUPPORTED_REG_OFFSET
353 #define CE_WRAPPER_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET
356 #define CE_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET
359 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES ATH_UNSUPPORTED_REG_OFFSET
362 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET
365 #define HOST_IE_ADDRESS_2 ATH_UNSUPPORTED_REG_OFFSET
368 #define HOST_IE_ADDRESS_3 ATH_UNSUPPORTED_REG_OFFSET
380 #define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
383 #define HOST_CMEM_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
386 #define PMM_SCRATCH_BASE ATH_UNSUPPORTED_REG_OFFSET