Lines Matching refs:scn
23 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
25 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
27 (scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
29 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
31 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
33 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
35 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
37 (scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
39 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
43 (scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
45 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
47 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
49 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
51 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
53 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
55 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
57 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
59 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
61 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
62 #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
63 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
64 #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
66 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
68 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
70 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
71 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
73 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
74 #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET)
76 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
78 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
80 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
82 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
84 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
85 #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS)
86 #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET)
87 #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET)
88 #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
89 #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
90 #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
92 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
94 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
95 #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB)
97 (scn->targetdef->d_SI_CONFIG_I2C_MASK)
99 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
101 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
103 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
105 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
107 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
109 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
110 #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
111 #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
112 #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS)
113 #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET)
114 #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET)
115 #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET)
116 #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET)
117 #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET)
118 #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET)
119 #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
120 #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK)
121 #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB)
122 #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK)
123 #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB)
124 #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK)
125 #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB)
126 #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK)
127 #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ)
128 #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ)
129 #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS)
130 #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
131 #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET)
132 #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET)
133 #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET)
134 #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET)
135 #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET)
136 #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET)
137 #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET)
138 #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
139 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
140 #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
141 #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
143 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
145 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
146 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
147 #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
148 #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS)
149 #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS)
150 #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
151 #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS)
152 #define CE_COUNT (scn->targetdef->d_CE_COUNT)
153 #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
154 #define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
155 #define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
156 #define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
157 #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
158 #define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
159 #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
163 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
165 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
166 #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS)
168 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
170 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
172 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
174 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
176 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
186 #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
187 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
188 #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
189 #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
190 #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
198 #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
199 #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS)
200 #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET)
206 #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET)
207 #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
208 #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
209 #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
210 #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
211 #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
212 #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
213 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
214 #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
215 #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
216 #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
217 #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
218 #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
219 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
220 #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
221 #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
222 #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
223 #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
225 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
227 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
229 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
231 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
233 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
235 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
237 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
239 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
241 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
243 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
245 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
247 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
249 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
251 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
253 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
254 #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
255 #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
256 #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
258 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
259 #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
260 #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
261 #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
262 #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
263 #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
264 #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
265 #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
267 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
269 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
271 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
273 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
275 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
276 #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
277 #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
279 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
281 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
283 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
287 (scn->targetdef->d_FW_CPU_PLL_CONFIG)
311 (scn->targetdef->d_CE_CMD_ADDRESS)
313 (scn->targetdef->d_CE_CMD_HALT_MASK)
315 (scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
317 (scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
320 (scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
322 (scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
324 (scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
326 (scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
328 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
330 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
333 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
336 (scn->targetdef->d_FW_AXI_MSI_ADDR)
338 (scn->targetdef->d_FW_AXI_MSI_DATA)
340 (scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
342 (scn->targetdef->d_FPGA_VERSION_ADDRESS)
431 (scn->targetdef->d_Q6_ENABLE_REGISTER_0)
433 (scn->targetdef->d_Q6_ENABLE_REGISTER_1)
435 (scn->targetdef->d_Q6_CAUSE_REGISTER_0)
437 (scn->targetdef->d_Q6_CAUSE_REGISTER_1)
439 (scn->targetdef->d_Q6_CLEAR_REGISTER_0)
441 (scn->targetdef->d_Q6_CLEAR_REGISTER_1)
446 (scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
449 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
450 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)
451 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)
452 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)
453 #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT)
454 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)
456 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
458 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
459 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
460 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
462 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
464 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
466 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
468 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
470 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
472 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
474 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
476 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
478 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
480 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
482 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
484 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
486 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
487 #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
488 #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
489 #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
491 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
493 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
495 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
497 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
499 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
501 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
502 #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS)
503 #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
504 #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
505 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
506 #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
508 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
510 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
511 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
512 #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS)
513 #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
514 #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
515 #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
516 #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS)
517 #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
518 #define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
519 #define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
520 #define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
521 #define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
522 #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK)
523 #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB)
524 #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING)
525 #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED)
526 #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER)
527 #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON)
529 #define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY)
533 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
535 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
659 void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
660 void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);