119 #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \  argument
120 	hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
123 				 uint32_t offset,
135 #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \  argument
137 		offset,	\
151 						    uint32_t offset,  in hal_reg_write_result_check()  argument
156 	value = qdf_ioread32(hal_soc->dev_base_addr + offset);  in hal_reg_write_result_check()
158 		HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);  in hal_reg_write_result_check()
202 					     uint32_t offset)  in hal_select_window_confirm()  argument
204 	uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;  in hal_select_window_confirm()
215 					     uint32_t offset)  in hal_select_window_confirm()  argument
217 	uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;  in hal_select_window_confirm()
276 static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,  in hal_write32_mb()  argument
283 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_write32_mb()
284 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb()
287 				hal_soc->dev_base_addr + offset);  in hal_write32_mb()
291 		hal_select_window_confirm(hal_soc, offset);  in hal_write32_mb()
293 			  (offset & WINDOW_RANGE_MASK), value);  in hal_write32_mb()
307 						uint32_t offset,  in hal_write32_mb_confirm()  argument
310 	hal_write32_mb(hal_soc, offset, value);  in hal_write32_mb_confirm()
316 static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,  in hal_write32_mb()  argument
330 	if (offset < MAPPED_REF_OFF) {  in hal_write32_mb()
331 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb()
345 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_write32_mb()
346 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb()
350 					hal_soc->dev_base_addr + offset);  in hal_write32_mb()
354 		hal_select_window_confirm(hal_soc, offset);  in hal_write32_mb()
356 			  (offset & WINDOW_RANGE_MASK), value);  in hal_write32_mb()
376 						uint32_t offset,  in hal_write32_mb_confirm()  argument
391 	if (offset < MAPPED_REF_OFF) {  in hal_write32_mb_confirm()
392 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb_confirm()
406 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_write32_mb_confirm()
407 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb_confirm()
408 		status = hal_reg_write_result_check(hal_soc, offset,  in hal_write32_mb_confirm()
413 					hal_soc->dev_base_addr + offset);  in hal_write32_mb_confirm()
421 		hal_select_window_confirm(hal_soc, offset);  in hal_write32_mb_confirm()
423 			  (offset & WINDOW_RANGE_MASK), value);  in hal_write32_mb_confirm()
427 				WINDOW_START + (offset & WINDOW_RANGE_MASK),  in hal_write32_mb_confirm()
447 static inline void hal_write32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset,  in hal_write32_mb_cmem()  argument
460 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_write32_mb_cmem()
461 		qdf_iowrite32(hal_soc->dev_base_addr + offset, value);  in hal_write32_mb_cmem()
465 					hal_soc->dev_base_addr + offset);  in hal_write32_mb_cmem()
469 		hal_select_window_confirm(hal_soc, offset);  in hal_write32_mb_cmem()
471 			  (offset & WINDOW_RANGE_MASK), value);  in hal_write32_mb_cmem()
488 	uint32_t offset;  in hal_write_address_32_mb()  local
493 	offset = addr - hal_soc->dev_base_addr;  in hal_write_address_32_mb()
496 		hal_write32_mb_confirm(hal_soc, offset, value);  in hal_write_address_32_mb()
498 		hal_write32_mb(hal_soc, offset, value);  in hal_write_address_32_mb()
553 static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)  in hal_read32_mb()  argument
560 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_read32_mb()
561 		return qdf_ioread32(hal_soc->dev_base_addr + offset);  in hal_read32_mb()
563 		new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);  in hal_read32_mb()
568 	hal_select_window_confirm(hal_soc, offset);  in hal_read32_mb()
570 		       (offset & WINDOW_RANGE_MASK));  in hal_read32_mb()
579 uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)  in hal_read32_mb()  argument
593 	if (offset < MAPPED_REF_OFF)  in hal_read32_mb()
594 		return qdf_ioread32(hal_soc->dev_base_addr + offset);  in hal_read32_mb()
604 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_read32_mb()
605 		ret = qdf_ioread32(hal_soc->dev_base_addr + offset);  in hal_read32_mb()
609 					hal_soc->dev_base_addr + offset);  in hal_read32_mb()
613 		hal_select_window_confirm(hal_soc, offset);  in hal_read32_mb()
615 			       (offset & WINDOW_RANGE_MASK));  in hal_read32_mb()
629 uint32_t hal_read32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset)  in hal_read32_mb_cmem()  argument
642 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hal_read32_mb_cmem()
643 		ret = qdf_ioread32(hal_soc->dev_base_addr + offset);  in hal_read32_mb_cmem()
647 					hal_soc->dev_base_addr + offset);  in hal_read32_mb_cmem()
651 		hal_select_window_confirm(hal_soc, offset);  in hal_read32_mb_cmem()
653 			       (offset & WINDOW_RANGE_MASK));  in hal_read32_mb_cmem()
796 						uint32_t offset,  in hal_write32_mb_confirm_retry()  argument
802 	ret = hal_write32_mb_shadow_confirm(hal_soc, offset, value);  in hal_write32_mb_confirm_retry()
809 						uint32_t offset,  in hal_write32_mb_confirm_retry()  argument
818 		ret = hal_write32_mb_confirm(hal_soc, offset, value);  in hal_write32_mb_confirm_retry()
823 		read_value = hal_read32_mb(hal_soc, offset);  in hal_write32_mb_confirm_retry()
829 			 offset, value, read_value);  in hal_write32_mb_confirm_retry()
912 	uint32_t offset;  in hal_read_address_32_mb()  local
918 	offset = addr - soc->dev_base_addr;  in hal_read_address_32_mb()
919 	ret = hal_read32_mb(soc, offset);  in hal_read_address_32_mb()
3384 hal_cmem_write(hal_soc_handle_t hal_soc_hdl, uint32_t offset,  in hal_cmem_write()  argument
3390 		hal_soc->ops->hal_cmem_write(hal_soc_hdl, offset, value);  in hal_cmem_write()