Lines Matching refs:reg_val
3327 uint32_t reg_val = 0; in hal_reo_shared_qaddr_cache_clear_be() local
3332 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); in hal_reo_shared_qaddr_cache_clear_be()
3333 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); in hal_reo_shared_qaddr_cache_clear_be()
3336 reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3341 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); in hal_reo_shared_qaddr_cache_clear_be()
3344 reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3348 "to erase stale entries in reo storage: regval:%x", hal, reg_val); in hal_reo_shared_qaddr_cache_clear_be()
3542 uint32_t reg_addr, reg_val = 0; in hal_tx_vdev_mismatch_routing_set_generic_be() local
3553 reg_val = val | (config << in hal_tx_vdev_mismatch_routing_set_generic_be()
3556 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_vdev_mismatch_routing_set_generic_be()
3583 uint32_t reg_addr, reg_val = 0; in hal_tx_mcast_mlo_reinject_routing_set_generic_be() local
3593 reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); in hal_tx_mcast_mlo_reinject_routing_set_generic_be()
3595 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_mcast_mlo_reinject_routing_set_generic_be()
3812 uint32_t reg_addr, reg_val = 0; in hal_cookie_conversion_reg_cfg_generic_be() local
3817 reg_val = cc_cfg->lut_base_addr_31_0; in hal_cookie_conversion_reg_cfg_generic_be()
3818 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3821 reg_val = 0; in hal_cookie_conversion_reg_cfg_generic_be()
3822 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3825 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3828 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3831 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3834 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3837 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3840 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3844 reg_val = cc_cfg->lut_base_addr_31_0; in hal_cookie_conversion_reg_cfg_generic_be()
3845 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3848 reg_val = 0; in hal_cookie_conversion_reg_cfg_generic_be()
3849 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3852 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3855 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3858 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, in hal_cookie_conversion_reg_cfg_generic_be()
3861 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3867 reg_val = 0; in hal_cookie_conversion_reg_cfg_generic_be()
3868 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3871 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3874 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3877 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3880 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3883 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3886 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3889 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3892 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, in hal_cookie_conversion_reg_cfg_generic_be()
3895 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3899 reg_val = 0; in hal_cookie_conversion_reg_cfg_generic_be()
3900 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, in hal_cookie_conversion_reg_cfg_generic_be()
3904 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, in hal_cookie_conversion_reg_cfg_generic_be()
3908 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, in hal_cookie_conversion_reg_cfg_generic_be()
3912 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, in hal_cookie_conversion_reg_cfg_generic_be()
3916 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3925 reg_val = HAL_REG_READ(soc, reg_addr); in hal_cookie_conversion_reg_cfg_generic_be()
3926 reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, in hal_cookie_conversion_reg_cfg_generic_be()
3929 HAL_REG_WRITE(soc, reg_addr, reg_val); in hal_cookie_conversion_reg_cfg_generic_be()
3993 uint32_t reg_addr, reg_val = 0; in hal_tx_populate_bank_register_be() local
3998 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); in hal_tx_populate_bank_register_be()
3999 reg_val |= (config->encap_type << in hal_tx_populate_bank_register_be()
4001 reg_val |= (config->encrypt_type << in hal_tx_populate_bank_register_be()
4003 reg_val |= (config->src_buffer_swap << in hal_tx_populate_bank_register_be()
4005 reg_val |= (config->link_meta_swap << in hal_tx_populate_bank_register_be()
4007 reg_val |= (config->index_lookup_enable << in hal_tx_populate_bank_register_be()
4009 reg_val |= (config->addrx_en << in hal_tx_populate_bank_register_be()
4011 reg_val |= (config->addry_en << in hal_tx_populate_bank_register_be()
4013 reg_val |= (config->mesh_enable << in hal_tx_populate_bank_register_be()
4015 reg_val |= (config->vdev_id_check_en << in hal_tx_populate_bank_register_be()
4017 reg_val |= (config->pmac_id << in hal_tx_populate_bank_register_be()
4019 reg_val |= (config->mcast_pkt_ctrl << in hal_tx_populate_bank_register_be()
4022 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_populate_bank_register_be()
4031 uint32_t reg_addr, reg_val = 0; in hal_tx_populate_bank_register_be() local
4036 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); in hal_tx_populate_bank_register_be()
4037 reg_val |= (config->encap_type << in hal_tx_populate_bank_register_be()
4039 reg_val |= (config->encrypt_type << in hal_tx_populate_bank_register_be()
4041 reg_val |= (config->src_buffer_swap << in hal_tx_populate_bank_register_be()
4043 reg_val |= (config->link_meta_swap << in hal_tx_populate_bank_register_be()
4045 reg_val |= (config->index_lookup_enable << in hal_tx_populate_bank_register_be()
4047 reg_val |= (config->addrx_en << in hal_tx_populate_bank_register_be()
4049 reg_val |= (config->addry_en << in hal_tx_populate_bank_register_be()
4051 reg_val |= (config->mesh_enable << in hal_tx_populate_bank_register_be()
4053 reg_val |= (config->vdev_id_check_en << in hal_tx_populate_bank_register_be()
4055 reg_val |= (config->pmac_id << in hal_tx_populate_bank_register_be()
4057 reg_val |= (config->dscp_tid_map_id << in hal_tx_populate_bank_register_be()
4060 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_populate_bank_register_be()
4085 uint32_t reg_addr, reg_val = 0; in hal_tx_vdev_mcast_ctrl_set_be() local
4101 reg_val = val | in hal_tx_vdev_mcast_ctrl_set_be()
4105 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); in hal_tx_vdev_mcast_ctrl_set_be()