1664 	u32 fw_pmu_param_len, i, j, plat_vreg_param_len = 0;  in cnss_aop_ol_cpr_cfg_setup()  local
1702 		for (j = 0; j < plat_priv->pmu_vreg_map_len; j += 2) {  in cnss_aop_ol_cpr_cfg_setup()
1703 			pmu_pin = plat_priv->pmu_vreg_map[j];  in cnss_aop_ol_cpr_cfg_setup()
1706 				vreg = plat_priv->pmu_vreg_map[j + 1];  in cnss_aop_ol_cpr_cfg_setup()
1718 		for (j = 0; j < QMI_WLFW_PMU_PARAMS_MAX_V01; j++) {  in cnss_aop_ol_cpr_cfg_setup()
1721 			if (plat_vreg_param[j].vreg[0] == '\0')  in cnss_aop_ol_cpr_cfg_setup()
1722 				strlcpy(plat_vreg_param[j].vreg, vreg,  in cnss_aop_ol_cpr_cfg_setup()
1723 					sizeof(plat_vreg_param[j].vreg));  in cnss_aop_ol_cpr_cfg_setup()
1724 			else if (!strnstr(plat_vreg_param[j].vreg, vreg,  in cnss_aop_ol_cpr_cfg_setup()
1725 					  strlen(plat_vreg_param[j].vreg)))  in cnss_aop_ol_cpr_cfg_setup()
1739 			plat_vreg_param[j].wake_volt =  in cnss_aop_ol_cpr_cfg_setup()
1740 				(wake_volt > plat_vreg_param[j].wake_volt ?  in cnss_aop_ol_cpr_cfg_setup()
1741 				 wake_volt : plat_vreg_param[j].wake_volt);  in cnss_aop_ol_cpr_cfg_setup()
1742 			plat_vreg_param[j].sleep_volt =  in cnss_aop_ol_cpr_cfg_setup()
1743 				(sleep_volt > plat_vreg_param[j].sleep_volt ?  in cnss_aop_ol_cpr_cfg_setup()
1744 				 sleep_volt : plat_vreg_param[j].sleep_volt);  in cnss_aop_ol_cpr_cfg_setup()
1746 			plat_vreg_param_len = (plat_vreg_param_len > j ?  in cnss_aop_ol_cpr_cfg_setup()
1747 					       plat_vreg_param_len : j);  in cnss_aop_ol_cpr_cfg_setup()
1749 				    plat_vreg_param[j].vreg,  in cnss_aop_ol_cpr_cfg_setup()
1750 				    plat_vreg_param[j].wake_volt,  in cnss_aop_ol_cpr_cfg_setup()
1751 				    plat_vreg_param[j].sleep_volt);  in cnss_aop_ol_cpr_cfg_setup()
1891 	int i, j;  in cnss_update_cpr_info()  local
1928 		for (j = 0; j < MAX_TCS_CMD_NUM; j++) {  in cnss_update_cpr_info()
1929 			offset = i * TCS_OFFSET + j * TCS_CMD_OFFSET;  in cnss_update_cpr_info()
1938 					    voltage_tmp, i, j);  in cnss_update_cpr_info()