112 enum which_base { FS, GS };  enumerator
129 		asm volatile ("mov %%gs:(%%rcx), %%rax" : : "c" (offset) : "rax");  in read_base()
145 		asm volatile ("mov %%gs:(%%rcx), %%rax"  in read_base()
163 	asm volatile ("mov %%gs, %0" : "=rm" (sel));  in check_gs_value()
164 	base = read_base(GS);  in check_gs_value()
190 …printf("[RUN]\tARCH_SET_GS to 0x%lx then mov 0 to %%gs%s\n", initial_base, schedule ? " and schedu…  in mov_0_gs()
197 	asm volatile ("mov %0, %%gs" : : "rm" (0));  in mov_0_gs()
198 	base = read_base(GS);  in mov_0_gs()
213  * ARCH_SET_FS/GS(0) may or may not program a selector of zero.  HARD_ZERO
231 		asm volatile ("mov %0, %%gs" : : "rm" ((unsigned short)0));  in do_remote_base()
234 	asm volatile ("mov %%gs, %0" : "=rm" (sel));  in do_remote_base()
236 	       to_set, hard_zero ? " and clear gs" : "", sel);  in do_remote_base()
244 	 * Sets GS != 0 and GSBASE != 0 but arranges for the kernel to think  in load_gs()
266 		asm volatile ("mov %0, %%gs" : : "rm" ((unsigned short)0x7));  in load_gs()
295 		unsigned short gs = (unsigned short)((desc.entry_number << 3) | 0x3);  in load_gs()  local
296 		asm volatile ("mov %0, %%gs" : : "rm" (gs));  in load_gs()
297 		return gs;  in load_gs()
308 	asm volatile ("mov %0, %%gs" : : "rm" (index));  in test_wrbase()
317 	asm volatile ("mov %%gs, %0" : "=rm" (newindex));  in test_wrbase()
323 		printf("[FAIL]\tAfter switch, GS = 0x%hx and GSBASE = 0x%lx\n",  in test_wrbase()
341 			 * On AMD chips, this causes GSBASE != 0, GS == 0, and  in threadproc()
346 			asm volatile ("mov %0, %%gs" : : "rm" ((unsigned short)0));  in threadproc()
370 	       local, hard_zero ? " and clear gs" : "", remote);  in set_gs_and_switch_to()
376 		asm volatile ("mov %0, %%gs" : : "rm" ((unsigned short)0));  in set_gs_and_switch_to()
378 	if (read_base(GS) != local) {  in set_gs_and_switch_to()
384 		asm volatile ("mov %0, %%gs" : : "rm" (force_sel));  in set_gs_and_switch_to()
386 		local = read_base(GS);  in set_gs_and_switch_to()
392 		asm volatile ("mov %0, %%gs" : : "rm" (force_sel));  in set_gs_and_switch_to()
394 		asm volatile ("mov %%gs, %0" : "=rm" (sel_pre_sched));  in set_gs_and_switch_to()
403 	asm volatile ("mov %%gs, %0" : "=rm" (sel_post_sched));  in set_gs_and_switch_to()
404 	base = read_base(GS);  in set_gs_and_switch_to()
427 	printf("[RUN]\tARCH_SET_GS(0), clear gs, then manipulate GSBASE in a different thread\n");  in test_unexpected_base()
430 	asm volatile ("mov %0, %%gs" : : "rm" ((unsigned short)0));  in test_unexpected_base()
437 	base = read_base(GS);  in test_unexpected_base()
457 		printf("[RUN]\tPTRACE_POKE GS, read GSBASE back\n");  in test_ptrace_write_gs_read_base()
474 		unsigned long gs_offset = USER_REGS_OFFSET(gs);  in test_ptrace_write_gs_read_base()
486 		printf("[RUN]\tSet GS = 0x7, read GSBASE\n");  in test_ptrace_write_gs_read_base()
488 		/* Poke an LDT selector into GS. */  in test_ptrace_write_gs_read_base()
496 			printf("[OK]\tGSBASE reads as 0x%lx with invalid GS\n", base);  in test_ptrace_write_gs_read_base()
533 		unsigned long gs, base;  in test_ptrace_write_gsbase()  local
534 		unsigned long gs_offset = USER_REGS_OFFSET(gs);  in test_ptrace_write_gsbase()
537 		gs = ptrace(PTRACE_PEEKUSER, child, gs_offset, NULL);  in test_ptrace_write_gsbase()
539 		if (gs != *shared_scratch) {  in test_ptrace_write_gsbase()
548 		gs = ptrace(PTRACE_PEEKUSER, child, gs_offset, NULL);  in test_ptrace_write_gsbase()
557 		if (gs != *shared_scratch) {  in test_ptrace_write_gsbase()
559 			printf("[FAIL]\tGS changed to %lx\n", gs);  in test_ptrace_write_gsbase()
569 			if (gs == 0)  in test_ptrace_write_gsbase()