Lines Matching full:reg
9 #define PUSH_VMX(pos,reg) \ argument
10 li reg,pos; \
11 stvx v20,reg,%r1; \
12 addi reg,reg,16; \
13 stvx v21,reg,%r1; \
14 addi reg,reg,16; \
15 stvx v22,reg,%r1; \
16 addi reg,reg,16; \
17 stvx v23,reg,%r1; \
18 addi reg,reg,16; \
19 stvx v24,reg,%r1; \
20 addi reg,reg,16; \
21 stvx v25,reg,%r1; \
22 addi reg,reg,16; \
23 stvx v26,reg,%r1; \
24 addi reg,reg,16; \
25 stvx v27,reg,%r1; \
26 addi reg,reg,16; \
27 stvx v28,reg,%r1; \
28 addi reg,reg,16; \
29 stvx v29,reg,%r1; \
30 addi reg,reg,16; \
31 stvx v30,reg,%r1; \
32 addi reg,reg,16; \
33 stvx v31,reg,%r1;
36 #define POP_VMX(pos,reg) \ argument
37 li reg,pos; \
38 lvx v20,reg,%r1; \
39 addi reg,reg,16; \
40 lvx v21,reg,%r1; \
41 addi reg,reg,16; \
42 lvx v22,reg,%r1; \
43 addi reg,reg,16; \
44 lvx v23,reg,%r1; \
45 addi reg,reg,16; \
46 lvx v24,reg,%r1; \
47 addi reg,reg,16; \
48 lvx v25,reg,%r1; \
49 addi reg,reg,16; \
50 lvx v26,reg,%r1; \
51 addi reg,reg,16; \
52 lvx v27,reg,%r1; \
53 addi reg,reg,16; \
54 lvx v28,reg,%r1; \
55 addi reg,reg,16; \
56 lvx v29,reg,%r1; \
57 addi reg,reg,16; \
58 lvx v30,reg,%r1; \
59 addi reg,reg,16; \
60 lvx v31,reg,%r1;