77 static enum gicv3_intid_range get_intid_range(unsigned int intid)  in get_intid_range()  argument
79 	switch (intid) {  in get_intid_range()
168 static void gicv3_access_reg(uint32_t intid, uint64_t offset,  in gicv3_access_reg()  argument
173 	enum gicv3_intid_range intid_range = get_intid_range(intid);  in gicv3_access_reg()
186 	index = intid % fields_per_reg;  in gicv3_access_reg()
190 	/* Set offset to the actual register holding intid's config. */  in gicv3_access_reg()
191 	offset += (intid / fields_per_reg) * (reg_bits / 8);  in gicv3_access_reg()
200 static void gicv3_write_reg(uint32_t intid, uint64_t offset,  in gicv3_write_reg()  argument
203 	gicv3_access_reg(intid, offset, reg_bits,  in gicv3_write_reg()
207 static uint32_t gicv3_read_reg(uint32_t intid, uint64_t offset,  in gicv3_read_reg()  argument
212 	gicv3_access_reg(intid, offset, reg_bits,  in gicv3_read_reg()
217 static void gicv3_set_priority(uint32_t intid, uint32_t prio)  in gicv3_set_priority()  argument
219 	gicv3_write_reg(intid, GICD_IPRIORITYR, 32, 8, prio);  in gicv3_set_priority()
222 /* Sets the intid to be level-sensitive or edge-triggered. */
223 static void gicv3_irq_set_config(uint32_t intid, bool is_edge)  in gicv3_irq_set_config()  argument
228 	GUEST_ASSERT(get_intid_range(intid) == SPI_RANGE);  in gicv3_irq_set_config()
230 	gicv3_write_reg(intid, GICD_ICFGR, 32, 2, val);  in gicv3_irq_set_config()
233 static void gicv3_irq_enable(uint32_t intid)  in gicv3_irq_enable()  argument
235 	bool is_spi = get_intid_range(intid) == SPI_RANGE;  in gicv3_irq_enable()
238 	gicv3_write_reg(intid, GICD_ISENABLER, 32, 1, 1);  in gicv3_irq_enable()
242 static void gicv3_irq_disable(uint32_t intid)  in gicv3_irq_disable()  argument
244 	bool is_spi = get_intid_range(intid) == SPI_RANGE;  in gicv3_irq_disable()
247 	gicv3_write_reg(intid, GICD_ICENABLER, 32, 1, 1);  in gicv3_irq_disable()
251 static void gicv3_irq_set_active(uint32_t intid)  in gicv3_irq_set_active()  argument
253 	gicv3_write_reg(intid, GICD_ISACTIVER, 32, 1, 1);  in gicv3_irq_set_active()
256 static void gicv3_irq_clear_active(uint32_t intid)  in gicv3_irq_clear_active()  argument
258 	gicv3_write_reg(intid, GICD_ICACTIVER, 32, 1, 1);  in gicv3_irq_clear_active()
261 static bool gicv3_irq_get_active(uint32_t intid)  in gicv3_irq_get_active()  argument
263 	return gicv3_read_reg(intid, GICD_ISACTIVER, 32, 1);  in gicv3_irq_get_active()
266 static void gicv3_irq_set_pending(uint32_t intid)  in gicv3_irq_set_pending()  argument
268 	gicv3_write_reg(intid, GICD_ISPENDR, 32, 1, 1);  in gicv3_irq_set_pending()
271 static void gicv3_irq_clear_pending(uint32_t intid)  in gicv3_irq_clear_pending()  argument
273 	gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1);  in gicv3_irq_clear_pending()
276 static bool gicv3_irq_get_pending(uint32_t intid)  in gicv3_irq_get_pending()  argument
278 	return gicv3_read_reg(intid, GICD_ISPENDR, 32, 1);  in gicv3_irq_get_pending()