276 static struct simd_flags arm_spe__synth_simd_flags(const struct arm_spe_record *record)  in arm_spe__synth_simd_flags()  argument
280 	if ((record->op & ARM_SPE_OP_LDST) && (record->op & ARM_SPE_OP_SVE_LDST))  in arm_spe__synth_simd_flags()
283 	if ((record->op & ARM_SPE_OP_OTHER) && (record->op & ARM_SPE_OP_SVE_OTHER))  in arm_spe__synth_simd_flags()
286 	if (record->type & ARM_SPE_SVE_PARTIAL_PRED)  in arm_spe__synth_simd_flags()
289 	if (record->type & ARM_SPE_SVE_EMPTY_PRED)  in arm_spe__synth_simd_flags()
300 	struct arm_spe_record *record = &speq->decoder->record;  in arm_spe_prep_sample()  local
303 		sample->time = tsc_to_perf_time(record->timestamp, &spe->tc);  in arm_spe_prep_sample()
305 	sample->ip = record->from_ip;  in arm_spe_prep_sample()
311 	sample->simd_flags = arm_spe__synth_simd_flags(record);  in arm_spe_prep_sample()
349 	struct arm_spe_record *record = &speq->decoder->record;  in arm_spe__synth_mem_sample()  local
357 	sample.addr = record->virt_addr;  in arm_spe__synth_mem_sample()
358 	sample.phys_addr = record->phys_addr;  in arm_spe__synth_mem_sample()
360 	sample.weight = record->latency;  in arm_spe__synth_mem_sample()
369 	struct arm_spe_record *record = &speq->decoder->record;  in arm_spe__synth_branch_sample()  local
377 	sample.addr = record->to_ip;  in arm_spe__synth_branch_sample()
378 	sample.weight = record->latency;  in arm_spe__synth_branch_sample()
387 	struct arm_spe_record *record = &speq->decoder->record;  in arm_spe__synth_instruction_sample()  local
403 	sample.addr = record->virt_addr;  in arm_spe__synth_instruction_sample()
404 	sample.phys_addr = record->phys_addr;  in arm_spe__synth_instruction_sample()
407 	sample.weight = record->latency;  in arm_spe__synth_instruction_sample()
419 static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record,  in arm_spe__synth_data_source_neoverse()  argument
434 	if (record->op & ARM_SPE_OP_ST) {  in arm_spe__synth_data_source_neoverse()
441 	switch (record->source) {  in arm_spe__synth_data_source_neoverse()
495 static void arm_spe__synth_data_source_generic(const struct arm_spe_record *record,  in arm_spe__synth_data_source_generic()  argument
498 	if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) {  in arm_spe__synth_data_source_generic()
501 		if (record->type & ARM_SPE_LLC_MISS)  in arm_spe__synth_data_source_generic()
505 	} else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) {  in arm_spe__synth_data_source_generic()
508 		if (record->type & ARM_SPE_L1D_MISS)  in arm_spe__synth_data_source_generic()
514 	if (record->type & ARM_SPE_REMOTE_ACCESS)  in arm_spe__synth_data_source_generic()
518 static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr)  in arm_spe__synth_data_source()  argument
523 	if (record->op & ARM_SPE_OP_LD)  in arm_spe__synth_data_source()
525 	else if (record->op & ARM_SPE_OP_ST)  in arm_spe__synth_data_source()
531 		arm_spe__synth_data_source_neoverse(record, &data_src);  in arm_spe__synth_data_source()
533 		arm_spe__synth_data_source_generic(record, &data_src);  in arm_spe__synth_data_source()
535 	if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) {  in arm_spe__synth_data_source()
538 		if (record->type & ARM_SPE_TLB_MISS)  in arm_spe__synth_data_source()
549 	const struct arm_spe_record *record = &speq->decoder->record;  in arm_spe_sample()  local
554 	data_src = arm_spe__synth_data_source(record, spe->midr);  in arm_spe_sample()
557 		if (record->type & ARM_SPE_L1D_MISS) {  in arm_spe_sample()
564 		if (record->type & ARM_SPE_L1D_ACCESS) {  in arm_spe_sample()
573 		if (record->type & ARM_SPE_LLC_MISS) {  in arm_spe_sample()
580 		if (record->type & ARM_SPE_LLC_ACCESS) {  in arm_spe_sample()
589 		if (record->type & ARM_SPE_TLB_MISS) {  in arm_spe_sample()
596 		if (record->type & ARM_SPE_TLB_ACCESS) {  in arm_spe_sample()
604 	if (spe->sample_branch && (record->type & ARM_SPE_BRANCH_MISS)) {  in arm_spe_sample()
611 	    (record->type & ARM_SPE_REMOTE_ACCESS)) {  in arm_spe_sample()
619 	 * When data_src is zero it means the record is not a memory operation,  in arm_spe_sample()
640 	struct arm_spe_record *record;  in arm_spe_run_decoder()  local
649 		 * based the record to synthesize sample; but here the flow is  in arm_spe_run_decoder()
655 		 * has decoded trace data and generated a record, but the record  in arm_spe_run_decoder()
657 		 * to synthesize sample for the left record.  in arm_spe_run_decoder()
658 		 * 2. After decoding trace data, it needs to compare the record  in arm_spe_run_decoder()
659 		 * timestamp with the coming perf event, if the record timestamp  in arm_spe_run_decoder()
661 		 * record into auxtrace heap, thus the record can be deferred to  in arm_spe_run_decoder()
670 		record = &speq->decoder->record;  in arm_spe_run_decoder()
671 		if (!spe->timeless_decoding && record->context_id != (u64)-1) {  in arm_spe_run_decoder()
672 			ret = arm_spe_set_tid(speq, record->context_id);  in arm_spe_run_decoder()
696 		record = &speq->decoder->record;  in arm_spe_run_decoder()
698 		/* Update timestamp for the last record */  in arm_spe_run_decoder()
699 		if (record->timestamp > speq->timestamp)  in arm_spe_run_decoder()
700 			speq->timestamp = record->timestamp;  in arm_spe_run_decoder()
721 	struct arm_spe_record *record;  in arm_spe__setup_queue()  local
751 		record = &speq->decoder->record;  in arm_spe__setup_queue()
753 		speq->timestamp = record->timestamp;  in arm_spe__setup_queue()