Lines Matching +full:7 +full:v
44 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
48 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
54 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
72 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0)) argument
73 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48) argument
75 #define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63) argument
76 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61) argument
77 #define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62) argument
78 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56) argument
102 EV_MISPRED = 7,
117 #define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8) argument
121 #define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1)) argument
130 #define SPE_OP_PKT_IS_LDST_ATOMIC(v) (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2) argument
137 #define SPE_OP_PKT_IS_LDST_SVE(v) (((v) & (BIT(3) | BIT(1))) == 0x8) argument
139 #define SPE_OP_PKT_SVE_SG BIT(7)
147 #define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4)) argument
151 #define SPE_OP_PKT_IS_INDIRECT_BRANCH(v) (((v) & GENMASK_ULL(7, 1)) == 0x2) argument