Lines Matching +full:power +full:- +full:sample +full:- +full:average
4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
5 "MetricGroup": "Power",
11 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
12 "MetricGroup": "Power",
18 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
19 "MetricGroup": "Power",
25 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
26 "MetricGroup": "Power",
32 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
33 "MetricGroup": "Power",
39 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
40 "MetricGroup": "Power",
46 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
47 "MetricGroup": "Power",
53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
54 "MetricGroup": "Power",
60 "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
61 "MetricGroup": "Power",
73 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
93 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
110 …-cases for operations that cannot be handled natively by the execution pipeline. For example; when…
116 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
121 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
127 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
132 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
150 …ram path; or stalls when the out-of-order part of the machine needs to recover its state from a sp…
159 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
164 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
168 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
173 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
177 …he CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLE…
187 … true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_…
191 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
192 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
197 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
201 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
203 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L…
207 …-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause in…
211 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
212 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
216 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
225 …than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDE…
231 …o_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread…
235 … loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RET…
240 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
253 …-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heav…
258 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLE…
262 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
266 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
271 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
280 …ultiple Logical Processors contend on different data-elements mapped into the same cache line. Sam…
294 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
299 …he Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RET…
304 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma…
309 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
314 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
318 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
322 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
327 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
336 …ts. FP Assist may apply when working with very small floating point values (so-called Denormals).",
340 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
345 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
349 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
354 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
358 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
363 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
367 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
372 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
376 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
381 … approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May…
387 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
392 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
396 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
397 …"MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0…
402 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
411 … fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RET…
415 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
420 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
423 …"BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lowe…
451 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
464 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
466 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
472 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
477 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
480 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
486 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
489 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
495 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
498 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
506 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
511 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
514 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
519 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
522 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
527 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
530 … "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
535 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
538 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
540 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
551 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
554 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
560 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
564 …t_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (…
573 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
580 "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
581 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
585 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
588 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
589 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
601 "BriefDescription": "Fraction of branches that are non-taken conditionals",
614 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
620 …"MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_call…
631 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
639 "MetricGroup": "Power",
649 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
653 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
656 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
670 …"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch un…
676 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
682 "BriefDescription": "Average Latency for L1 instruction cache misses",
688 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
729 … "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST"
740 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
745 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
748 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
753 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
756 …"BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means hi…
761 …"PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means h…
764 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
769 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
772 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
777 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
836 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
842 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
848 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
854 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
860 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
866 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
884 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
891 "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
926 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
932 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
944 "BriefDescription": "Average Parallel L2 cache miss data reads",
950 "BriefDescription": "Average Latency for L2 cache miss demand Loads",
956 "BriefDescription": "Average Parallel L2 cache miss demand Loads",
962 "BriefDescription": "Average Latency for L3 cache miss demand Loads",
968 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
980 "BriefDescription": "Un-cacheable retired load per kilo instruction",
986 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
990 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
993 … level TLB) code speculative misses per kilo instruction (misses of any page-size that complete th…
999 …l TLB) data load speculative misses per kilo instruction (misses of any page-size that complete th…
1012 … TLB) data store speculative misses per kilo instruction (misses of any page-size that complete th…
1018 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
1024 "BriefDescription": "Average number of uops fetched from DSB per cycle",
1030 "BriefDescription": "Average number of uops fetched from LSD per cycle",
1036 "BriefDescription": "Average number of uops fetched from MITE per cycle",
1050 …"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
1056 "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
1058 "MetricGroup": "Power;Summary",
1062 "BriefDescription": "Average CPU Utilization (percentage)",
1068 "BriefDescription": "Average number of utilized CPUs",
1074 "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
1078 …"PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Relat…
1085 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
1108 "BriefDescription": "Average number of parallel data read requests to external memory",
1112 …"PublicDescription": "Average number of parallel data read requests to external memory. Accounts f…
1115 … "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)",
1119 …tion": "Average latency of data read request to external memory (in nanoseconds). Accounts for dem…
1122 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for ba…
1124 "MetricGroup": "Power",
1126 … was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, …
1129 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1131 "MetricGroup": "Power",
1134 …as running with power-delivery for license level 1. This includes high current AVX 256-bit instru…
1137 …"BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for li…
1139 "MetricGroup": "Power",
1142 …ere the core was running with power-delivery for license level 2 (introduced in SKX). This includ…
1146 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_…
1157 "BriefDescription": "Average Frequency Utilization relative nominal frequency",
1159 "MetricGroup": "Power",
1163 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1175 "BriefDescription": "The ratio of Executed- by Issued-Uops",
1179 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1188 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1194 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
1219 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RET…
1224 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1228 …t stalls; while some non-completed demand load lives in the machine without having that demand loa…
1233 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1237 …ncy of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. S…
1243 …1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALL…
1247 ….e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RET…
1253 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1257 ….e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RET…
1266 …performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RET…
1279 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
1280 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
1285 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
1294 …ion of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATC…
1298 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1299 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1306 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1316 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1320 … classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RET…
1325 "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2",
1329 …ly does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be…
1334 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
1339 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
1343 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1348 …- DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic i…
1352 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1353 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1357 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1367 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1371 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
1385 …odes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS.…
1394 … Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLE…
1399 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2",
1403 …-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long imm…
1408 …"MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_thread…
1415 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1420 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1429 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
1438 …rs often use NOPs for certain address alignments - e.g. start address of a function or loop body. …
1442 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1444 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_in…
1448 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
1452 …action of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches …
1453 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1461 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1473 …atched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATC…
1482 …s Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATC…
1491 …spatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATC…
1500 …patched uops on execution port 6 ([HSW+] Primary Branch and simple ALU). Sample with: UOPS_DISPATC…
1504 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
1505 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1509 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
1518 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
1527 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
1536 …-most compilers feature auto-Vectorization options today- reduces pressure on the execution ports …
1545 …ts (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTE…
1551 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
1556 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
1560 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1565 …-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE seri…
1574 …esents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED…
1578 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1583 …ion of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. S…
1593 …lit store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample wit…
1597 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1602 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1606 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1611 …-for-ownership request before the write. Even though store accesses do not typically stall out-of-…
1621 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1626 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_ST…
1630 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
1639 …on of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATC…
1643 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1644 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1664 …t-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be f…
1673 …is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY…
1687 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1694 "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1701 "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
1708 "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",