x86/tigerlake/cache.json

114         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
118         "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
123         "BriefDescription": "L2 cache misses when fetching instructions",
127         "PublicDescription": "Counts L2 cache misses when fetching instructions.",
136 …n": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cac…
190 …ts that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not …
199 …s that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not …
231         "BriefDescription": "Retired load instructions.",
237 …PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch ins…
242         "BriefDescription": "Retired store instructions.",
248         "PublicDescription": "Counts all retired store instructions.",
253         "BriefDescription": "All retired memory instructions.",
259         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
264         "BriefDescription": "Retired load instructions with locked access.",
270         "PublicDescription": "Counts retired load instructions with locked access.",
275         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
281 …   "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
286         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
292 …  "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
297         "BriefDescription": "Retired load instructions that miss the STLB.",
303 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
308         "BriefDescription": "Retired store instructions that miss the STLB.",
314 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
325 …"PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cor…
330 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop…
336 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros…
341 …"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops r…
347 …"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without …
358 …"PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cro…
363         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
369 …"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or a…
380 …"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1…
385         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
391 … retired load instructions with at least one uop that hit in the L1 data cache. This event include…
396         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
402 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1…
407         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
413         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
418         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
424         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
429         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
435 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 ca…
440         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
446 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3…
601 …the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
609         "BriefDescription": "Number of PREFETCHNTA instructions executed.",
613         "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
618         "BriefDescription": "Number of PREFETCHW instructions executed.",
622         "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
627         "BriefDescription": "Number of PREFETCHT0 instructions executed.",
631         "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
636         "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
640         "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",