x86/skylakex/cache.json

7 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
25 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
68 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
223         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
232         "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
246         "BriefDescription": "Core-originated cacheable demand requests missed L3",
251 … "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Reques…
256         "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
261 …n": "Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests …
294         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
337 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
348 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
353 …Description": "Retired load instructions which data sources were L3 and cross-core snoop hits in o…
359 …Description": "Retired load instructions which data sources were L3 and cross-core snoop hits in o…
364 …"BriefDescription": "Retired load instructions which data sources were HitM responses from shared …
370 …"PublicDescription": "Retired load instructions which data sources were HitM responses from shared…
375 …cription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed i…
385 …"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops r…
391 …"PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops …
396 …"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from loca…
402 …"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from loc…
407 …"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remo…
417 …"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cach…
423 …"PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cac…
428         "BriefDescription": "Retired load instructions whose data sources was remote HITM",
434         "PublicDescription": "Retired load instructions whose data sources was remote HITM.",
449 …"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB d…
460         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
471         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
482         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
488         "PublicDescription": "Retired load instructions with L2 cache hits as data sources.",
493         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
499         "PublicDescription": "Retired load instructions missed L2 cache as data sources.",
504         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
515         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
544         "BriefDescription": "Cacheable and non-cacheable code read requests",
548         "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
584 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
594 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
614 …utstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
660 …ng state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corr…
714 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
774 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
834 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
904 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
964 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1024 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1084 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1144 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1204 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1264 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1324 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …
1384 …t hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or …