x86/skylake/skl-metrics.json

3         "BriefDescription": "C2 residency percent per package",
4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10         "BriefDescription": "C3 residency percent per core",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17         "BriefDescription": "C3 residency percent per package",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24         "BriefDescription": "C6 residency percent per core",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31         "BriefDescription": "C6 residency percent per package",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38         "BriefDescription": "C7 residency percent per core",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45         "BriefDescription": "C7 residency percent per package",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52         "BriefDescription": "Uncore frequency per die [GHZ]",
59         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
82 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
90 …"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the…
95 …CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long seq…
100 …"MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 i…
105 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
110 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
115 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
119 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Mis…
126 …CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an…
130 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
135 …CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching o…
139 …"BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from…
140         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
144 …CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instr…
148 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
149 …"MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.…
153 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
167 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
169         "MetricExpr": "tma_backend_bound - tma_memory_bound",
174 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
178 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
184 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
188 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
189 …"MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) /…
193 …"PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only activ…
206 …"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external m…
208 …o_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread…
212 …"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external …
216 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
217         "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2",
221 …"PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limit…
225 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches…
230 …ion of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-c…
236 …etricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, ma…
240 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
244 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
245 …"MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) /…
249 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
253 …"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due…
259 …CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; …
265 …"MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / t…
273 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
274         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
279 …"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend…
283 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
289 …etric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For exampl…
293 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructi…
295         "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
299 …of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] f…
303 …ion": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU h…
309 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
313 …"BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a res…
318 …the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when …
322 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
327 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
331 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
337 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
341 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
346 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
350 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
355 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
365 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
369 …on": "This metric represents fraction of slots where the CPU was retiring fused instructions -- wh…
374 …on": "This metric represents fraction of slots where the CPU was retiring fused instructions -- wh…
378 …fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require …
379 …"MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_inf…
384 …ots where the CPU was retiring heavy-weight operations -- instructions that require two or more uo…
388 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruct…
389 …"MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / t…
393 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruc…
397 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
401 …"PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative …
404 …"BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower…
411 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
424 …      "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
426 …"MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_ut…
432 …"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch…
437 …"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetc…
440 …"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fet…
446 …"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fe…
449 …"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bott…
454 …"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bot…
457 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
465 …"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset …
470 …"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset…
473 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottleneck…
478 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenec…
481 …"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
486 …"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks…
489 …     "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
494 …ine cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as w…
497 …tch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the…
499 …- (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_…
510 …"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait tim…
513 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
519 …"Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related m…
523 …alse_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (…
532 …"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispre…
539         "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
540 …"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tm…
544 …aining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) a…
547 …"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring catego…
548 … "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIR…
560         "BriefDescription": "Fraction of branches that are non-taken conditionals",
567 …"MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRA…
574 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.COND - BR_INST_RETIRED.NOT_TAKEN) - …
585         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
591         "BriefDescription": "uops Executed per Cycle",
597         "BriefDescription": "Floating Point Operations Per Cycle",
604 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
608 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
611 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
612         "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
625 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
631         "BriefDescription": "Average number of Uops issued by front-end when it issued something",
632         "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
638 …     "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ + 2",
643 …"BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurren…
650 …"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower nu…
656         "BriefDescription": "L2 cache true code cacheline misses per kilo instruction",
662         "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction",
668         "BriefDescription": "Branch instructions per taken branch.",
681 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
687 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
690 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
695 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
698 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
703 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
706 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
711 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
714 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
719 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
722         "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
729 …    "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
736 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
744         "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
751         "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
758 …"BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Pre…
759         "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
765         "BriefDescription": "Instructions per taken branch",
770 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
773         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
779         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
785         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
791         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
797 …iption": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that me…
803 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
809         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
815 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
821         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
827 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
828         "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
833 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculati…
839         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
845 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
851 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (inc…
857         "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
863         "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
869         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
875         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
899 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
905         "BriefDescription": "Un-cacheable retired load per kilo instruction",
911 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
915 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
918 …ription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-s…
924 …on": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-s…
938 …n": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-s…
944 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
945 …UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREA…
950         "BriefDescription": "Average number of uops fetched from DSB per cycle",
956         "BriefDescription": "Average number of uops fetched from MITE per cycle",
962         "BriefDescription": "Instructions per a microcode Assist invocation",
967 …"PublicDescription": "Instructions per a microcode Assist invocation. See Assists tree node for de…
971         "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
982         "BriefDescription": "Average CPU Utilization (percentage)",
1001         "BriefDescription": "Giga Floating Point Operations Per Second",
1006 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
1009 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
1016         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1040 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
1044 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
1061 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
1067         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
1073         "BriefDescription": "The ratio of Executed- by Issued-Uops",
1077 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
1080         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
1086 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
1092         "BriefDescription": "Uops Per Instruction",
1099         "BriefDescription": "Uops per taken branch",
1106 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruct…
1111 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruc…
1115 …"BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the…
1116 …"MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thr…
1120 …CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shor…
1125 …EM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CY…
1129 …e L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access…
1133 …"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses …
1135 ….FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.S…
1139 …"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses…
1143 …"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to …
1144 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_c…
1148 …"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to…
1161 …"BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chang…
1166 …"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chan…
1170 …raction of slots where the CPU was retiring light-weight operations -- instructions that require n…
1171         "MetricExpr": "tma_retiring - tma_heavy_operations",
1176 …CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-…
1180 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1181 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
1185 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1189 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
1191         "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
1198 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
1206 …"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses…
1207 …"MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOC…
1211 …"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misse…
1215 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Cl…
1217         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
1222 …CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the …
1226 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
1227 …"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\…
1231 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
1235 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1236 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1240 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
1251 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
1255 …ion": "This metric represents fraction of slots where the CPU was retiring memory operations -- uo…
1263 …"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by…
1269 …"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched b…
1273 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
1278 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
1282 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
1283 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
1287 …les in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pi…
1291 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1296 …n terms of percentage of([SKL+] injected blend uops out of all Uops Issued -- the Count Domain; [A…
1300 …"BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to …
1305 …CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used ins…
1309 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch in…
1310 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / …
1314 …etric represents fraction of slots where the CPU was retiring branch instructions that were not fu…
1318 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no o…
1323 …action of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for …
1327 …on": "This metric represents the remaining light uops fraction the CPU has executed - remaining me…
1328 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_ins…
1332 …on": "This metric represents the remaining light uops fraction the CPU has executed - remaining me…
1336 …": "This metric estimates fraction of slots the CPU was stalled due to other cases of mispredictio…
1337 …"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_C…
1344 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Mac…
1345 …"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT…
1352 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1357 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1361 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1366 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1370 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads …
1375 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads …
1379 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads …
1384 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads …
1388 …on": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Stor…
1393 …on": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Stor…
1397 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1402 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1406 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1411 …"PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execut…
1415 …his metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simpl…
1420 …his metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simpl…
1424 … estimates fraction of cycles the CPU performance was potentially limited due to Core computation …
1425 … tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALL…
1429 …CPU performance was potentially limited due to Core computation issues (non divider-related).  Two…
1433 …"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any executi…
1438 …action of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, P…
1442 …ption": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle…
1443 …"MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on e…
1447 …CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, …
1451 …iefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle…
1452 …"MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on e…
1456 …CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL,…
1460 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
1474 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
1478 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
1483 …of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUI…
1487 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1493 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1502 …resents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granu…
1506 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1511 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1515 …n": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store …
1520 …CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request be…
1529 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1533 …"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store mis…
1535 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STO…
1539 …CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performa…
1543 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
1551 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
1552         "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
1567 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new bran…
1572 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new bra…
1586         "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)",
1593         "MetricExpr": "(cycles\\-t / el\\-start if has_event(el\\-start) else 0)",
1600         "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)",
1607         "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)",