x86/skylake/frontend.json

7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
30         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
46 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-…
58 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st…
97         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
109 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
120 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
127 …tions that are delivered to the back-end after a front-end stall of at least 16 cycles. During thi…
132 … after an interval where the front-end delivered no uops for a period of 2 cycles which was not in…
143 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
154 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
161 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
166 …r an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was n…
177 …r an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was n…
188 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
195 …tions that are delivered to the back-end after a front-end stall of at least 32 cycles. During thi…
200 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
211 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
222 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
233 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
240 …tions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this…
266 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
274 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is…
303 …re uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
308 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias …
313 …es uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
323 …s' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
333 …s' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
338 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
343 …ps are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
348 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias …
353 …es uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
358 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is…
363 …re uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
368 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
372 …mber of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
391 …' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
401 … includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MI…
406 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
411 …"PublicDescription": "Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are …
425 …"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pip…
431 …"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pi…
445 …"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend…
449 …per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode …
454 …"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocatio…
459 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
474 …"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocatio…
479 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
489         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
499         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",