Lines Matching +full:6 +full:a
3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
20 "Counter": "0,1,2,3,4,5,6,7",
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
29 "Counter": "0,1,2,3,4,5,6,7",
38 "Counter": "0,1,2,3,4,5,6,7",
41 …ge walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is out…
46 …nd level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will res…
47 "Counter": "0,1,2,3,4,5,6,7",
54 …efDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
55 "Counter": "0,1,2,3,4,5,6,7",
62 …ription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
63 "Counter": "0,1,2,3,4,5,6,7",
71 …efDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
72 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
84 …ge walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is out…
89 …"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed …
90 "Counter": "0,1,2,3,4,5,6,7",
97 …misses but second level hits due to an instruction fetch that did not start a page walk. Account f…
98 "Counter": "0,1,2,3,4,5,6,7",
106 "Counter": "0,1,2,3,4,5,6,7",
114 …": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
115 "Counter": "0,1,2,3,4,5,6,7",
123 …iption": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
124 "Counter": "0,1,2,3,4,5,6,7",
133 "Counter": "0,1,2,3,4,5,6,7",
136 …"Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is out…
141 …hat the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
142 "Counter": "0,1,2,3,4,5,6,7",