x86/sandybridge/snb-metrics.json

4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
5         "MetricGroup": "Power",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
12         "MetricGroup": "Power",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
19         "MetricGroup": "Power",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
26         "MetricGroup": "Power",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
33         "MetricGroup": "Power",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
40         "MetricGroup": "Power",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
47         "MetricGroup": "Power",
59         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75         "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
85 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
90 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
101 …ram path; or stalls when the out-of-order part of the machine needs to recover its state from a sp…
110 …-predicted branches. For example; branchy code with lots of miss-predictions might get categorized…
114 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
116         "MetricExpr": "tma_backend_bound - tma_memory_bound",
121 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
130 …than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDE…
136 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_…
140 … loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
149 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
158 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
163         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
178 …-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Fron…
182 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
187 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
191 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
196 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
200 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
205 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
209 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
214 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
218 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
223 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
233 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
237 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
243 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
253         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
265 …efDescription": "Instruction-Level-Parallelism (average number of uops executed when there is exec…
283 …   "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST"
286 …"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
292         "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]",
294         "MetricGroup": "Power;Summary",
298         "BriefDescription": "Average CPU Utilization (percentage)",
304         "BriefDescription": "Average number of utilized CPUs",
310         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
314 …"PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Relat…
321 …egate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
345 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
356         "BriefDescription": "Average Frequency Utilization relative nominal frequency",
358         "MetricGroup": "Power",
362 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
374         "BriefDescription": "The ratio of Executed- by Issued-Uops",
378 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
387 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
405 …tion of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.…
415 ….e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOP…
428 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
429         "MetricExpr": "tma_retiring - tma_heavy_operations",
434 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
440         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
445 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
449 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
454 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
458 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
459 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
463 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
469 …EAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@…
474 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
483 …odes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS.…
492 …-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled native…
496 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
498 …- (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.T…
502 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
512 …-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no r…
516 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
521 …-for-ownership request before the write. Even though store accesses do not typically stall out-of-…