Lines Matching +full:counter +full:- +full:2
3 …with all the following traits: 1. addressing of the format [base + offset], 2. the offset is betwe…
4 "Counter": "0,1,2,3", string
12 "Counter": "0,1,2,3", string
23 "Counter": "0,1,2,3", string
31 "Counter": "0,1,2,3", string
38 "BriefDescription": "Speculative and retired macro-conditional branches.",
39 "Counter": "0,1,2,3", string
46 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
47 "Counter": "0,1,2,3", string
55 "Counter": "0,1,2,3", string
63 "Counter": "0,1,2,3", string
71 "Counter": "0,1,2,3", string
78 "BriefDescription": "Not taken macro-conditional branches.",
79 "Counter": "0,1,2,3", string
86 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
87 "Counter": "0,1,2,3", string
94 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
95 "Counter": "0,1,2,3", string
103 "Counter": "0,1,2,3", string
111 "Counter": "0,1,2,3", string
119 "Counter": "0,1,2,3", string
127 "Counter": "0,1,2,3", string
135 "Counter": "0,1,2,3", string
141 "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
142 "Counter": "0,1,2,3", string
145 "PEBS": "2",
150 "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).",
151 "Counter": "0,1,2,3", string
160 "Counter": "0,1,2,3", string
167 … "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).",
168 "Counter": "0,1,2,3", string
176 …t and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).",
177 "Counter": "0,1,2,3", string
185 "BriefDescription": "Return instructions retired. (Precise Event - PEBS).",
186 "Counter": "0,1,2,3", string
194 "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).",
195 "Counter": "0,1,2,3", string
204 "Counter": "0,1,2,3", string
212 "Counter": "0,1,2,3", string
220 "Counter": "0,1,2,3", string
228 "Counter": "0,1,2,3", string
236 "Counter": "0,1,2,3", string
244 "Counter": "0,1,2,3", string
247 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou…
253 "Counter": "0,1,2,3", string
261 "Counter": "0,1,2,3", string
269 "Counter": "0,1,2,3", string
277 "Counter": "0,1,2,3", string
285 "Counter": "0,1,2,3", string
293 "Counter": "0,1,2,3", string
301 "Counter": "0,1,2,3", string
307 … "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
308 "Counter": "0,1,2,3", string
311 "PEBS": "2",
316 …"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).…
317 "Counter": "0,1,2,3", string
325 …ption": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).",
326 "Counter": "0,1,2,3", string
334 … "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).",
335 "Counter": "0,1,2,3", string
343 … "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).",
344 "Counter": "0,1,2,3", string
353 "Counter": "0,1,2,3", string
361 "Counter": "0,1,2,3", string
370 "Counter": "0,1,2,3", string
378 "Counter": "0,1,2,3", string
386 "Counter": "Fixed counter 2", string
388 …counter. This event can approximate elapsed time while the core was not in a halt state. This even…
394 "Counter": "0,1,2,3", string
403 "Counter": "0,1,2,3", string
411 "Counter": "Fixed counter 1", string
413 …e the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four…
420 "Counter": "Fixed counter 1", string
427 "Counter": "0,1,2,3", string
435 "Counter": "0,1,2,3", string
441 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
442 "Counter": "2", string
443 "CounterMask": "2",
450 …"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-com…
451 "Counter": "0,1,2,3", string
459 … no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be …
460 "Counter": "0,1,2,3", string
468 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
469 "Counter": "2", string
477 …-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry…
478 "Counter": "0,1,2,3", string
487 "Counter": "0,1,2,3", string
495 "Counter": "0,1,2,3", string
503 "Counter": "Fixed counter 0", string
505 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
510 … "BriefDescription": "Number of instructions retired. General Counter - architectural event.",
511 "Counter": "0,1,2,3", string
517 "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
518 "Counter": "1", string
521 "PEBS": "2",
527 "Counter": "0,1,2,3", string
535 "Counter": "0,1,2,3", string
545 "Counter": "0,1,2,3", string
554 "Counter": "0,1,2,3", string
563 …"BriefDescription": "Number of cases where any load ends up with a valid block-code written to the…
564 "Counter": "0,1,2,3", string
572 "Counter": "0,1,2,3", string
580 "Counter": "0,1,2,3", string
587 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
588 "Counter": "0,1,2,3", string
591 …re. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Opti…
597 "Counter": "0,1,2,3", string
606 "Counter": "0,1,2,3", string
613 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
614 "Counter": "0,1,2,3", string
621 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
622 "Counter": "0,1,2,3", string
630 "Counter": "0,1,2,3", string
639 "Counter": "0,1,2,3", string
648 "Counter": "0,1,2,3", string
656 "Counter": "0,1,2,3", string
666 "Counter": "0,1,2,3", string
669 …"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flo…
674 "BriefDescription": "Self-modifying code (SMC) detected.",
675 "Counter": "0,1,2,3", string
678 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
684 "Counter": "0,1,2,3", string
691 "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
692 "Counter": "0,1,2,3", string
699 … "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
700 "Counter": "0,1,2,3", string
704 …uting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mor…
710 "Counter": "0,1,2,3", string
718 "Counter": "0,1,2,3", string
721 …where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and …
726 "BriefDescription": "Resource-related stall cycles.",
727 "Counter": "0,1,2,3", string
735 "Counter": "0,1,2,3", string
743 "Counter": "0,1,2,3", string
751 "Counter": "0,1,2,3", string
759 "Counter": "0,1,2,3", string
766 "BriefDescription": "Cycles stalled due to re-order buffer full.",
767 "Counter": "0,1,2,3", string
775 "Counter": "0,1,2,3", string
783 "Counter": "0,1,2,3", string
791 "Counter": "0,1,2,3", string
799 "Counter": "0,1,2,3", string
807 "Counter": "0,1,2,3", string
815 "Counter": "0,1,2,3", string
823 "Counter": "0,1,2,3", string
831 "Counter": "0,1,2,3", string
839 "Counter": "0,1,2,3", string
850 "Counter": "0,1,2,3", string
858 "Counter": "0,1,2,3", string
866 "Counter": "0,1,2,3", string
875 "Counter": "0,1,2,3", string
883 "Counter": "0,1,2,3", string
892 "Counter": "0,1,2,3", string
899 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.",
900 "Counter": "0,1,2,3", string
908 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.",
909 "Counter": "0,1,2,3", string
917 "Counter": "0,1,2,3", string
926 "Counter": "0,1,2,3", string
934 "Counter": "0,1,2,3", string
943 "Counter": "0,1,2,3", string
951 "Counter": "0,1,2,3", string
960 "Counter": "0,1,2,3", string
967 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
968 "Counter": "0,1,2,3", string
976 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
977 "Counter": "0,1,2,3", string
978 "CounterMask": "2",
985 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
986 "Counter": "0,1,2,3", string
994 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
995 "Counter": "0,1,2,3", string
1003 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1004 "Counter": "0,1,2,3", string
1013 "Counter": "0,1,2,3", string
1016 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1023 "Counter": "0,1,2,3", string
1033 "Counter": "0,1,2,3", string
1042 "BriefDescription": "Actually retired uops. (Precise Event - PEBS).",
1043 "Counter": "0,1,2,3", string
1047 "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)",
1053 "Counter": "0,1,2,3", string
1062 "BriefDescription": "Retirement slots used. (Precise Event - PEBS).",
1063 "Counter": "0,1,2,3", string
1067 …- meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determini…
1073 "Counter": "0,1,2,3", string
1083 "Counter": "0,1,2,3", string