Lines Matching +full:3 +full:at
4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
82 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
112 "Counter": "0,1,2,3,4,5,6,7",
116 …dicts the destination of the branch. When the misprediction is discovered at execution, all the i…
121 "Counter": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3,4,5,6,7",
141 "Counter": "0,1,2,3,4,5,6,7",
151 "Counter": "0,1,2,3,4,5,6,7",
161 "Counter": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3,4,5,6,7",
181 "Counter": "0,1,2,3,4,5,6,7",
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
220 …es duty off periods the processor is 'halted'. The counter update is done at a lower clock rate t…
226 "Counter": "0,1,2,3,4,5,6,7",
243 "Counter": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
323 "Counter": "0,1,2,3,4,5,6,7",
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
334 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
341 "Counter": "0,1,2,3,4,5,6,7",
350 "Counter": "0,1,2,3,4,5,6,7",
360 "Counter": "0,1,2,3",
369 "Counter": "0,1,2,3",
387 "Counter": "0,1,2,3,4,5,6,7",
396 "Counter": "0,1,2,3,4,5,6,7",
414 "Counter": "0,1,2,3,4,5,6,7",
425 "Counter": "0,1,2,3,4,5,6,7",
435 "Counter": "0,1,2,3,4,5,6,7",
446 "Counter": "0,1,2,3,4,5,6,7",
455 "Counter": "0,1,2,3,4,5,6,7",
464 "Counter": "0,1,2,3,4,5,6,7",
473 "Counter": "0,1,2,3",
482 "Counter": "0,1,2,3",
491 "Counter": "0,1,2,3",
500 "Counter": "0,1,2,3",
509 "Counter": "0,1,2,3",
513 …"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream…
519 "Counter": "0,1,2,3",
529 "Counter": "0,1,2,3",
538 "Counter": "0,1,2,3,4,5,6,7",
549 "Counter": "0,1,2,3,4,5,6,7",
558 "Counter": "0,1,2,3,4,5,6,7",
567 "Counter": "0,1,2,3,4,5,6,7",
576 "Counter": "0,1,2,3,4,5,6,7",
585 "Counter": "0,1,2,3,4,5,6,7",
593 "Counter": "0,1,2,3,4,5,6,7",
602 "Counter": "0,1,2,3,4,5,6,7",
614 "Counter": "0,1,2,3,4,5,6,7",
623 "Counter": "Fixed counter 3",
625 … TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
631 "Counter": "0,1,2,3,4,5,6,7",
640 "Counter": "0,1,2,3",
649 "Counter": "0,1,2,3,4,5,6,7",
652 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
658 "Counter": "0,1,2,3,4,5,6,7",
661 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
666 "BriefDescription": "Number of uops executed on port 2 and 3",
667 "Counter": "0,1,2,3,4,5,6,7",
670 …r-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (R…
676 "Counter": "0,1,2,3,4,5,6,7",
679 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
685 "Counter": "0,1,2,3,4,5,6,7",
688 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
694 "Counter": "0,1,2,3,4,5,6,7",
697 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
703 "Counter": "0,1,2,3,4,5,6,7",
706 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
712 "Counter": "0,1,2,3,4,5,6,7",
720 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
721 "Counter": "0,1,2,3,4,5,6,7",
725 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
730 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
731 "Counter": "0,1,2,3,4,5,6,7",
735 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
740 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
741 "Counter": "0,1,2,3,4,5,6,7",
742 "CounterMask": "3",
745 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
750 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
751 "Counter": "0,1,2,3,4,5,6,7",
755 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
760 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
761 "Counter": "0,1,2,3,4,5,6,7",
765 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
770 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
771 "Counter": "0,1,2,3,4,5,6,7",
775 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
780 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
781 "Counter": "0,1,2,3,4,5,6,7",
782 "CounterMask": "3",
785 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
790 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
791 "Counter": "0,1,2,3,4,5,6,7",
795 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
801 "Counter": "0,1,2,3,4,5,6,7",
812 "Counter": "0,1,2,3,4,5,6,7",
820 "Counter": "0,1,2,3,4,5,6,7",
829 "Counter": "0,1,2,3,4,5,6,7",
838 "Counter": "0,1,2,3,4,5,6,7",
848 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
849 "Counter": "0,1,2,3,4,5,6,7",
858 "Counter": "0,1,2,3,4,5,6,7",
867 "Counter": "0,1,2,3,4,5,6,7",
878 "Counter": "0,1,2,3,4,5,6,7",