x86/rocketlake/frontend.json

7 …is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a …
12 …"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is al…
16 …Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the …
48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
60 …that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Cr…
72 …"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true mis…
77         "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
84 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
89         "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
96 …"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
245 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
249 …ption": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The…
254 …"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts…
258 …"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I)…
263 …"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Count…
267 …"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I…
272 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
276 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
281 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
285 …ption": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The…
290 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
294 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
304 …"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue …
314 …the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (I…
319 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
323 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
333 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
343 …the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (I…
348         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
352 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
362 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
382 …he total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops wil…
391 …"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (…
401 …tion": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (I…
412 …number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (I…