Lines Matching +full:2 +full:a

3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4         "Counter": "0,1,2,3,4,5,6,7",
13         "Counter": "0,1,2,3",
22 …    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
23         "Counter": "0,1,2,3",
27 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
34         "Counter": "0,1,2,3,4,5,6,7",
42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
43         "Counter": "0,1,2,3",
46 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
52         "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
53         "Counter": "0,1,2,3",
56 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
62 …cription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
63         "Counter": "0,1,2,3,4,5,6,7",
66 … missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ…
72         "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
73         "Counter": "0,1,2,3",
76 …2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and…
82 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
83         "Counter": "0,1,2,3,4,5,6,7",
92         "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
93         "Counter": "0,1,2,3",
96 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
103         "Counter": "0,1,2,3,4,5,6,7",
106 …ge walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.  A PMH page walk is out…
112 …   "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
113         "Counter": "0,1,2,3",
116 …"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Pa…
122 …nd level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will res…
123         "Counter": "0,1,2,3,4,5,6,7",
132         "Counter": "0,1,2,3",
135 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
141         "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
142         "Counter": "0,1,2,3",
146 …": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
152 …efDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
153         "Counter": "0,1,2,3,4,5,6,7",
161 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
162         "Counter": "0,1,2,3",
165 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
171         "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
172         "Counter": "0,1,2,3",
175 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
181 …ription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
182         "Counter": "0,1,2,3,4,5,6,7",
185 … missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Inclu…
191         "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
192         "Counter": "0,1,2,3",
195 …2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB an…
201 …efDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
202         "Counter": "0,1,2,3,4,5,6,7",
211         "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
212         "Counter": "0,1,2,3",
215 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
222         "Counter": "0,1,2,3,4,5,6,7",
225 …ge walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is out…
231         "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
232         "Counter": "0,1,2,3",
235 …"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Mis…
241 …"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed …
242         "Counter": "0,1,2,3,4,5,6,7",
250 …misses but second level hits due to an instruction fetch that did not start a page walk. Account f…
251         "Counter": "0,1,2,3,4,5,6,7",
260         "Counter": "0,1,2,3",
269 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction f…
270         "Counter": "0,1,2,3",
274 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instru…
281         "Counter": "0,1,2,3,4,5,6,7",
290 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
291         "Counter": "0,1,2,3",
294 …caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of…
300 …": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
301         "Counter": "0,1,2,3,4,5,6,7",
304 … missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Inclu…
310 …      "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
311         "Counter": "0,1,2,3",
314 …2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and…
320 …iption": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
321         "Counter": "0,1,2,3,4,5,6,7",
330         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
331         "Counter": "0,1,2,3",
334 …caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of…
341         "Counter": "0,1,2,3,4,5,6,7",
344 …"Counts the number of page walks outstanding for iside in PMH every cycle.  A PMH page walk is out…
351         "Counter": "0,1,2,3",
360 …hat the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
361         "Counter": "0,1,2,3,4,5,6,7",