Lines Matching +full:6 +full:- +full:3
4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
54 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 "Counter": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3,4,5,6,7",
115 "Counter": "0,1,2,3,4,5,6,7",
124 "Counter": "0,1,2,3,4,5,6,7",
135 "Counter": "0,1,2,3,4,5,6,7",
144 "Counter": "0,1,2,3,4,5,6,7",
155 "Counter": "0,1,2,3,4,5,6,7",
164 "Counter": "0,1,2,3,4,5,6,7",
174 "Counter": "0,1,2,3,4,5,6,7",
183 "Counter": "0,1,2,3,4,5,6,7",
194 "Counter": "0,1,2,3,4,5,6,7",
203 "Counter": "0,1,2,3,4,5,6,7",
214 "Counter": "0,1,2,3,4,5,6,7",
225 "Counter": "0,1,2,3,4,5,6,7",
228 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
234 "Counter": "0,1,2,3,4,5,6,7",
244 "Counter": "0,1,2,3,4,5,6,7",
254 "Counter": "0,1,2,3,4,5,6,7",
263 "Counter": "0,1,2,3,4,5,6,7",
274 "Counter": "0,1,2,3,4,5,6,7",
283 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
284 "Counter": "0,1,2,3,4,5,6,7",
294 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise …
295 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
325 "Counter": "0,1,2,3,4,5,6,7",
335 "Counter": "0,1,2,3,4,5,6,7",
343 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
344 "Counter": "0,1,2,3,4,5,6,7",
348 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
355 "Counter": "0,1,2,3,4,5,6,7",
364 "Counter": "0,1,2,3,4,5,6,7",
375 "Counter": "0,1,2,3,4,5,6,7",
385 "Counter": "0,1,2,3,4,5,6,7",
395 "Counter": "0,1,2,3,4,5,6,7",
404 "Counter": "0,1,2,3,4,5,6,7",
415 "Counter": "0,1,2,3,4,5,6,7",
425 "Counter": "0,1,2,3,4,5,6,7",
429 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
436 "Counter": "0,1,2,3,4,5,6,7",
445 "Counter": "0,1,2,3,4,5,6,7",
454 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
455 "Counter": "0,1,2,3,4,5,6,7",
458 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
464 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
465 "Counter": "0,1,2,3,4,5,6,7",
468 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
475 "Counter": "0,1,2,3,4,5,6,7",
493 "Counter": "0,1,2,3,4,5,6,7",
501 "Counter": "0,1,2,3,4,5,6,7",
511 "Counter": "0,1,2,3,4,5,6,7",
521 "Counter": "0,1,2,3,4,5,6,7",
530 "Counter": "0,1,2,3,4,5,6,7",
541 "Counter": "0,1,2,3,4,5,6,7",
544 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
568 "Counter": "0,1,2,3,4,5,6,7",
578 "Counter": "0,1,2,3,4,5,6,7",
605 "Counter": "0,1,2,3,4,5,6,7",
613 "Counter": "0,1,2,3,4,5,6,7",
622 "Counter": "0,1,2,3",
632 "Counter": "0,1,2,3",
642 "Counter": "0,1,2,3,4,5,6,7",
652 "Counter": "0,1,2,3",
662 "Counter": "0,1,2,3",
672 "Counter": "0,1,2,3,4,5,6,7",
682 "Counter": "0,1,2,3,4,5,6,7",
691 …"BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station…
692 "Counter": "0,1,2,3,4,5,6,7",
701 "Counter": "0,1,2,3,4,5,6,7",
710 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
711 "Counter": "0,1,2,3,4,5,6,7",
713 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
714 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
721 "Counter": "0,1,2,3,4,5,6,7",
731 "Counter": "0,1,2,3,4,5,6,7",
741 "Counter": "0,1,2,3,4,5,6,7",
752 "Counter": "0,1,2,3,4,5,6,7",
762 "Counter": "0,1,2,3",
780 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
784 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
791 "Counter": "0,1,2,3,4,5,6,7",
798 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
799 "Counter": "0,1,2,3,4,5,6,7",
803 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
809 "Counter": "0,1,2,3,4,5,6,7",
819 "Counter": "0,1,2,3,4,5,6,7",
829 "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
840 "Counter": "0,1,2,3,4,5,6,7",
844 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
851 "Counter": "0,1,2,3,4,5,6,7",
863 "Counter": "0,1,2,3,4,5,6,7",
873 "Counter": "0,1,2,3,4,5,6,7",
883 "Counter": "0,1,2,3,4,5,6,7",
894 "Counter": "0,1,2,3,4,5,6,7",
897 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
904 "Counter": "0,1,2,3,4,5,6,7",
913 "Counter": "0,1,2,3,4,5,6,7",
921 "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
922 "Counter": "0,1,2,3,4,5,6,7",
925 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
931 "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
932 "Counter": "0,1,2,3,4,5,6,7",
935 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
942 "Counter": "0,1,2,3,4,5,6,7",
951 "Counter": "0,1,2,3,4,5,6,7",
960 "Counter": "0,1,2,3,4,5,6,7",
969 "Counter": "0,1,2,3,4,5,6,7",
978 "Counter": "0,1,2,3,4,5,6,7",
987 "Counter": "0,1,2,3",
997 "Counter": "0,1,2,3,4,5,6,7",
1006 "Counter": "0,1,2,3",
1016 "Counter": "0,1,2,3,4,5,6,7",
1025 "Counter": "0,1,2,3",
1035 "Counter": "0,1,2,3",
1038 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
1045 "Counter": "0,1,2,3,4,5,6,7",
1049 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
1056 "Counter": "0,1,2,3,4,5,6,7",
1057 "CounterMask": "6",
1060 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
1067 "Counter": "0,1,2,3,4,5,6,7",
1070 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
1077 "Counter": "0,1,2,3,4,5,6,7",
1085 "Counter": "0,1,2,3,4,5,6,7",
1097 "Counter": "0,1,2,3,4,5,6,7",
1106 "Counter": "0,1,2,3,4,5,6,7",
1114 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
1115 "Counter": "0,1,2,3,4,5,6,7",
1124 "Counter": "0,1,2,3,4,5,6,7",
1133 "Counter": "0,1,2,3,4,5,6,7",
1141 "BriefDescription": "Self-modifying code (SMC) detected.",
1142 "Counter": "0,1,2,3,4,5,6,7",
1145 … "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1152 "Counter": "0,1,2,3,4,5,6,7",
1162 "Counter": "0,1,2,3,4,5,6,7",
1171 "Counter": "0,1,2,3,4,5,6,7",
1181 "Counter": "0,1,2,3,4,5,6,7",
1189 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
1190 "Counter": "0,1,2,3,4,5,6,7",
1193 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
1203 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
1213 …speculative operations that were issued but not retired as well as the out-of-order engine recover…
1220 "Counter": "0,1,2,3,4,5,6,7",
1228 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1229 "Counter": "Fixed counter 3",
1231 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1237 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1238 "Counter": "0,1,2,3,4,5,6,7",
1241 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1248 "Counter": "0,1,2,3,4,5,6,7",
1257 "Counter": "0,1,2,3,4,5,6,7",
1266 "Counter": "0,1,2,3,4,5,6,7",
1275 "Counter": "0,1,2,3,4,5,6,7",
1284 "Counter": "0,1,2,3,4,5,6,7",
1293 "Counter": "0,1,2,3,4,5,6,7",
1302 "Counter": "0,1,2,3,4,5,6,7",
1310 "Counter": "0,1,2,3,4,5,6,7",
1319 "Counter": "0,1,2,3,4,5,6,7",
1327 "Counter": "0,1,2,3,4,5,6,7",
1335 …y cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to …
1336 "Counter": "0,1,2,3,4,5,6,7",
1345 "Counter": "0,1,2,3,4,5,6,7",
1354 "Counter": "0,1,2,3,4,5,6,7",
1363 "Counter": "0,1,2,3,4,5,6,7",
1372 "Counter": "0,1,2,3,4,5,6,7",
1380 "Counter": "0,1,2,3,4,5,6,7",
1388 "Counter": "0,1,2,3,4,5,6,7",
1397 "Counter": "0,1,2,3,4,5,6,7",
1406 "Counter": "0,1,2,3,4,5,6,7",
1415 "Counter": "0,1,2,3,4,5,6,7",
1424 "Counter": "0,1,2,3,4,5,6,7",
1433 "Counter": "0,1,2,3,4,5,6,7",
1442 "Counter": "0,1,2,3,4,5,6,7",
1452 "Counter": "0,1,2,3,4,5,6,7",
1461 "Counter": "0,1,2,3,4,5,6,7",
1470 "Counter": "0,1,2,3,4,5,6,7",
1479 "Counter": "0,1,2,3,4,5,6,7",
1487 "Counter": "0,1,2,3,4,5,6,7",
1494 "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
1495 "Counter": "0,1,2,3",
1498 … "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
1505 "Counter": "0,1,2,3,4,5,6,7",
1515 "Counter": "0,1,2,3,4,5,6,7",
1524 "BriefDescription": "Uops executed on ports 2, 3 and 10",
1525 "Counter": "0,1,2,3,4,5,6,7",
1528 "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
1535 "Counter": "0,1,2,3,4,5,6,7",
1545 "Counter": "0,1,2,3,4,5,6,7",
1554 "BriefDescription": "Uops executed on port 6",
1555 "Counter": "0,1,2,3,4,5,6,7",
1558 "PublicDescription": "Number of uops dispatch to execution port 6.",
1565 "Counter": "0,1,2,3,4,5,6,7",
1575 "Counter": "0,1,2,3,4,5,6,7",
1584 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1585 "Counter": "0,1,2,3,4,5,6,7",
1589 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1595 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1596 "Counter": "0,1,2,3,4,5,6,7",
1600 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1606 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1607 "Counter": "0,1,2,3,4,5,6,7",
1608 "CounterMask": "3",
1611 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1617 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1618 "Counter": "0,1,2,3,4,5,6,7",
1622 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1628 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1629 "Counter": "0,1,2,3,4,5,6,7",
1633 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1639 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1640 "Counter": "0,1,2,3,4,5,6,7",
1644 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1650 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1651 "Counter": "0,1,2,3,4,5,6,7",
1652 "CounterMask": "3",
1655 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1661 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1662 "Counter": "0,1,2,3,4,5,6,7",
1666 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1673 "Counter": "0,1,2,3,4,5,6,7",
1684 "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1685 "Counter": "0,1,2,3,4,5,6,7",
1694 "Counter": "0,1,2,3,4,5,6,7",
1704 "Counter": "0,1,2,3,4,5,6,7",
1707 …he number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops a…
1713 "Counter": "0,1,2,3,4,5,6,7",
1723 "Counter": "0,1,2,3,4,5,6,7",
1733 "Counter": "0,1,2,3,4,5,6,7",
1741 "Counter": "0,1,2,3,4,5,6,7",
1752 "Counter": "0,1,2,3,4,5,6,7",
1755 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1762 "Counter": "0,1,2,3,4,5,6,7",
1770 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This…
1771 "Counter": "0,1,2,3,4,5,6,7",
1780 "Counter": "0,1,2,3,4,5,6,7",
1790 …orrelates with higher performance for example, as measured by the instructions-per-cycle metric.",
1791 "Counter": "0,1,2,3,4,5,6,7",
1794 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…
1801 "Counter": "0,1,2,3,4,5,6,7",
1813 "Counter": "0,1,2,3,4,5,6,7",