x86/meteorlake/frontend.json

17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
27 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
42         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
46 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
72 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
85 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
139         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
146 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
152 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
159 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
165 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
172 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
178         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
185 …ter an interval where the front-end delivered no uops for a period of at least 2 cycles which was …
191 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
198 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
204 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
211 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
217 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
224 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
230 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
237 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
243 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
250 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
256 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
263 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
269 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
276 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
341 …s line or being redirected by a jump and the instruction cache registers bytes are not present. -",
478 …hen no operation was delivered to the back-end pipeline due to instruction fetch limitations when …
482 …-end pipeline due to instruction fetch limitations when the back-end could have accepted more oper…
493 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
499 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
505 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
515 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
526 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
532 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
538 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…