x86/lunarlake/pipeline.json

8 …"Counts the total number of instructions in which the instruction pointer (IP) of the processor is…
28 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
43         "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
54 …frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep…
60 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C…
72 …frequency may change from time to time due to power or thermal throttling. For this reason, this e…
77         "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
88 …frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency…
94         "BriefDescription": "Counts the number of unhalted reference clock cycles",
98 …T instruction. This event is not affected by core frequency changes and increments at a fixed freq…
108 …frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency…
114         "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
125 …frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep…
131 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C…
143 …frequency may change from time to time due to power or thermal throttling. For this reason, this e…
157         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
161 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
176         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
181 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
186 … because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forw…
226 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
230 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
236 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
239 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
245 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
249 …gical processor. The event increments by machine-width of the narrowest pipeline as employed by th…
325 …orrelates with higher performance  for example, as measured by the instructions-per-cycle metric.",
329 …he instructions-per-cycle metric. Software can use this event as the numerator for the Retiring me…