x86/lunarlake/pipeline.json

28 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
54 …e. It is counted on a dedicated fixed counter, leaving the programmable counters available for oth…
125 …e. It is counted on a dedicated fixed counter, leaving the programmable counters available for oth…
157         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
161 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
176         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
181 …- an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside…
186 … because its address partially overlaps with an older store (size mismatch) - unknown_sta/bad_forw…
226 … the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end r…
230 …-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution…
236 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
239 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
245 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
249 …cal processor. The event increments by machine-width of the narrowest pipeline as employed by the …
325 …orrelates with higher performance  for example, as measured by the instructions-per-cycle metric.",
329 … instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metr…