x86/jaketown/jkt-metrics.json

3         "BriefDescription": "C2 residency percent per package",
4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10         "BriefDescription": "C3 residency percent per core",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17         "BriefDescription": "C3 residency percent per package",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24         "BriefDescription": "C6 residency percent per core",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31         "BriefDescription": "C6 residency percent per package",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38         "BriefDescription": "C7 residency percent per core",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45         "BriefDescription": "C7 residency percent per package",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52         "BriefDescription": "Uncore frequency per die [GHZ]",
59         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
75         "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
80 …processor core where the out-of-order scheduler dispatches ready uops into their respective execut…
85 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
90 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
101 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
110 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
114 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
116         "MetricExpr": "tma_backend_bound - tma_memory_bound",
121 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
136 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_…
149 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
158 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
163         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
178 …he CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB mi…
182 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
187 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
191 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
196 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
200 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
205 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
209 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
214 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
218 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
223 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
227 …"BriefDescription": "This category represents fraction of slots where the processor's Frontend und…
233 …processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor c…
237 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
243 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
247 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
253         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
259         "BriefDescription": "Floating Point Operations Per Cycle",
265 …cription": "Instruction-Level-Parallelism (average number of uops executed when there is execution…
317         "BriefDescription": "Giga Floating Point Operations Per Second",
321 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
324 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
331         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
355 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
359 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
382 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
388         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
394         "BriefDescription": "The ratio of Executed- by Issued-Uops",
398 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
401         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
407 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
413         "BriefDescription": "Uops Per Instruction",
448 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
449         "MetricExpr": "tma_retiring - tma_heavy_operations",
454 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
460         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
465 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
469 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
474 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
478 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
479 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
483 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
489 …EAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@…
494 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
512 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
516 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
518 …- (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_thread_ipc > 1.8 else cpu@UOPS_DISPATCHED.T…
522 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
532 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
536 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
541 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …