x86/ivytown/ivt-metrics.json

3         "BriefDescription": "C2 residency percent per package",
4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10         "BriefDescription": "C3 residency percent per core",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17         "BriefDescription": "C3 residency percent per package",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24         "BriefDescription": "C6 residency percent per core",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31         "BriefDescription": "C6 residency percent per package",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38         "BriefDescription": "C7 residency percent per core",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45         "BriefDescription": "C7 residency percent per package",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
52         "BriefDescription": "Uncore frequency per die [GHZ]",
59         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
102         "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
107 …processor core where the out-of-order scheduler dispatches ready uops into their respective execut…
112 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
117 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
128 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
137 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
143         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
147 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
157 …sted accesses occur when data written by one Logical Processor are read by another Logical Process…
161 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
163         "MetricExpr": "tma_backend_bound - tma_memory_bound",
168 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
172 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
178 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
193 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_…
202 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
215 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
224 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
228 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
233 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
242 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
257         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
272 …he CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB mi…
276 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
281 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
285 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
290 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
294 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
299 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
303 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
308 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
312 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
317 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
321 …"BriefDescription": "This category represents fraction of slots where the processor's Frontend und…
327 …processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor c…
331 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
337 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
342         "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_itlb_misses",
349 …"BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower…
356 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
363 …"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
369         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
375         "BriefDescription": "Floating Point Operations Per Cycle",
381 …cription": "Instruction-Level-Parallelism (average number of uops executed when there is execution…
395 …"BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower nu…
401         "BriefDescription": "Branch instructions per taken branch.",
414 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
419 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
422         "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
429 …    "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
436         "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
443         "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
450         "BriefDescription": "Instructions per taken branch",
455 …"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_…
458         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
464         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
470         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
476 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
482         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
488         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
494         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
500         "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
506         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
512         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
536 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
543 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
548 …cription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least…
558 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
595         "BriefDescription": "Giga Floating Point Operations Per Second",
599 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
602 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
609         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
633 …y (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)"
637 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
660 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
666         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
672         "BriefDescription": "The ratio of Executed- by Issued-Uops",
676 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
679         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
685 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
691         "BriefDescription": "Uops Per Instruction",
698         "BriefDescription": "Uops per taken branch",
715 …"MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVI…
719 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
724 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_t…
761 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
762         "MetricExpr": "tma_retiring - tma_heavy_operations",
767 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
773 …"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.P…
802         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
807 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
811 …as likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM…
816 …- DRAM ([SPR-HBM] and/or HBM).  The underlying heuristic assumes that a similar off-core traffic i…
820 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
821 …EAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
825 …e the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM…
831 …CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS…
836 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
850 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
854 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
863 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
885 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
890 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
894 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
899 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
903 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
908 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: U…
921 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
923 …- (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_thread_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2…
927 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
931 … fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL…
932 …SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYC…
936 …ted no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherw…
940 …on of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Proce…
941 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECU…
945 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
949 …ts fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Proce…
950 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECU…
954 …per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwi…
958 …ion of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Proce…
972 …r sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocati…
981 …ystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocati…
991 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
995 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1001 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
1010 …resents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granu…
1014 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1019 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
1023 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
1028 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
1037 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
1043 …"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
1047 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…