Lines Matching full:cycles
14 "BriefDescription": "Cycles when divider is busy executing divide operations",
18 …"PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=…
343 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
353 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
369 "BriefDescription": "Reference cycles when the core is not in halt state.",
376 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
380 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
386 …"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalte…
394 "BriefDescription": "Core cycles when the thread is not in halt state.",
402 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
405 …"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt sta…
410 "BriefDescription": "Thread cycles when thread is not in halt state",
414 …"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. …
419 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
423 …"PublicDescription": "Core cycles when at least one thread on the physical core is not in halt sta…
427 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
436 "BriefDescription": "Cycles with pending L1 cache miss loads.",
441 … "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.",
446 "BriefDescription": "Cycles while L2 cache miss load* is outstanding.",
455 "BriefDescription": "Cycles with pending L2 cache miss loads.",
460 "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.",
465 "BriefDescription": "Cycles with pending memory loads.",
470 "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.",
475 "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
559 "BriefDescription": "Stall cycles because IQ is full",
563 "PublicDescription": "Stall cycles due to IQ is full.",
601 …"BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RA…
611 …"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear even…
675 "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder",
680 … "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
685 "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder",
690 "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
755 "BriefDescription": "Resource-related stall cycles",
759 "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.",
764 "BriefDescription": "Cycles stalled due to re-order buffer full.",
772 "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
780 …"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining for…
784 …"PublicDescription": "Cycles stalled due to no store buffers available (not including draining for…
798 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
802 "PublicDescription": "Cycles the RS is empty for the thread.",
818 "BriefDescription": "Cycles per thread when uops are dispatched to port 0",
822 "PublicDescription": "Cycles which a Uop is dispatched on port 0.",
828 "BriefDescription": "Cycles per core when uops are dispatched to port 0",
832 "PublicDescription": "Cycles per core when uops are dispatched to port 0.",
837 "BriefDescription": "Cycles per thread when uops are dispatched to port 1",
841 "PublicDescription": "Cycles which a Uop is dispatched on port 1.",
847 "BriefDescription": "Cycles per core when uops are dispatched to port 1",
851 "PublicDescription": "Cycles per core when uops are dispatched to port 1.",
856 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2",
860 "PublicDescription": "Cycles which a Uop is dispatched on port 2.",
874 "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3",
878 "PublicDescription": "Cycles which a Uop is dispatched on port 3.",
884 "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3",
888 "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.",
893 "BriefDescription": "Cycles per thread when uops are dispatched to port 4",
897 "PublicDescription": "Cycles which a Uop is dispatched on port 4.",
903 "BriefDescription": "Cycles per core when uops are dispatched to port 4",
907 "PublicDescription": "Cycles per core when uops are dispatched to port 4.",
912 "BriefDescription": "Cycles per thread when uops are dispatched to port 5",
916 "PublicDescription": "Cycles which a Uop is dispatched on port 5.",
922 "BriefDescription": "Cycles per core when uops are dispatched to port 5",
926 "PublicDescription": "Cycles per core when uops are dispatched to port 5.",
940 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core",
945 … "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
950 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core",
955 … "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
960 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core",
965 … "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
970 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core",
975 … "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
980 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core",
985 "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
990 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
995 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1000 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1005 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1010 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1015 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1020 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1025 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1030 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
1044 …number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.",
1053 …Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.",
1059 …"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservatio…
1065 …"PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservati…
1097 …"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservatio…
1103 …"PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservati…
1118 "BriefDescription": "Cycles without actually retired uops.",
1137 "BriefDescription": "Cycles without actually retired uops.",
1147 "BriefDescription": "Cycles with less than 10 actually retired uops.",