x86/icelakex/pipeline.json

4         "Counter": "0,1,2,3,4,5,6,7",
13 …      "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
14         "Counter": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
23         "Counter": "0,1,2,3,4,5,6,7",
32         "Counter": "0,1,2,3,4,5,6,7",
42         "Counter": "0,1,2,3,4,5,6,7",
52         "Counter": "0,1,2,3,4,5,6,7",
62         "Counter": "0,1,2,3,4,5,6,7",
72         "Counter": "0,1,2,3,4,5,6,7",
82         "Counter": "0,1,2,3,4,5,6,7",
92         "Counter": "0,1,2,3,4,5,6,7",
102         "Counter": "0,1,2,3,4,5,6,7",
112         "Counter": "0,1,2,3,4,5,6,7",
116 …ll the retired branch instructions that were mispredicted by the processor. A branch misprediction…
121         "Counter": "0,1,2,3,4,5,6,7",
131         "Counter": "0,1,2,3,4,5,6,7",
141         "Counter": "0,1,2,3,4,5,6,7",
151         "Counter": "0,1,2,3,4,5,6,7",
161         "Counter": "0,1,2,3,4,5,6,7",
171         "Counter": "0,1,2,3,4,5,6,7",
181         "Counter": "0,1,2,3,4,5,6,7",
185 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
191         "Counter": "0,1,2,3,4,5,6,7",
194 …t distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes …
200         "Counter": "0,1,2,3,4,5,6,7",
209         "Counter": "0,1,2,3,4,5,6,7",
212 …ose in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructio…
220 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
226         "Counter": "0,1,2,3,4,5,6,7",
237 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
243         "Counter": "0,1,2,3,4,5,6,7",
246 …a halt state. The thread enters the halt state when it is running the HLT instruction. The core fr…
269         "Counter": "0,1,2,3,4,5,6,7",
296         "Counter": "0,1,2,3,4,5,6,7",
305         "Counter": "0,1,2,3,4,5,6,7",
314         "Counter": "0,1,2,3,4,5,6,7",
317 …"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Re…
323         "Counter": "0,1,2,3,4,5,6,7",
326 …"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and …
332         "Counter": "0,1,2,3,4,5,6,7",
341         "Counter": "0,1,2,3,4,5,6,7",
350         "Counter": "0,1,2,3,4,5,6,7",
363 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
368         "BriefDescription": "Instruction decoders utilized in a cycle",
372 …"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline…
381 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
387         "Counter": "0,1,2,3,4,5,6,7",
391 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
396         "Counter": "0,1,2,3,4,5,6,7",
404 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
408 …"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of sa…
413 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
414         "Counter": "0,1,2,3,4,5,6,7",
418 …ription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buf…
424         "Counter": "0,1,2,3,4,5,6,7",
434 …"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear til…
435         "Counter": "0,1,2,3,4,5,6,7",
438 …"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the …
444         "Counter": "0,1,2,3,4,5,6,7",
453         "Counter": "0,1,2,3,4,5,6,7",
470 …"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwar…
474 … prevented for a load operation. The most common case is a load blocked due to the address of memo…
483 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies due …
527         "Counter": "0,1,2,3,4,5,6,7",
538         "Counter": "0,1,2,3,4,5,6,7",
541 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
547         "Counter": "0,1,2,3,4,5,6,7",
556         "Counter": "0,1,2,3,4,5,6,7",
565         "Counter": "0,1,2,3,4,5,6,7",
574         "Counter": "0,1,2,3,4,5,6,7",
582         "Counter": "0,1,2,3,4,5,6,7",
591         "Counter": "0,1,2,3,4,5,6,7",
603         "Counter": "0,1,2,3,4,5,6,7",
614 …top-level metrics of the TMA method. This architectural event is counted on a designated fixed cou…
620         "Counter": "0,1,2,3,4,5,6,7",
638         "Counter": "0,1,2,3,4,5,6,7",
647         "Counter": "0,1,2,3,4,5,6,7",
656         "Counter": "0,1,2,3,4,5,6,7",
665         "Counter": "0,1,2,3,4,5,6,7",
674         "Counter": "0,1,2,3,4,5,6,7",
682         "BriefDescription": "Number of uops executed on port 6",
683         "Counter": "0,1,2,3,4,5,6,7",
686 …, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
692         "Counter": "0,1,2,3,4,5,6,7",
701         "Counter": "0,1,2,3,4,5,6,7",
711         "Counter": "0,1,2,3,4,5,6,7",
721         "Counter": "0,1,2,3,4,5,6,7",
731         "Counter": "0,1,2,3,4,5,6,7",
741         "Counter": "0,1,2,3,4,5,6,7",
751         "Counter": "0,1,2,3,4,5,6,7",
761         "Counter": "0,1,2,3,4,5,6,7",
771         "Counter": "0,1,2,3,4,5,6,7",
781         "Counter": "0,1,2,3,4,5,6,7",
792         "Counter": "0,1,2,3,4,5,6,7",
800         "Counter": "0,1,2,3,4,5,6,7",
809         "Counter": "0,1,2,3,4,5,6,7",
818         "Counter": "0,1,2,3,4,5,6,7",
829         "Counter": "0,1,2,3,4,5,6,7",
838         "Counter": "0,1,2,3,4,5,6,7",
847         "Counter": "0,1,2,3,4,5,6,7",
858         "Counter": "0,1,2,3,4,5,6,7",