Lines Matching +full:3 +full:at
4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
52 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
72 "Counter": "0,1,2,3,4,5,6,7",
82 "Counter": "0,1,2,3,4,5,6,7",
92 "Counter": "0,1,2,3,4,5,6,7",
102 "Counter": "0,1,2,3,4,5,6,7",
112 "Counter": "0,1,2,3,4,5,6,7",
116 …dicts the destination of the branch. When the misprediction is discovered at execution, all the i…
121 "Counter": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3,4,5,6,7",
141 "Counter": "0,1,2,3,4,5,6,7",
151 "Counter": "0,1,2,3,4,5,6,7",
161 "Counter": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3,4,5,6,7",
181 "Counter": "0,1,2,3,4,5,6,7",
191 "Counter": "0,1,2,3,4,5,6,7",
200 "Counter": "0,1,2,3,4,5,6,7",
209 "Counter": "0,1,2,3,4,5,6,7",
220 …es duty off periods the processor is 'halted'. The counter update is done at a lower clock rate t…
226 "Counter": "0,1,2,3,4,5,6,7",
243 "Counter": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
260 "Counter": "0,1,2,3",
269 "Counter": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
287 "Counter": "0,1,2,3",
296 "Counter": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3,4,5,6,7",
314 "Counter": "0,1,2,3,4,5,6,7",
323 "Counter": "0,1,2,3,4,5,6,7",
331 …"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was …
332 "Counter": "0,1,2,3,4,5,6,7",
334 "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
335 …"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS…
341 "Counter": "0,1,2,3,4,5,6,7",
350 "Counter": "0,1,2,3,4,5,6,7",
360 "Counter": "0,1,2,3",
369 "Counter": "0,1,2,3",
387 "Counter": "0,1,2,3,4,5,6,7",
396 "Counter": "0,1,2,3,4,5,6,7",
414 "Counter": "0,1,2,3,4,5,6,7",
424 "Counter": "0,1,2,3,4,5,6,7",
435 "Counter": "0,1,2,3,4,5,6,7",
444 "Counter": "0,1,2,3,4,5,6,7",
453 "Counter": "0,1,2,3,4,5,6,7",
462 "Counter": "0,1,2,3",
471 "Counter": "0,1,2,3",
480 "Counter": "0,1,2,3",
489 "Counter": "0,1,2,3",
498 "Counter": "0,1,2,3",
502 …"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream…
508 "Counter": "0,1,2,3",
518 "Counter": "0,1,2,3",
527 "Counter": "0,1,2,3,4,5,6,7",
538 "Counter": "0,1,2,3,4,5,6,7",
547 "Counter": "0,1,2,3,4,5,6,7",
556 "Counter": "0,1,2,3,4,5,6,7",
565 "Counter": "0,1,2,3,4,5,6,7",
574 "Counter": "0,1,2,3,4,5,6,7",
582 "Counter": "0,1,2,3,4,5,6,7",
591 "Counter": "0,1,2,3,4,5,6,7",
603 "Counter": "0,1,2,3,4,5,6,7",
612 "Counter": "Fixed counter 3",
614 … TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
620 "Counter": "0,1,2,3,4,5,6,7",
629 "Counter": "0,1,2,3",
638 "Counter": "0,1,2,3,4,5,6,7",
641 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
647 "Counter": "0,1,2,3,4,5,6,7",
650 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
655 "BriefDescription": "Number of uops executed on port 2 and 3",
656 "Counter": "0,1,2,3,4,5,6,7",
659 …r-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (R…
665 "Counter": "0,1,2,3,4,5,6,7",
668 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
674 "Counter": "0,1,2,3,4,5,6,7",
677 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
683 "Counter": "0,1,2,3,4,5,6,7",
686 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
692 "Counter": "0,1,2,3,4,5,6,7",
695 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
700 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
701 "Counter": "0,1,2,3,4,5,6,7",
705 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
710 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
711 "Counter": "0,1,2,3,4,5,6,7",
715 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
720 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
721 "Counter": "0,1,2,3,4,5,6,7",
722 "CounterMask": "3",
725 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
730 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
731 "Counter": "0,1,2,3,4,5,6,7",
735 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
740 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
741 "Counter": "0,1,2,3,4,5,6,7",
745 "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
750 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
751 "Counter": "0,1,2,3,4,5,6,7",
755 "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
760 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
761 "Counter": "0,1,2,3,4,5,6,7",
762 "CounterMask": "3",
765 "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
770 "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
771 "Counter": "0,1,2,3,4,5,6,7",
775 "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
781 "Counter": "0,1,2,3,4,5,6,7",
792 "Counter": "0,1,2,3,4,5,6,7",
800 "Counter": "0,1,2,3,4,5,6,7",
809 "Counter": "0,1,2,3,4,5,6,7",
818 "Counter": "0,1,2,3,4,5,6,7",
828 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
829 "Counter": "0,1,2,3,4,5,6,7",
838 "Counter": "0,1,2,3,4,5,6,7",
847 "Counter": "0,1,2,3,4,5,6,7",
858 "Counter": "0,1,2,3,4,5,6,7",