x86/icelakex/frontend.json

3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
48 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
60 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
108 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
113 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
120 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
125 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
132 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
137         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
144 …ter an interval where the front-end delivered no uops for a period of at least 2 cycles which was …
149 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
156 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
161 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
168 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
173 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
180 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
185 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
192 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
197 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
204 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
209 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
216 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
221 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
228 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
254 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
258 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
263 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
267 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
381 … to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
391 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…
396 …n": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not sta…
402 …red by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-e…